CN101599055A - Built-in isomerization CPU array system based on mutual pass bus - Google Patents
Built-in isomerization CPU array system based on mutual pass bus Download PDFInfo
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Abstract
The present invention relates to a kind of built-in isomerization CPU array system based on mutual pass bus, include some redundant subsystems, all redundant subsystems interconnect through closing bus mutually, form array; Redundant subsystems is to connect the outer storing module F of independent F lash, local high-speed internal memory module M, global information memory module T and peripheral hardware I/O interface module by a CPU to be formed; The CPU that system uses physical index to have nothing in common with each other; Closing bus mutually is 34 line system structures, includes 32 data lines, 1 clock lines and 1 function signal line, has the complete transmission agreement; The CPU of all redundant subsystems is connected by " logical and " mode its 34 universal ports with the mutual bus of closing, each CPU that is connected to mutual pass bus has unique identification marking and priority; A certain redundant subsystems in the system is the verification module, will be through most results of verification final output as system.When the software of certain redundant subsystems or hardware components sustain damage and can't operate as normal the time, can be rejected automatically and do not influenced other parts, system still has normal output.
Description
Technical field
The present invention relates to a kind of computer system, specifically a kind of built-in isomerization CPU array system based on mutual pass bus.
Background technology
Along with use increasingly extensive of embedded system with deepen continuously, controlling unit is being brought into play more and more important effect in the whole equipment that is embedded into.As the integrated circuit of controller core, now obtained the development of advancing by leaps and bounds.The raising of circuit level causes it more and more responsive to various electromagnetic energies.The broadening with frequency spectrum of continuing to increase along with the power of radiation sources such as various body electromagnetic radiations such as radar, communication facilities, navigator, add problems such as electromagnetic radiation that system self exists and static, make the control system of many types in its limited spatial dimension, be faced with complicated more and abominable electromagnetic environment.Highly Dian Zihua equipment is under environment like this, and its work effect can be subjected to very big influence naturally.When situation is comparatively serious, even its viability all can be subjected to certain threat.
Generally speaking, circuit level is high more, and galvanomagnetic effect is then more for obvious; Bearing of task is complicated more, and the consequence that all kinds of interference cause is just serious more.Under abominable electromagnetic environment, anti-interference, the anti-ability of injuring of embedded system mainly just is embodied in the anti-interference, anti-of integrated circuit (IC) chip and injures on the ability.And integrated circuit itself also is relatively poor for the resistivity of the electromagnetic interference (EMI) in the applied environment.
The common anti-interference measure of integrated circuit is strengthened shielding exactly and is improved wiring structure etc., to reduce the influence of external electromagnetic environment to its internal circuit as far as possible.But along with the continuous expansion of electromagnetic interference (EMI) scale, form is complicated all the more, and many tradition and effective electromagnetic protection measure and anti-interference means can be subjected to many restrictions, usually are difficult to prove effective.
Summary of the invention
Purpose of the present invention just provides a kind of built-in isomerization CPU array system based on mutual pass bus, to solve integrated circuit anti-interference and the limited problem of electromagnetic protection measure, thereby make total system can satisfy multiple safe operation requirement on different aspects, the security and the reliability of system are improved.
The present invention is achieved in that a kind of built-in isomerization CPU array system based on mutual pass bus, and this system includes some redundant subsystems, and all redundant subsystems all interconnect through closing bus mutually, form array structure;
Described redundant subsystems is to connect the outer storing module F of independent F lash, local high-speed internal memory module M, global information memory module T and peripheral hardware I/O interface module by a CPU;
The type of used CPU or physical index are different in each redundant subsystems;
Described mutual pass bus is 34 line system bus structure, includes 32 data line DATA, 1 clock lines CLK and 1 function signal line FUN, has the complete transmission agreement;
The CPU of all redundant subsystems is connected by " logical and " mode its 34 universal ports with the described mutual pass bus of 34 line systems, each device that is connected to described mutual pass bus all has unique identification marking and priority;
In system, there is a redundant subsystems to be configured as the verification module, the most results that finally are output as the process verification of system.
Redundant subsystems of the present invention is moved independently operating system respectively according to many host modes.
Redundant subsystems of the present invention is configured as main many auxilliary modes, operates under the same operating system.
The clock employing of the clock line CLK of mutual pass of the present invention bus is dynamically obtained and the main hero of biography is sent out pattern, for many host computer control, has priority able to programme, single data word verification, clock check, collision detection and arbitration mechanism.
The priority of redundant subsystems of the present invention is dynamically changeable, both can be same level, also can be different stage.All redundant subsystems all close mutually bus connect under mode by programming the priority of data transmission is selected, promptly user program can carry out determining of each cpu data transmission priority by programming mode.
Essence of the present invention be exactly realized a kind of be based upon on the bus basis, mutual pass, by array structure and system that a plurality of isomery CPU are formed, this isomery CPU array system can move according to the embedded computer mode.
Redundant subsystems in the isomery CPU array of the present invention can be used same operating system, or same operating system is used respectively in the CPU of independent operating, i.e. the operating system of the same type of parallel running.In addition, this isomery CPU array can also move different operating system respectively according to many host modes.Certainly, all redundant subsystems of isomery CPU array of the present invention are the same application programs of operation at application finally.
Because the type difference of CPU, the implementation of its logical circuit, mode of operation, instruction set, software environment and programming mode etc. also just all have difference.Just because of various isomery CPU at principle design (CISC and RISC, Harvard structure and von Neumann structure etc.), implementation (ASIC and FPGA etc.) and semiconductor material (CMOS and ambipolar etc.) go up and have bigger otherness, makes it also different for tolerance degree that dissimilar working environments (for example complex electromagnetic environment) disturb.Therefore, in a specific abominable working environment,,, just can obtain operation result as long as a CPU is arranged in the array also in operation so long as not damage of overall importance.
Because the computer system that this mode constitutes relies on each inner CPU module can set up the pattern of a kind of " parallel " operation, mutual verification is also carried out error-detecting and restriction, therefore, general performance is a work system highly reliably, becomes the effective preventive means that control system is taked under rugged surroundings such as electromagnetic interference (EMI).
The present invention just is being based on this design philosophy and requirement designs; and on the basis of this means of defence and structure; utilize the structural advantage of brand-new isomery CPU array; can further strengthen the interference rejection ability of various types of core control systems; the system that makes can finish the work that can only finish usually under home under rugged surroundings, can prolong the whole service life of system greatly thus.
Electromagnetic protection technology based on " isomery CPU array " and " closing bus mutually " notion proposed by the invention, be to consider after the inevitable property of system's chips damage, be based upon the electromagnetic protection new model of being carried out on the architecture basics of " guaranteeing the quality ", " seeking survival " with fault-tolerant with quantity.Its objective is the mode of wishing by " allomeric function localization ", make overall formation " tolerance " residing rugged surroundings to a certain extent of control system, get muddled or even after segment chip occurs by the situation that injures the part, collapse takes place certain operating system, still can not rely on extraneous intervention and fault-tolerant operation at its state that becomes any working routine, each system of " part ".
Different according to actual application environment and protection requirements, the CPU in each redundant subsystems of the present invention adopts different frameworks.Utilize isomery CPU array structure and close being connected of bus mutually, the problem that had been faced in the time of both can having solved the communication of interior data high efficient and reliable, can reduce " common cause failure " in the isomorphism redundant system again to the influence that system reliability caused, thereby improve the reliability of redundant system effectively.
The invention enables the novel protection imagination of under rugged surroundings control system one-level to become possibility technically, and make guarded control system finally can satisfy the requirement of the multiple safe operation on different aspects.Therefore, the present invention is the computer system that strong, safe and reliable to operation, the comprehensive viability of a kind of electromagnetic immunity ability significantly improves.
Design feature of the present invention is:
1, has a plurality of dissimilar embedded type CPU chips and constitute redundant subsystems respectively, under the mutual pass of special use bus connects, form basic array structure.Each device that is connected to bus all has unique address, can be set by software programming.Wherein, some redundant subsystems must be configured as the verification module.
2, these redundant subsystems both can be moved independently operating system respectively according to many host modes, can be configured as main many auxilliary modes again, operated under the same operating system.The same application program of the final operation of all CPU according to same input, obtains output separately in the array.At this moment, these results under normal circumstances should be able to be in full accord.
3, all redundant subsystems all interconnect through closing bus mutually, and its data line separates with control line for parallel 32.Control signal wire has only two, and one is clock line CLK, and one is function signal line FUN.Bus clock adopts " dynamically obtaining " and " the main hero of biography is sent out " pattern, can supply many host computer control, has priority programmable, single data word verification, clock check, collision detection and efficient arbitration mechanism.
4, the priority of redundant subsystems is dynamically changeable.Can be equal to, also can be not wait, and all mode by programming is selected under the bus environment of mutual pass, and promptly user program can carry out determining of each cpu data transmission priority by programming mode.In case a certain CPU sustains damage or internal processes causes confusion, its output result must be inconsistent with the output of other module, but do not influence the operate as normal of other CPU.At this moment, different result can be detected by the verification module of system and conductively-closed (or title " rejecting ").So, the most results that finally are output as the process verification of system.
The present invention is the loosely-coupled enterprise schema of a kind of key modules high degree of autonomy and system.This structure had both helped reducing the bandwidth pressure of shared bus, can improve overall system efficiency and degree of parallelism again, also helped each redundant subsystems of isolation, prevented that risk of disturbance from spreading, and had improved the security of system thus.
Therefore, under any circumstance, as long as most CPU can have normal output, system just can export normal result.The fault-tolerant operation mode that Here it is " multimode redundancy ".Different with traditional parallel running mode, the advantage of this array way maximum that is made of separate CPU is to move the operating system of dissimilar or different editions, and on this basis, operation simultaneously compiling is finished under corresponding operating system environment respectively, have the application program of identical function and close working time.This is the redundant software of the isomery CPU array of the present invention mode that " runs parallel ".
The purpose of this " running parallel " based on isomery CPU array is not that hope improves whole system operation speed by the quantity that improves CPU, but increases the functional reliability of its system by the mode of mutual verification.Be general high reliability computer system if it is expanded, the present invention also can realize its " two similarities and differences " pattern equally, i.e. isomery CPU, and foreign peoples's operating system, running simultaneously is with enjoying Peripheral Interface.
Description of drawings
Fig. 1 is a system hardware building-block of logic of the present invention.
Clock synchronization figure when Fig. 2 is data transmission.
Fig. 3 is isomery CPU array and the mutual hardware logic structure figure that closes bus that is made of 4 redundant subsystems.
Fig. 4 is data word transmission form figure.
Fig. 5 is startup and the stop condition figure that closes bus mutually.
Fig. 6 is address data word format figure.
Fig. 7 is bus acknowledge signal figure.
Fig. 8 is the data transmission format figure of bus.
Fig. 9 is the bus response diagram.
Embodiment
The basic hardware configuration of the present invention as shown in Figure 1, be to connect the outer storing module F of independent F lash, local high-speed internal memory module M, global information memory module T and peripheral hardware I/O interface module, constitute a redundant subsystems by cpu chip with physical indexs such as unlike material, type, clock frequency and electromagnetic susceptibilities.Can hold 32 redundant subsystems in the array of the present invention at most, the CPU of all redundant subsystems is connected by " logical and " mode its 34 universal ports with the mutual pass bus of 34 line systems.This bus has 32 data line DATA[0..31], 1 clock lines CLK and 1 function signal line FUN, can be in order to each redundant subsystems is connected to become one according to the CPU array of various modes coordinated operation.This is the basic model of the present invention's " isomery array ".Information transmission between the CPU in each redundant subsystems relies on the mutual bus of closing to carry out, and each device all has unique Address Recognition and priority.
Utilize the detailed process of closing bus transfer data mutually as follows:
At first be the dynamic assignment of system address: after the normal startup of system, each redundant subsystems that is connected to mutual pass bus has the start mark and the initial priority of an acquiescence, and is kept in the global information memory module, forms the Initial master label table.Utilize executive routine to distribute address and priority for each redundant subsystems automatically then.Executive routine uses the pseudorandom method, and the redundant subsystems of each normal operation produces one 32 pseudo random number by pseudo-random algorithm, is broadcast to remaining redundant subsystems successively by its order in closing bus Initial master label table mutually.Like this, each redundant subsystems has been preserved the pseudo random number that all redundant subsystems produce in its global information memory module T, and its ordering back is preserved.The priority of the redundant subsystems that the pseudo random number that unified regulation produces is big is the highest; And the like, the priority of the redundant subsystems of generation pseudo random number minimum is minimum.Then, distribute the address according to priority for each redundant subsystems.By such " initialization " process, with regard to the dynamic assignment of address in the energy realization system.Sharpest edges of the dynamic assignment of this system address are exactly can be in the long-term use of system, and the balance that realizes load is heavily divided in the address when powering on by each system.
Next is choosing of verification module: these redundant subsystems in the system work in many master modes, form the multi-mode redundant structure.Choose a certain redundant subsystems as the verification module by Automatic Program, for example select for use the highest redundant subsystems of priority to serve as the verification module.When the verification module broke down, priority time high redundant subsystems replaces automatically served as the verification module, and the like.With respect to traditional built-in check mode, the dynamically selected method of verification module has more superiority in this multimode redundant system, in case can solve the impaired then restriction problem that can't repair of built-in check module preferably.Redundant resource can be effectively utilized like this, system availability can be improved again.The verification module is responsible for the result of the redundant task moved on other redundant subsystems of verification, and compile by of the operation result unification of mutual pass bus with redundant task on other redundant subsystems, notify corresponding redundant subsystems output result after the verification, perhaps directly control the peripheral hardware running.The verification module also can be collected the ruuning situation of all redundant subsystems in the total system when carrying out information communication with other redundant subsystems, and it is broadcast to other all redundant subsystems.Its fundamental purpose is, in case certain redundant subsystems breaks down, other redundant subsystems just can in time know and no longer carry out work such as exchanges data with it, promptly automatically with its shielding and reject its corresponding data or result.
Moreover be the method for synchronization of clock: as shown in Figure 2, clock synchronization connects mutual pass bus interface by " logical and " mode and carries out to clock line CLK.That is to say, close the level switching from high to low of the clock line CLK of bus mutually, can make each redundant subsystems begin to count their low-level period respectively, in case and the clock of redundant subsystems itself becomes low level, it can make the clock line CLK of mutual pass bus keep this state to arrive high level up to the clock of this redundant subsystems.But if when having still be in low-level period clock this moment of another redundant subsystems, then the switching from low to high of this clock can not change the state of the clock line CLK of mutual pass bus.That is to say that the clock line CLK that closes bus is mutually had that the redundant subsystems of long low-level period remains low level, the short redundant subsystems of low-level period then is in the waiting status that clock is a high level at this moment.After all redundant subsystems finished to their low-level period counting, the low level of closing the clock line CLK of bus mutually was released, and is transformed into high level thereupon.
Like this, the low-level period of generation synchronous clock is determined that by the longest device of low level clock period in the redundant subsystems of carrying out data interaction high level period is determined by the shortest device of high level clock period in the array.In this case, clock frequency is with this moment, to take that minimum transmission subsystem of Bus Speed consistent.This promptly carries out the basic meaning that the clock master sends out by the main subsystem that passes, and also can abbreviate " the main hero of biography is sent out " pattern as.
As previously mentioned, the address of redundant subsystems is a dynamic assignment, and chooses the highest redundant subsystems of priority level as the verification module through Automatic Program.Bus Clock Rate is unfixing in the array, and depends on that fully a certain moment takies two redundant subsystems that mutual pass bus is carried out exchanges data.Strictly speaking, depend on the side that both medium frequencys are lower exactly.So, its high transmission speed is according to closing the switching of different redundant subsystems on the bus mutually and changing at any time with efficient, both can satisfy the clock request that a certain redundant subsystems has to use lower frequency, and can satisfy again and wish the high as far as possible requirement of whole mutual pass Bus Clock Rate.The operation conditions of all redundant subsystems is all interrelated, in the hope of realizing that the overall operation efficiency of pass bus is the highest mutually in the whole isomery CPU array.This i.e. the basic meaning of " closing bus mutually ".
Difference according to demand, each CPU in the system of the present invention both can be identical framework, also can be different frameworks; Both the identical operations system can be used, also different operating system can be used.Wherein, the situation of different frameworks is more complicated, is called " isomery CPU array ".
So-called " isomery CPU array ", just being to use all different cpu chip of physical indexs such as material, type, structure and electromagnetic susceptibility to make up one can be according to the CPU array of various modes coordinated operation.These CPU both can be configured to be many main working methods, also can be configured to the working method into " is main how auxilliary "; The setting of the priority of all CPU is selected by the software programming mode.
And in case different CPU and operating system are adopted in consideration, then the high speed communication technology between CPU just may become a principal element of system for restricting performance.For this reason, the present invention is the bus structure of a kind of " closing mutually " formula that adopted CPU array design that the isomery mode constitutes specially, to satisfy its practical requirement.
So-called " closing bus mutually ", be a kind of based on CPU isomery array parallel, at a high speed, special-purpose many host buses with complete agreement.This bus adopts 32 position datawires and control line separated structures, has able to programme, single data word verification scheme of many host computer control, priority and the running status characteristics that are mutually related.Bus Clock Rate occupies module and dynamic adjustable according to different buses, it is unique that each is connected to the address of devices of bus, and can need not the logic connecting circuit of types such as address decoder by program setting, and then can according to collision detection and efficiently the priority arbitration mode solve the bus contention problem.
When the mutual pass bus among the present invention compares with existing other embedded system bus technology, have faster than universal serial bus speed, than the clear superiority of existing parallel bus flexible working mode.By finishing the formulation of dedicated transmissions agreement, make user program in whole array environment, to carry out determining of each cpu data transmission priority in programmable mode.
Embodiment:
Fig. 3 has shown isomery CPU array that is made of 4 redundant subsystems and the hardware logic structure that closes bus mutually.In this array, each CPU connects the outer storing module F of independent F lash, local high-speed internal memory module M, global information memory module T and peripheral hardware I/O interface module, constitutes a redundant subsystems.All redundant subsystems adopt the mode of " logical and " to be articulated on the bus of mutual pass, form the isomery CPU array system of one four redundant subsystems thus.
This array system can use same operating system, also same operating system can be used respectively in the CPU of independent operating, and promptly the operating system of the same type of parallel running also can be moved different operating system respectively according to many host modes.Yet all redundant subsystems of this array are had in the end in the same application program of application operation most.
Under normal circumstances, this array system should be able to obtain identical output result according to same input.In order to satisfy the requirement of high reliability, serve as the verification module according to a certain redundant subsystems working properly of program selecting in advance.This verification module is responsible for obtaining the output result of every redundant task, and notice peripheral hardware control module carries out final system's output after verification succeeds.If a certain redundant subsystems sustains damage or internal processes (comprising operating system) causes confusion, then its abnormal system output can be found immediately by the contrast of verification module.But this error situation does not influence the operate as normal of other redundant subsystems.In this case, the verification module is rejected inconsistent result, and other redundant subsystems is exported as net result through verification and consistent result.
As previously mentioned, the mutual pass bus among the present invention is the bus of main frame more than, and being used for plate, to carry many CPU interconnected, promptly can connect device more than an energy control bus on bus.Information transmission between CPU is to rely on bus to carry out, and each device all has a unique Address Recognition.And can be as a transmitter or receiver.Except as transmitter and the receiver, device also can be counted as main frame or slave when carrying out data transmission.Main frame is the data transmission terminal of initialization bus, and also is the device that produces the synchronizing clock signals that allows transmission.This moment, any device that is addressed all was considered to slave.
Mutual pass bus among the present invention has been given prominence to the relation of the main frame-slave and the receiver-transmitter of bus, and these relations and non-persistent, only by the direction decision of data transmission at that time.All circuits all are two-way, all are connected to positive supply voltage through a current source or pull-up resistor.When mutual pass bus was idle, all circuits all were high level.The device output stage that is connected to mutual pass bus must be open-drain or open-collector structure, so that carry out the function of " logical and ".
A complete data transmission procedure in the native system is: startup, arbitration, addressing, transmit, stop.Be described in detail below.
1, suppose that microcontroller A will send information to microcontroller B, its data transmission procedure is:
A, microcontroller A (main frame) addressing microcontroller B (slave); B, microcontroller A (main frame-transmitter) send data to microcontroller B (slave-receiver); C, microcontroller A stop transmission.
If 2 microcontroller A want to receive information from microcontroller B, its data transmission procedure is:
A, microcontroller A (main frame) addressing microcontroller B (slave); B, microcontroller A (main frame-receiver) receive data from microcontroller B (slave-transmitter); C, microcontroller A stop transmission.
As shown in Figure 4, data word of the every transmission of the main frame of isomery CPU array of the present invention just produces a time clock.Data are only effective in the high level period of clock.So the data on the DATA line must keep stable in the high level period of clock.The high level of data line or low level state only could change when the clock signal of clock line CLK is low level.
The startup of pass bus and stop condition are defined within startup (frame of broken lines S) and stop to see Fig. 5 under the situation of (frame of broken lines P) mutually.When clock line CLK was high level, function signal line FUN switched to low level from high level.This situation is represented initial conditions.When clock line CLK was high level, function signal line FUN switched to high level from low level.This situation is represented stop condition.Startup and stop condition are generally produced by main frame.Close bus mutually and after entry condition, considered to be in busy state; After certain period of stop condition, close bus mutually and be considered to be in once more idle condition.
Generally speaking, in multi-CPU system, the arbitration of bus is the key that system can stable operation.Mutual pass bus in the isomery CPU array of the present invention is public by total system.Main frame must start transmission the bus free time.Two or more main frames may apply for taking bus simultaneously, and consequently can only produce the initial conditions of a regulation on bus.First data word that formally begins to transmit also is its priority arbitration for the mark of each main frame.Institute's underlined use " contraposition " coded system, its sharpest edges are that step-by-step carries out " logical and " computing, directly distinguish the size of its numerical value, so that the realization of arbitration circuit makes its used time accomplish the shortest.But the main frame that the regulation mark value is lower has higher priority arbitration, and the distribution of its mark code value is as shown in table 1.
Table 1: main frame mark allocation table
| The mark allocation table | Priority arbitration |
| 0000 0000 0000 0000 0000 0000 0000 0000 | Broadcast address (reservation) |
| 0000 0000 0000 0000 0000 0000 0000 0001 | 1 |
| 0000 0000 0000 0000 0000 0000 0000 0011 | 2 |
| 0000 0000 0000 0000 0000 0000 0000 0111 | 3 |
| 0000 0000 0000 0000 0000 0000 0000 1111 | 4 |
| 0000 0000 0000 0000 0000 0000 0001 1111 | 5 |
| 0000 0000 0000 0000 0000 0000 0011 1111 | 6 |
| 0000 0000 0000 0000 0000 0000 0111 1111 | 7 |
| 0000 0000 0000 0000 0000 0000 1111 1111 | 8 |
| 0000 0000 0000 0000 0000 0001 1111 1111 | 9 |
| 0000 0000 0000 0000 0000 0011 1111 1111 | 10 |
| 0000 0000 0000 0000 0000 0111 1111 1111 | 11 |
| 0000 0000 0000 0000 0000 1111 1111 1111 | 12 |
| 0000 0000 0000 0000 0001 1111 1111 1111 | 13 |
| 0000 0000 0000 0000 0011 1111 1111 1111 | 14 |
| 0000 0000 0000 0000 0111 1111 1111 1111 | 15 |
| 0000 0000 0000 0000 1111 1111 1111 1111 | 16 |
| 0000 0000 0000 0001 1111 1111 1111 1111 | 17 |
| 0000 0000 0000 0011 1111 1111 1111 1111 | 18 |
| 0000 0000 0000 0111 1111 1111 1111 1111 | 19 |
| 0000 0000 0000 1111 1111 1111 1111 1111 | 20 |
| 0000 0000 0001 1111 1111 1111 1111 1111 | 21 |
| 0000 0000 0011 1111 1111 1111 1111 1111 | 22 |
| 0000 0000 0111 1111 1111 1111 1111 1111 | 23 |
| 0000 0000 1111 1111 1111 1111 1111 1111 | 24 |
| 0000 0001 1111 1111 1111 1111 1111 1111 | 25 |
| 0000 0011 1111 1111 1111 1111 1111 1111 | 26 |
| 0000 0111 1111 1111 1111 1111 1111 1111 | 27 |
| 0000 1111 1111 1111 1111 1111 1111 1111 | 28 |
| 0001 1111 1111 1111 1111 1111 1111 1111 | 29 |
| 0011 1111 1111 1111 1111 1111 1111 1111 | 30 |
| 0111 1111 1111 1111 1111 1111 1111 1111 | 31 |
| 1111 1111 1111 1111 1111 1111 1111 1111 | 32 |
Because data line DATA[0..31] be to rely on " logical and " junctor highway interface on the bus of mutual pass, so in each data bit on the data line DATA after being changed to 0 by certain main frame, other main frame can not be changed to 1 with it.Aspect the main frame arbitration, when first data word of transmission, the main frame of filing of the award all will read simultaneously.The main frame competition failure that the data word that reads is different with the mark of oneself loses bus control right.And the data word that the reads main frame identical with own mark arbitrated successfully, thereby obtains bus control right.The main frame that obtains bus control right produces first answer signal voluntarily to be finished with expression arbitration this time.
In isomery CPU array, after a certain main frame obtained bus control right, first data word was used for the addressing slave addresses, had wherein also comprised the address and the read-write control bit of main frame.Its address data word format as shown in Figure 6.
Data line DATA[0] be read-write control bit (R/W), ' 0 ' expression sends (writing), ' 1 ' expression request msg (reading).
Data line DATA[1..5] the expression host address.Corresponding to 32 right of priority marks, can be array 32 host addresses are provided.
Data line DATA[6..10] the expression slave addresses.In fact, after main frame was determined, system can only 31 slaves of addressing.
Other everybody conduct of data line keeps the position, can supply to carry out services such as system's global information issue.
When be addressed after this information of machine testing, on function signal line FUN, produce an answer signal, expression main frame, slave addressing success are promptly carried out " shaking hands ", as shown in Figure 7.
Send to data line DATA[0..31] on each data word can be the 1--32 position.The number of words that each transmission can send is unrestricted, but must be with sending out a response bit on signal wire FUN after each data word.If from confidential after finishing some other functions (for example in-line interrupt service routine) could receive or send next complete data word, then can make clock line CLK keep low level, force main frame to enter waiting status.After slave is ready to receive next data word and discharges clock line CLK, data transmission will be proceeded, as shown in Figure 8.
Data transmission must be carried out under the situation of response, and relevant response time clock is produced by main frame.During the time clock of response, transmitter discharges data line DATA[0..31], make it to be high level.At this moment, receiver must drag down the level of function signal line FUN, makes it keep stable low level between the high period of this time clock, as shown in Figure 9.
When slave can not respond slave addresses (for example it carrying out some real-time functions can not receive or send), slave must make data line DATA keep high level.Main frame produces a stop condition subsequently, stops transmission or produce repeating initial conditions, begins new transmission.
If the slave receiver has responded slave addresses, but can not receive the more data byte after having transmitted a period of time, main frame must stop transmission again.In addition, the main frame receiver does not produce corresponding response after last data word that allows slave generation data, notify slave transmitter data end of transmission (EOT) then.Both of these case does not all produce response with slave and represents after a data word transmission.Slave makes function signal line FUN keep high level, and main frame just can produce one and stop or repeating initial conditions.
As can be seen, the present invention be aim at solve embedded computer system under rugged surroundings the safe operation problem and design.Based on the embedded type CPU of isomery, form some redundant subsystems.All redundant subsystems connect through closing bus mutually, form isomery formula CPU array system.Wherein, the priority of each redundant subsystems can be set flexibly by software programming.In case certain CPU sustains damage or internal processes causes confusion, just can be detected and be rejected by the verification module of system because of its results abnormity.At this moment, do not influence the normal operation of other redundant subsystems, the final output of system still is the most results through verification.If the verification module of system sustains damage, then system must dispose the verification module immediately separately.Although the output of system has in short-term and interrupts in this case, can be recovered rapidly, so that whole array can continue operate as normal.
Claims (4)
1, a kind of built-in isomerization CPU array system based on mutual pass bus, it is characterized in that: this system includes some redundant subsystems, and all redundant subsystems all interconnect through closing bus mutually, form array structure;
Described redundant subsystems is to connect the outer storing module F of independent F lash, local high-speed internal memory module M, global information memory module T and peripheral hardware I/O interface module by a CPU;
The type of used CPU or physical index are different in each redundant subsystems;
Described mutual pass bus is 34 line system bus structure, includes 32 data line DATA, 1 clock lines CLK and 1 function signal line FUN, has the complete transmission agreement;
The CPU of all redundant subsystems is connected by " logical and " mode its 34 universal ports with the described mutual pass bus of 34 line systems, each device that is connected to described mutual pass bus all has unique identification marking and priority;
In system, there is a redundant subsystems to be configured as the verification module, the most results that finally are output as the process verification of system.
2, the built-in isomerization CPU array system based on mutual pass bus according to claim 1 is characterized in that described redundant subsystems moves independently operating system respectively according to many host modes.
3, the built-in isomerization CPU array system based on mutual pass bus according to claim 1 is characterized in that described redundant subsystems is configured to main many auxilliary modes, operates under the same operating system.
4, the built-in isomerization CPU array system based on mutual pass bus according to claim 1 and 2, it is characterized in that having priority able to programme, single data word verification, clock check, collision detection and arbitration mechanism, the clock employing of the synchronous clock line CLK of described mutual pass bus is dynamically obtained and the main hero of biography is sent out pattern.
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| EP1077412A3 (en) * | 1999-08-16 | 2004-12-15 | Hewlett-Packard Company, A Delaware Corporation | Bus system having improved control process |
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