CN103855202A - IGBT, celluar structure of IGBT and IGBT forming method - Google Patents
IGBT, celluar structure of IGBT and IGBT forming method Download PDFInfo
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- CN103855202A CN103855202A CN201210520131.3A CN201210520131A CN103855202A CN 103855202 A CN103855202 A CN 103855202A CN 201210520131 A CN201210520131 A CN 201210520131A CN 103855202 A CN103855202 A CN 103855202A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims description 87
- 239000004065 semiconductor Substances 0.000 claims description 84
- 230000015572 biosynthetic process Effects 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 17
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 6
- 229910001439 antimony ion Inorganic materials 0.000 claims description 4
- 238000002207 thermal evaporation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 38
- 150000002500 ions Chemical class 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention discloses an IGBT, a celluar structure of the IGBT and an IGBT forming method. The celluar structure comprises a first drift region, a second drift region which is placed on the lower surface of the first drift region, at least one doping region placed between the first drift region and the second drift region, and a collector region which is placed on one side, deviating from the doping region, of the second drift region. The doping type and the concentration of the first drift region and the doping type and the concentration of the second drift region are both the same. The doping type of the doping region is the same as the doping type of the second drift region, and the doping concentration of the doping region is larger than the doping concentration of the second drift region. The doping type of the collector region is opposite to the doping type of the second drift region, so that the IGBT has a good trade-off relation between conduction loss and switching loss, and the overall performance is high.
Description
Technical field
The present invention relates to semiconductor device processing technology field, relate in particular to the formation method of IGBT and structure cell thereof and IGBT a kind of.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, be called for short IGBT) the compound full-control type voltage driven type power semiconductor that formed by double pole triode (BJT) and insulating gate type field effect tube (MOSFET), the high input impedance and the power transistor that have MOSFET device concurrently (are huge transistor, be called for short GTR) the advantage of low conduction voltage drop two aspects, reduce because IGBT has advantages of the little and saturation pressure of driving power, IGBT is widely applied to every field as a kind of novel power electronic device at present.
IGBT mainly comprises that in vertical structure non-punch through IGBT (being called for short NPT-IGBT) and punch IGBT(are called for short PT-IGBT).The advantages such as wherein, it is simple that non-punch through IGBT has manufacture craft, and production cost is low, and good safe voltage characteristic, the conducting voltage with positive temperature coefficient and switching loss are low.But its conduction loss is larger.And compared to non-punch through IGBT, punch IGBT has lower conduction loss, but its switching loss is larger.
Because described IGBT exists switch and conducting two states in the time specifically applying, and between switching loss and conduction loss, exist this those long relations that disappear, cause IGBT of the prior art or switching loss less, conduction loss is larger, or conduction loss is less, switching loss is larger, and in prior art, the tradeoff between switching loss and the conduction loss of IGBT is poor.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of IGBT and structure cell thereof, and the formation method of IGBT.IGBT provided by the present invention, has the tradeoff between good switching loss and conduction loss, has improved the overall performance of IGBT.
For addressing the above problem, the embodiment of the present invention provides following technical scheme:
A kind of IGBT structure cell, comprising: the first drift region and the second drift region that is positioned at described the first drift region lower surface, and described the first drift region is all identical with doping type and the concentration of described the second drift region; At least one doped region between described the first drift region and the second drift region, the doping type of described doped region is identical with the doping type of described the second drift region, and the doping content of described doped region is greater than the doping content of described the second drift region; Be positioned at described the second drift region and deviate from Yi Ce collector region, described doped region, the doping type of described collector region is contrary with the doping type of described the second drift region.
Preferably, when the number of described doped region is at least two, adjacent doped region is spaced apart.
Preferably, the doping ion of described doped region is arsenic ion or antimony ion.
Preferably, described doped region doping content scope is 5*10
15cm
-3-9*10
17cm
-3, comprise endpoint value.
Preferably, the number scope of described doped region is 2-4, comprises endpoint value.
Preferably, described doped region is uniformly distributed.
Preferably, the spacing between adjacent doped region be described doped region width 1-3 doubly.
Preferably, the depth bounds of described doped region is 3 μ m-8 μ m, comprises endpoint value.
Preferably, the spacing range of described doped region and described collector region is 4 μ m-9 μ m, comprises endpoint value.
A kind of IGBT, comprises the structure cell described at least one above-mentioned any one.
A formation method of IGBT, comprising: the first Semiconductor substrate is provided, and described the first Semiconductor substrate comprises the first drift region; In the lower surface of described the first Semiconductor substrate, form at least one doped region, the doping type of described doped region is identical with the doping type of described the first drift region, and the doping content of described doped region is greater than the doping content of described the first drift region; Form the second Semiconductor substrate at described the first Semiconductor substrate lower surface, described the second Semiconductor substrate is all identical with doping type and the concentration of described the first Semiconductor substrate, and described the second Semiconductor substrate comprises the second drift region, described the second drift region covers described the first drift region and described doped region completely; In described the second Semiconductor substrate lower surface, form collector region.
Preferably, in the lower surface of described the first Semiconductor substrate, forming at least one doped region comprises: in described the first semiconductor lower surface, form oxide layer; In described oxide layer, form etching window, described etching window is corresponding with the position of doped region to be formed in described the first Semiconductor substrate; Take the oxide layer with etching window as mask, in described the first Semiconductor substrate, form at least one doped region.
Preferably, the formation technique of described doped region is Implantation or thermal deposition.
Preferably, when the formation technique of described doped region is Implantation, the Implantation Energy of doping ion is less than 40keV.
Preferably, the formation technique of described the second Semiconductor substrate is extension.
Preferably, the thickness range of described the second Semiconductor substrate is 5 μ m-10 μ m, comprises endpoint value.
Compared with prior art, technique scheme has the following advantages:
The technical scheme that the embodiment of the present invention provides, comprise at least one doped region between described the first drift region and the second drift region, the doping type of described doped region is identical with the doping type of described drift region, and the doping content of described doped region is greater than the doping content of described drift region, thereby make in the time bearing identical puncture voltage, the IGBT providing in technical solution of the present invention, compared to traditional non-punch through IGBT, has reduced conduction loss; Compared to punch IGBT, reduce turn-off power loss, thereby optimized the conduction loss of IGBT and the tradeoff of switching loss.
In the time having identical thickness of detector, the IGBT providing in technical solution of the present invention, compared to traditional non-punch through IGBT, reduce turn-off power loss, and compared to traditional punch IGBT, reduced conduction loss, thereby the conduction loss of IGBT and the tradeoff of switching loss are optimized.
Therefore, IGBT provided by the present invention has the tradeoff between good conduction loss and switching loss, and overall performance is higher.
Accompanying drawing explanation
Fig. 1 is the structural representation of non-punch through IGBT in prior art;
Fig. 2 is the structural representation of punch IGBT in prior art;
The structural representation of the IGBT that Fig. 3 provides for the embodiment of the present invention.
Embodiment
In prior art, punch IGBT and non-punch through IGBT include multiple structure cells.As shown in Figure 1, the structure cell of non-punch through IGBT mainly comprises: the substrate of N-type light dope (N-), be positioned at the Facad structure of the substrate face of described N-type light dope (N-), and be positioned at the structure of the substrate back of described N-type light dope (N-).Wherein, described Facad structure comprises: the grid structure 104 that is positioned at the substrate top surface of described N-type light dope (N-); The P type well region 102(that is positioned at N-substrate top surface is generally P type light dope), be positioned at the N-type source region 103 on P type well region 102 surfaces; Be positioned at the lip-deep source electrode 105 in P type well region 102 and N-type source region 103.
Described structure comprises: be positioned at the P type heavy doping collector region 106 of N-substrate back, be positioned at the collector electrode 107 on 106 surfaces, collector region.The region of removing Facad structure and structure in the substrate of described N-type light dope (N-) is drift region 101.
As shown in Figure 2, compared to non-punch through IGBT, the structure cell of punch IGBT also comprises: be formed at the N-type resilient coating 108 between described drift region 101 and collector region 106.
Inventor studies discovery, under the condition of identical thickness of detector, the injection efficiency of described non-punch through IGBT collector region 106 is high, make the conduction loss of described non-punch through IGBT little, but under on off state, the shutoff tail current of described non-punch through IGBT is larger, make that its turn-off power loss is large and safe voltage scope is less, while causing it as switch application, have certain defect, overall performance is poor.
Compared to non-punch through IGBT, under the condition of identical thickness of detector, due to the existence of described resilient coating 108, the injection efficiency of described punch IGBT collector region 106 is low, there is higher puncture voltage, although reduced the turn-off power loss of described punch IGBT, caused the conduction loss of described punch IGBT larger.
In the time bearing identical puncture voltage, the switching loss of described non-punch through IGBT is smaller, but its integral thickness is larger, thereby makes its conduction voltage drop larger, and conduction loss is larger.Compared to non-punch through IGBT, the drift region of described punch IGBT is thinner, and conduction loss is smaller, but its turn-off power loss is larger.And, in the manufacture craft of the IGBT of punch described in prior art, need the drift region that extension is very thick, thereby greatly increased described punch IGBT cost of manufacture.
On basis based on above-mentioned research, the invention provides a kind of IGBT and structure cell thereof, and the formation method of IGBT, make IGBT provided by the present invention, there is the tradeoff between good switching loss and conduction loss, improve the overall performance of IGBT.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.The embodiment of the present invention describes as planar gate structure IGBT as example take described IGBT, but is equally applicable to trench gate structure IGBT, and the present invention does not limit this.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
Embodiment mono-:
The embodiment of the present invention provides a kind of IGBT structure cell, and comprises the IGBT of at least one this structure cell.As shown in Figure 3, the IGBT structure cell that the embodiment of the present invention provides comprises:
Drift region, described drift region comprises the first drift region 301 and the second drift region 302 that is positioned at described the first drift region 301 lower surfaces, described the first drift region 301 is all identical with doping type and the concentration of described the second drift region 302;
At least one doped region 303 between described the first drift region 301 and the second drift region 302, the doping type of described doped region 303 is identical with the doping type of described the second drift region, and the doping content of described doped region 303 is greater than the doping content of described the second drift region;
Be positioned at the collector region 304 that described the second drift region 302 deviates from described doped region 303 1 sides, the doping type of described collector region 304 is contrary with the doping type of described the second drift region.
In addition, the embodiment of the present invention also comprises: be positioned at the Facad structure in front, described drift region, described Facad structure comprises the grid structure 305 that is positioned at described drift region upper surface; Be positioned at the well region 306 of the drift region upper surface of described grid structure 305 both sides; Be positioned at the source region 307 of described well region 306 upper surfaces; Be positioned at described source region 307 upper surfaces, and the source electrode 308 being electrically connected with described source region 307.Wherein, between described source electrode 308 and described grid structure 305, be also formed with passivation layer.
In one embodiment of the invention, the doping ion of described doped region 303 is preferably arsenic ion or antimony ion.Because arsenic ion or antimony ion have less diffusion coefficient, thereby avoid in described structure cell manufacturing process, the phenomenon that spread to described the first drift region 301 directions described doped region 303, thus can strictly control the doping content of described doped region 303 and inject the degree of depth.
Due to the structure cell providing in the embodiment of the present invention, comprise at least one doped region 303 between described the first drift region 301 and the second drift region 302, the doping type of described doped region 303 is identical with the doping type of described drift region, and the doping content of described doped region 303 is greater than the doping content of described drift region, thereby make in the time bearing identical puncture voltage, the IGBT providing in technical solution of the present invention, compared to traditional non-punch through IGBT, there is thinner drift region, integral thickness is smaller, thereby reduce conduction loss, improve the tradeoff between conduction loss and the switching loss of device, improve the overall performance of device, and compared to traditional punch IGBT, reduced turn-off power loss, and improve the tradeoff between conduction loss and the switching loss of device, improve the overall performance of device.
There is identical thickness of detector, the IGBT structure providing in technical solution of the present invention, compared to traditional non-punch through IGBT, the Implantation efficiency of collector region is lower, turn-off power loss is smaller, and compared to traditional punch IGBT, the Implantation efficiency of collector region is higher, conduction loss is smaller.
Therefore, IGBT provided by the present invention has the tradeoff between good conduction loss and switching loss, and overall performance is higher.
It should be noted that, when in the structure cell that the embodiment of the present invention provides, while comprising at least two doped regions 303 between described the first drift region 301 and the second drift region 302, adjacent doped region 303 is spaced apart.
In one embodiment of the invention, the doping content scope of described doped region 303 is 5*10
15cm
-3-9*10
17cm
-3, comprising endpoint value, described doped region 303 is 3 μ m-8 μ m along the scope of the degree of depth h1 in the direction of described collector region 304 to described drift region, comprises endpoint value; In order to form the second best in quality collector region 304, and can finely tune the injection efficiency of described collector region 304, further optimize the overall performance of described IGBT, described doped region 303 is 4 μ m-9 μ m with described collector region 304 along the scope of the spacing h2 in the direction of described collector region 304 to described drift region, comprise endpoint value, but the present invention does not limit this, depending on concrete situation.
For the tradeoff between conduction loss and switching loss in the described IGBT of further optimization, choose the optimum point of close initial point, to improve the overall performance of described IGBT, in another embodiment of the present invention, the number scope of described doped region 303 is 2-4, comprises endpoint value; Described doped region 303 is uniformly distributed on the interface of described the first drift region 301 and described the second drift region 302; Spacing b between adjacent doped region 303 be described doped region 303 width a 1-3 doubly, but the present invention do not limit this, depending on concrete situation.
In sum, IGBT structure cell provided by the present invention, and comprise thering is the IGBT of this structure cell the tradeoff between good switching loss and conduction loss, thereby improved the overall performance of described IGBT.
Embodiment bis-:
The embodiment of the present invention provides the formation method of IGBT described in a kind of embodiment mono-.Take planar gate structure IGBT as example, IGBT formation method provided by the present invention comprises:
Step 201: the first Semiconductor substrate is provided, and described the first Semiconductor substrate comprises the first drift region 301.In embodiments of the present invention, described the first Semiconductor substrate can be N-type doping, also can, for the doping of P type, be determined on a case-by-case basis.In the present embodiment, take described Semiconductor substrate as N-type light dope is as example, the formation method of IGBT provided by the present invention is elaborated.
Step 202: form at least one doped region 303 in the lower surface of described the first Semiconductor substrate, the doping type of described doped region 303 is identical with the doping type of described the first drift region 301, and the doping content of described doped region 303 is greater than the doping content of described the first drift region 301.
In one embodiment of the invention, step 202 comprises:
Step 20201: the lower surface in described the first Semiconductor substrate forms oxide layer, and described oxide layer covers described the first Semiconductor substrate completely;
Step 20202: form photoresist layer on described oxide layer surface, and place mask plate on described photoresist layer surface, there is the etching window corresponding with the position of doped region 303 to be formed in described the first Semiconductor substrate on described mask plate;
Step 20203: described photoresist layer is exposed, developed take described mask plate as mask, in described photoresist layer, form etching window, described etching window runs through described photoresist layer, and corresponding with the position of doped region 303 to be formed in described the first Semiconductor substrate;
Step 20204: take the photoresist layer with etching window as mask, described oxide layer is carried out to etching, in described oxide layer, form etching window, described etching window runs through described oxide layer, and corresponding with the position of doped region 303 to be formed in described the first Semiconductor substrate;
Step 20205: take the oxide layer with etching window as mask, form at least one doped region 303 in described the first Semiconductor substrate, described the first doped region 303 is positioned at the lower surface of described the first drift region 301.
In one embodiment of the invention, the formation technique of described doped region 303 can be Implantation, can be also thermal deposition, and the present invention does not limit this.In the time that the formation technique of described doped region 303 is Implantation, the Implantation Energy of doping ion is less than 40keV.
Step 203: the oxide layer of removing described the first Semiconductor substrate lower surface, form the second Semiconductor substrate at described the first Semiconductor substrate lower surface, described the second Semiconductor substrate is all identical with doping type and the concentration of described the first Semiconductor substrate, is also N-type light dope Semiconductor substrate.Described the second Semiconductor substrate comprises the second drift region 302, and described the second drift region 302 is positioned at the lower surface of described the first drift region 301, and covers described the first drift region and described doped region completely;
In one embodiment of the invention, the formation optimal process of described the second Semiconductor substrate is extension, thereby can guarantee that described the second drift region 302 is all identical with doping type and the doping content of described the first drift region 301.
In another embodiment of the present invention, the thickness range of described the second Semiconductor substrate on along described the second Semiconductor substrate to the direction of described the first Semiconductor substrate is 5 μ m-10 μ m, comprises endpoint value.Compared to punch IGBT formation method of the prior art, the IGBT formation method that the embodiment of the present invention provides, do not need the drift region that extension is very thick, but only need the second Semiconductor substrate that epitaxial thickness is very little, thereby greatly reduce the cost of manufacture of described IGBT.
Step 204: the upper surface in described the first Semiconductor substrate forms grid structure.
In one embodiment of the invention, step 204 comprises:
Step 20401: form gate dielectric layer at described the first Semiconductor substrate upper surface, described gate dielectric layer is preferably gate oxide;
Step 20402: form gate electrode layer on described gate dielectric layer surface, and described gate dielectric layer and described gate electrode layer are carried out to etching, form grid structure 305 at described the first Semiconductor substrate upper surface.
Step 20403: form passivation layer on described grid structure 305 surfaces, described passivation layer is formed at upper surface and the sidewall of described grid structure 305.
Step 205: form source configuration in the first Semiconductor substrate of described grid structure 305 both sides.
In one embodiment of the invention, step 205 comprises:
Step 20501: take described passivation layer as mask, described the first Semiconductor substrate is carried out to Implantation, in described the first Semiconductor substrate upper surface, form well region 306, and under the condition of 1000 ℃-1200 ℃, described the first Semiconductor substrate is carried out to high annealing, make described well region 306 reach the required degree of depth.In the present embodiment, described well region 306 is P type well region, and its doping ion is preferably boron ion.
Step 20502: described well region 306 is carried out to Implantation, at the heavily doped N-type doped region of the interior formation of described well region 306;
Step 20503: form oxide layer at described well region 306 and 307 surfaces, source region, and under the condition of 800 ℃-1000 ℃, described N-type doped region is annealed, form source region 307, its doping ion is preferably arsenic ion.
Step 20504: form with the surface in source region 307 source electrode 308 being electrically connected with source region 307 with described well region 306 at described well region 306.In one embodiment of the invention, described source electrode 308 is preferably aluminium electrode, and it forms optimal process is deposit.
Step 206: form protective layer at described grid structure and source configuration surface, to avoid described grid structure and source configuration to be subject to the pollution of external environment.
Step 207: the lower surface of described the second Semiconductor substrate is carried out to Implantation, and anneal under the condition of 450 ℃, form collector region 304, the doping type of described collector region 304 is different from the doping type of described drift region, is P type collector region.
Step 208: the lower surface in described collector region 304 forms the collector electrode being electrically connected with described collector region 306, and described collector electrode is preferably aluminium electrode, it forms optimal process is deposit.
The IGBT that utilizes IGBT formation method that the embodiment of the present invention provides to make, has the tradeoff between good switching loss and conduction loss, improved the overall performance of IGBT, and cost of manufacture is low.
Embodiment tri-:
The embodiment of the present invention provides the formation method of IGBT described in another kind of embodiment mono-.Take trench gate structure IGBT as example, IGBT formation method provided by the present invention comprises:
Step 301: the first Semiconductor substrate is provided, and described the first Semiconductor substrate comprises the first drift region 301.
Step 302: form at least one doped region 303 in the lower surface of described the first Semiconductor substrate, the doping type of described doped region 303 is identical with the doping type of described the first drift region 301, and the doping content of described doped region 303 is greater than the doping content of described the first drift region 301.
Step 303: form the second Semiconductor substrate at described the first Semiconductor substrate lower surface, described the second Semiconductor substrate is all identical with doping type and the concentration of described the first Semiconductor substrate, is also N-type light dope Semiconductor substrate.Described the second Semiconductor substrate comprises the second drift region 302, and described the second drift region 302 is positioned at the lower surface of described the first drift region 301, and covers described the first drift region and described doped region completely;
In one embodiment of the invention, the formation optimal process of described the second Semiconductor substrate is extension; In another embodiment of the present invention, the thickness range of described the second Semiconductor substrate on along described the second Semiconductor substrate to the direction of described the first Semiconductor substrate is 5 μ m-10 μ m, comprise endpoint value, but the present invention do not limit to this.
Step 304: described the first Semiconductor substrate is carried out to Implantation, in described the first Semiconductor substrate upper surface, form well region 306, and under the condition of 1000 ℃-1200 ℃, described the first Semiconductor substrate is carried out to high annealing, make described well region 306 reach the required degree of depth.In the present embodiment, described well region 306 is P type well region, and its doping ion is preferably boron ion.
Step 305: to forming grid structure in described the first Semiconductor substrate, described grid structure runs through described well region 306.
In one embodiment of the invention, step 305 comprises:
Step 30501: form groove in described the first Semiconductor substrate, described groove runs through described well region;
Step 30502: form gate dielectric layer at reeded the first semiconductor substrate surface of tool;
Step 30502: form gate electrode layer on described gate dielectric layer surface, and unnecessary gate dielectric layer and the gate electrode layer of etching, form grid structure 305.Wherein, the formation optimal process of described gate electrode layer is deposit.
Step 306: form source configuration in described the first Semiconductor substrate.
In one embodiment of the invention, step 306 comprises:
Step 30601: form passivation layer at described grid structure 305 and well region 306 surfaces, and form etching window in described passivation layer, described etching window is corresponding with the position in the interior source region 307 to be formed of described well region 306;
Step 30602: described well region 306 is carried out to Implantation, at the heavily doped N-type doped region of the interior formation of described well region 306;
Step 30603: form passivation layer on described N-type doped region surface, and under the condition of 800 ℃-1000 ℃, described N-type doped region is annealed, form source region 307, its doping ion is preferably arsenic ion.
Step 30604: remove the passivation layer on described well region 306 and 307 surfaces, source region, form with the surface in source region 307 source electrode 308 being electrically connected with source region 307 with described well region 306 at described well region 306.In one embodiment of the invention, described source electrode 308 is preferably aluminium electrode, and it forms optimal process is deposit.
Step 307: form protective layer at described grid structure and source configuration surface, to avoid described grid structure and source configuration to be subject to the pollution of external environment.
Step 308: the lower surface of described the second Semiconductor substrate is carried out to Implantation, and anneal under the condition of 450 ℃, form collector region 304, the doping type of described collector region 304 is different from the doping type of described drift region, is P type collector region.
Step 309: the lower surface in described collector region 304 forms the collector electrode being electrically connected with described collector region 306, and described collector electrode is preferably aluminium electrode, it forms optimal process is deposit.
The IGBT that utilizes IGBT formation method that the embodiment of the present invention provides to make, has the tradeoff between good switching loss and conduction loss, improved the overall performance of IGBT, and cost of manufacture is low.
In this specification, various piece adopts the mode of going forward one by one to describe, and what each part stressed is and the difference of other parts, between various piece identical similar part mutually referring to.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the present invention.To be apparent for those skilled in the art to the multiple modification of these embodiment, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (16)
1. an IGBT structure cell, is characterized in that, comprising:
The first drift region and the second drift region that is positioned at described the first drift region lower surface, described the first drift region is all identical with doping type and the concentration of described the second drift region;
At least one doped region between described the first drift region and the second drift region, the doping type of described doped region is identical with the doping type of described the second drift region, and the doping content of described doped region is greater than the doping content of described the second drift region;
Be positioned at described the second drift region and deviate from Yi Ce collector region, described doped region, the doping type of described collector region is contrary with the doping type of described the second drift region.
2. structure cell according to claim 1, is characterized in that, when the number of described doped region is at least two, adjacent doped region is spaced apart.
3. structure cell according to claim 2, is characterized in that, the doping ion of described doped region is arsenic ion or antimony ion.
4. structure cell according to claim 3, is characterized in that, described doped region doping content scope is 5*10
15cm
-3-9*10
17cm
-3, comprise endpoint value.
5. structure cell according to claim 2, is characterized in that, the number scope of described doped region is 2-4, comprises endpoint value.
6. structure cell according to claim 5, is characterized in that, described doped region is uniformly distributed.
7. structure cell according to claim 6, is characterized in that, the spacing between adjacent doped region is 1-3 times of described doped region width.
8. structure cell according to claim 1, is characterized in that, the depth bounds of described doped region is 3 μ m-8 μ m, comprises endpoint value.
9. structure cell according to claim 1, is characterized in that, the spacing range of described doped region and described collector region is 4 μ m-9 μ m, comprises endpoint value.
10. an IGBT, is characterized in that, comprises the structure cell described at least one claim 1-9 any one.
The formation method of 11. 1 kinds of IGBT, is characterized in that, comprising:
The first Semiconductor substrate is provided, and described the first Semiconductor substrate comprises the first drift region;
In the lower surface of described the first Semiconductor substrate, form at least one doped region, the doping type of described doped region is identical with the doping type of described the first drift region, and the doping content of described doped region is greater than the doping content of described the first drift region;
Form the second Semiconductor substrate at described the first Semiconductor substrate lower surface, described the second Semiconductor substrate is all identical with doping type and the concentration of described the first Semiconductor substrate, and described the second Semiconductor substrate comprises the second drift region, described the second drift region covers described the first drift region and described doped region completely;
In described the second Semiconductor substrate lower surface, form collector region.
12. formation methods according to claim 11, is characterized in that, form at least one doped region and comprise in the lower surface of described the first Semiconductor substrate:
In described the first semiconductor lower surface, form oxide layer;
In described oxide layer, form etching window, described etching window is corresponding with the position of doped region to be formed in described the first Semiconductor substrate;
Take the oxide layer with etching window as mask, in described the first Semiconductor substrate, form at least one doped region.
13. formation methods according to claim 12, is characterized in that, the formation technique of described doped region is Implantation or thermal deposition.
14. formation methods according to claim 13, is characterized in that, when the formation technique of described doped region is Implantation, the Implantation Energy of doping ion is less than 40keV.
15. formation methods according to claim 11, is characterized in that, the formation technique of described the second Semiconductor substrate is extension.
16. formation methods according to claim 15, is characterized in that, the thickness range of described the second Semiconductor substrate is 5 μ m-10 μ m, comprises endpoint value.
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| CN201210520131.3A CN103855202A (en) | 2012-12-06 | 2012-12-06 | IGBT, celluar structure of IGBT and IGBT forming method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015196534A1 (en) * | 2014-06-24 | 2015-12-30 | 江苏中科君芯科技有限公司 | Dual-mode insulated gate transistor |
| CN106252399A (en) * | 2016-08-31 | 2016-12-21 | 电子科技大学 | A kind of inverse conductivity type IGBT |
| CN116153992A (en) * | 2023-04-21 | 2023-05-23 | 上海陆芯电子科技有限公司 | Reverse-conduction insulated gate bipolar transistor |
-
2012
- 2012-12-06 CN CN201210520131.3A patent/CN103855202A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015196534A1 (en) * | 2014-06-24 | 2015-12-30 | 江苏中科君芯科技有限公司 | Dual-mode insulated gate transistor |
| CN106252399A (en) * | 2016-08-31 | 2016-12-21 | 电子科技大学 | A kind of inverse conductivity type IGBT |
| CN106252399B (en) * | 2016-08-31 | 2019-03-29 | 电子科技大学 | A kind of inverse conductivity type IGBT |
| CN116153992A (en) * | 2023-04-21 | 2023-05-23 | 上海陆芯电子科技有限公司 | Reverse-conduction insulated gate bipolar transistor |
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Application publication date: 20140611 |