CN103855140B - 用于击穿电压改进的功率器件上部分soi - Google Patents
用于击穿电压改进的功率器件上部分soi Download PDFInfo
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Abstract
本发明涉及增加半导体功率器件的击穿电压的方法和装置。通过利用中间氧化物层将器件晶圆接合至操作晶圆来形成接合晶圆。从器件晶圆的原始厚度大幅地减薄器件晶圆。通过半导体制造工艺在器件晶圆内形成功率器件。图案化操作晶圆以去除操作晶圆位于功率器件下方的部分,从而导致功率器件的击穿电压改进以及功率器件在反向偏置条件下的均匀静电势,其中确定击穿电压。也公开了其他方法和结构。公开了用于击穿电压改进的功率器件上部分SOI。
Description
技术领域
本发明涉及增加半导体功率器件的击穿电压的方法和装置。
背景技术
由于超高压(UHV)金属氧化物半导体场效应晶体管(MOSFET)器件相对于诸如绝缘栅极双极型晶体管和半导体闸流管的其他功率半导体器件的高效率,超高压(UHV)金属氧化物半导体场效应晶体管(MOSFET)器件在集成电路中主要用于转换用途。UHV MOSFET器件的击穿电压与围绕UHV MOSFET器件的埋氧层(BOX)厚度和晶圆厚度相关。增加BOX厚度以增加击穿电压可能增加缺陷密度并降低生产量。
发明内容
为了解决现有技术中存在的问题,根据本发明的一方面,提供了一种功率器件,包括:在器件晶圆的第一表面上设置的晶体管;和通过中间氧化物层接合至所述器件晶圆的第二表面的操作晶圆,所述操作晶圆包括位于所述晶体管附近的凹槽。
在所述的功率器件中,所述凹槽位于所述晶体管的一部分的上方。在一个实施例中,在上述功率器件中,所述凹槽位于所述晶体管的漏极区的上方并且横跨所述晶体管的沟道和所述晶体管的漏极之间的区域。在另一个实施例中,在上述功率器件中,利用电介质沟槽隔离结构和包括中间氧化物层的BOX隔离件,所述功率器件的区域被横向隔离开。
所述的功率器件还包括在大约2μm和大约10μm之间的器件晶圆厚度。
在所述的功率器件中,所述晶体管还包括横向扩散金属氧化物半导体场效应晶体管或横向绝缘栅极双极型晶体管。
所述的功率器件还包括大于约500V的击穿电压。
根据本发明的另一方面,提供了一种在利用中间氧化物层接合至操作晶圆的器件晶圆上设置的半导体器件,包括:在所述半导体器件的源极上方设置的第一场氧化物层;在所述半导体器件的漏极上方设置的第二场氧化物层;在所述半导体器件的沟道上方且在栅极多晶硅下方设置的第三场氧化物层;以及在所述操作晶圆中形成的凹槽,其中,已在所述半导体器件的一部分的下方去除所述操作晶圆的一部分。
在所述的半导体器件中,所述凹槽位于所述半导体器件的漏极区并且横跨所述半导体器件的所述沟道和所述半导体器件的漏极之间的区域。
所述的半导体器件还包括:围绕所述半导体器件的埋氧层;位于所述半导体器件的源极内且具有第一类型的第一导电性的第一阱;位于所述第一场氧化物层下方且具有第二类型的第二导电性的第二阱;在所述第一阱内邻近所述第一场氧化物层设置的包括第一过量的第一类型的载流子的第一掺杂区;在所述第一阱内邻近所述栅极多晶硅设置的包括第二过量的第二类型的载流子的第二掺杂区;以及在所述漏极内设置的包括过量的第一类型的载流子的第三掺杂区。
在上述半导体器件中,所述第一类型的导电性包括p型导电性;所述第二类型的导电性包括n型导电性;所述第一类型的载流子包括空穴;以及所述第二类型的载流子包括电子。
在上述半导体器件中,所述器件晶圆包括厚度在大约2μm和大约10μm之间的硅外延层。在一个实施例中,上述半导体器件还包括大于约500V的击穿电压。在另一个实施例中,上述半导体器件还包括横向扩散金属氧化物半导体场效应晶体管。在又一个实施例中,上述半导体器件还包括横向绝缘栅极双极型晶体管。
根据本发明的又一方面,提供了一种增加功率器件的击穿电压的方法,包括:提供接合晶圆,所述接合晶圆包括利用中间氧化物层接合至操作晶圆的器件晶圆;减薄所述器件晶圆;在所述器件晶圆上制造所述功率器件;以及去除所述操作晶圆的一部分。
在所述的方法中,去除所述操作晶圆的所述一部分还包括:选择性地图案化所述操作晶圆的表面;以及去除所述操作晶圆被选择性图案化的部分。
上述方法还包括在所述功率器件的一部分的上方的区域中选择性地图案化所述操作晶圆。
上述方法还包括:用光刻胶涂覆所述操作晶圆的表面;使所述操作晶圆的表面与包含图案的光掩模对准;将所述操作晶圆的表面暴露于光以转印所述图案至所述光刻胶;以及利用所述中间氧化物层作为蚀刻停止件根据所述图案对所述操作晶圆的表面进行蚀刻。
上述方法还包括去除所述操作晶圆的所述一部分结合减薄所述器件晶圆以基本上去除从反偏置条件下所述功率器件的栅极发射的电势线的横向分量,其中测量所述击穿电压。
附图说明
图1示出超高压(UHV)金属氧化物半导体场效应晶体管(MOSFET)功率器件的一些方面。
图2A-图2L示出为了改进击穿电压在接合晶圆上形成功率器件的一些实施例。
图3A-图3B示出制造UHV功率器件的方法的一些实施例。
图4A-图4B示出对功率器件的击穿电压测量的一些实施例。
图5示出功率器件的电场分布的图。
图6示出对功率器件击穿电压作为器件晶圆厚度的函数的图。
具体实施方式
结合附图作出本文的描述,其中类似的参考数字通常始终用于表示类似的元件,并且其中各个结构不一定要按照比例绘制。在以下描述中,为了说明的目的,详尽地解释许多具体的细节以帮助理解。然而,对于本领域普通技术人员来说显而易见的是本文描述的一个或多个方面可以以比这些具体的细节低的程度实践。在其他情况中,以框图形式示出已知的结构和器件以帮助理解。
图1示出在接合晶圆上形成的超高压(UHV)金属氧化物半导体场效应晶体管(MOSFET)功率器件100的一些方面。接合晶圆包括通过中间氧化物层104接合的操作晶圆102和器件晶圆106。UHV MOSFET器件100包括横向扩散金属氧化物半导体场效应晶体管(LDMOS)功率器件或横向绝缘栅极双极型晶体管(LIGBT),对于给定的集成电路(IC)应用被配置用于支持相关逻辑器件的升高电压条件。在本发明中,LIGBT100用作UHV MOSFET器件100的实例。栅极108在LIGBT功率器件100的有源沟道区上方形成。邻近栅极设置源极114,源极114包括进一步具有第一类型的第一导电性(例如p型)的第一阱110和进一步具有第二类型的第二导电性(例如n型)的第二阱112。LIGBT功率器件100还包括漏极116、被配置用于使栅极108、源极114和漏极116与UHV偏置的非预期效应隔离的场氧化物层(FOX)118。
LIGBT功率器件100被用于诸如片上系统(SoC)IC的应用。SoC技术通过集成逻辑和模拟制造工艺实现单个芯片上的系统级功能。高成本效益的SoC技术要求利用低成本高性能的功率器件来驱动多个负载支持安全工作区(SOA)为大约10V至大约20V的SoC内的多电源域。这种类型的驱动可以通过电荷泵器件实现,电荷泵器件需要额外的工艺复杂性和增加的成本。LIGBT功率器件100还可以实现SoC应用所需的期望电压但是容易遭受超过LIGBT功率器件100的击穿电压的电介质击穿。击穿电压(即在不用作导体的情况下LIGBT器件100可以承受的最大电压,由器件晶圆106的电介质击穿导致的)取决于隔离器件晶圆106内的LIGBT功率器件100的隐埋氧化物(BOX)的厚度,和器件晶圆106本身的厚度。增加BOX的厚度可以增加击穿电压,但是也可能产生非预期效应(诸如增加LIGBT功率器件100内的缺陷密度和降低总生产量)。
因此,本发明涉及增加半导体功率器件的击穿电压的方法和装置。通过利用中间氧化物层将器件晶圆接合至操作晶圆来形成接合晶圆。从器件晶圆的原始厚度大幅地减薄器件晶圆。通过半导体制造工艺在器件晶圆内形成功率器件。图案化操作晶圆以去除操作晶圆位于功率器件下方的部分,从而导致功率器件的击穿电压改进和功率器件在反向偏置条件下的均匀静电势,其中确定击穿电压。也公开了其他方法和结构。
图2A-图2L示出为了改进击穿电压在接合晶圆上的功率器件形成的一些实施例。图2A示出通过氧化器件晶圆106的表面以产生中间氧化物层104,倒转器件晶圆106,以及利用中间氧化物层104将器件晶圆106接合至操作晶圆102而形成的接合晶圆200A。减薄器件晶圆106,使其从大约20μm的原始厚度减薄至大约5μm的厚度。利用电介质凹槽隔离结构和包括中间氧化物层104的BOX隔离件横向隔离功率器件的区域以防止功率器件的电流泄露。
图2B示出具有设置在器件晶圆106的表面区域中的阱的接合晶圆200B。在一些实施例中,器件晶圆106包括轻掺杂的p型衬底。具有第一类型的第一导电性的第一阱110通过扩散、注入或它们的组合设置在器件晶圆106的源极114内。对于图2A-图2L的实施例,第一类型的第一导电性包括p型导电性,其中用硼掺杂第一阱110。具有第二类型的第二导电性(例如n型导电性)的第二阱112通过磷掺杂设置在源极114内。RESURF(降低表面电场)技术利用器件晶圆106的近表面区域的砷掺杂来产生p型环或“p-环”202,其降低栅极氧化物下的电势拥挤现象并且增加击穿电压。
图2C示出沉积有用于在升高的电压条件下进行器件终端隔离的场氧化物(FOX)或场板的接合晶圆200C。第一场氧化物层206(例如TEOS)在源极114上方设置并且被配置用于使源极114与施加给源极114的电势隔离。第二场氧化物层208在位于与第一场氧化物层206的p环202相对的区域中的漏极116上方设置,并且被配置用于使漏极116与施加给漏极116的电势隔离。第三场氧化物层204在p-环202上方设置并且形成为场板以增加击穿电压。
图2D示出在接合晶圆200D上形成电源栅极。为了减轻源极114的热载流子效应,将n型轻掺杂漏极212注入第一阱110中。栅极108在第三场氧化物层204的一部分的上方和第一阱110的一部分的上方沉积,栅极108具有覆盖n型轻掺杂漏极212的第一间隔件210A和位于栅极108的相对侧上的第二间隔件210B。
图2E示出在接合晶圆上设置的功率器件结构200E。通过离子注入掺杂图2B中形成的阱和漏极116制造功率器件结构200E。用第一过量的第一类型的载流子(例如空穴)掺杂第一阱110以邻近第一场氧化物层206形成第一掺杂区。还通过离子注入在第一阱110内邻近栅极108设置包括第二过量的第二类型的载流子(例如电子)的第二掺杂区216。在漏极116内设置包括过量的第一类型的载流子的第三掺杂区214B。
如图2F所示,在完成功率器件结构200E时,形成层间电介质(ILD)218以使器件晶圆106表面和功率器件与周边环境隔离。图2G示出翻转包含制造的功率器件200G的接合晶圆用于选择性地去除部分操作晶圆102。对于图2A-图2L的实施例,完全去除操作晶圆102位于功率器件200G下方的区域。在随后的实施例中,只去除该区域位于功率器件200G下方的一部分。图2H示出用于功率器件的操作晶圆去除200H的一些实施例。借助旋转涂覆装置利用光刻胶220(例如正性光刻胶)涂覆操作晶圆102的表面,操作晶圆102的表面与包含图案的光掩模对准,该图案包括开口,该开口位于功率器件222下方的操作晶圆表面的区域上方。将操作晶圆102的涂覆表面暴露于照明以转印开口至光刻胶220,并且使用中间氧化物层作为蚀刻停止件来根据图案对操作晶圆102的表面进行蚀刻,从而在操作晶圆102内产生凹槽224,凹槽224包括操作晶圆102的去除部分并且位于功率器件222的附近。对于图2A-图2L的实施例,凹槽224包括操作晶圆102位于功率器件222上方被基本上完全去除的一部分。应该注意到,在正向取向中,操作晶圆102的被基本上完全去除的部分位于功率器件222的下方。为了避免混淆,可以说不管取向如何,操作晶圆102的被基本上完全去除的部分位于功率器件222的上方,正如通过布尔交互布局限制(Boolean interaction layoutrestrictions)所强制实施的。如图2I所示去除光刻胶220,并且如图2J所示将接合晶圆翻转回到其初始取向。
在选择性去除操作晶圆之后,通过形成多个金属化层以连接功率器件和外部刺激(即电压)来完成后段工序(BEOL)金属化。图2K示出具有在凹槽(224)形成之后增加的BEOL层的功率器件200K。功率器件的终端在ILD218内被隔离并且与位于金属间电介质(IMD)228内互相隔离的第一金属化层226A-226C连接。第一金属化层226A-226C与位于钝化(PA)层232内互相隔离的第二金属化层230A-230C连接。图2A-图2L的实施例示出完全去除操作晶圆102位于功率器件222下方的部分。然而,如图2L所示,通过部分去除操作晶圆102位于功率器件222下方的部分也可以实现改进的击穿电压,其中凹槽224在功率器件222的漏极区下方形成并且横跨功率器件222的沟道和漏极116之间的n漂移区(未示出)。
图3A示出制造UHV功率器件的方法300A的一些实施例的流程图。虽然在下文中将方法300A示出和描述为一系列的动作或事件,但是应该理解不应以限制性意义解释这些动作或事件所示出的顺序。例如,一些动作可以以不同的顺序发生和/或与除了本文中示出和/或描述的动作或事件之外的其他动作或事件同时发生。另外,并不是所有示出的动作都是实施本说明书的一个或多个方面或实施例所必需的。另外,可以在一个或多个单独的动作和/或阶段中实施本文描述的一个或多个动作。
在302A,利用在器件晶圆上形成的中间氧化物层将器件晶圆接合至操作晶圆。在一些实施例中,中间氧化物层包括通过湿式或干式化学工艺生长的SiO2,该中间氧化物层将硅操作晶圆接合至轻掺杂的p型器件晶圆。
在304A,通过湿式化学蚀刻工艺、干式化学蚀刻工艺、化学机械抛光(CMP)、或它们的组合减薄器件晶圆使其从大约20μm的原始厚度减薄至小于大约5μm的厚度。
在306A,在器件晶圆的表面区域内设置第一源极阱,第一源极阱包括与器件晶圆的导电类型相反的导电类型(例如,对于轻掺杂的p型器件晶圆,第一源极阱包括NWELL,并且通过磷注入形成)。通过硼注入形成包括PWELL的第二源极阱。还通过器件晶圆的近表面区域的砷掺杂形成RESURF层或p-环以降低在随后的步骤中形成的栅极材料下方的电势拥挤现象。
在308A,在器件晶圆的源极、漏极和栅极区上方形成场氧化物层(FOX)。在一些实施例中,FOX形成包括外延生长原硅酸四乙酯(TEOS)层。
在310A,在栅极区中形成的FOX层的一部分上方以及在源极阱的一部分的上方设置栅极材料。在栅极的两侧上形成间隔件以使栅极与源极和漏极隔离。在一些实施例中,栅极材料包括n+多晶硅。在其他实施例中,栅极材料包括p+多晶硅。
在312A,在邻接源极FOX层的第一区域中通过离子注入对第二源极阱进行p+掺杂。在邻接栅极的第二区域中通过离子注入对第二源极阱进行n+掺杂。还在近表面区域对漏极进行p+掺杂。
在314A,形成层间电介质(ILD)以使器件晶圆表面和功率器件与周边环境隔离。ILD还封装源极、漏极和栅极接触件,源极、漏极和栅极接触件将功率器件连接至在随后的步骤中制造的BEOL金属化层。
在316A,通过形成用于将功率器件连接至外部刺激的多个金属化层来完成BEOL金属化。第一金属化层设置在ILD上方并且通过位于IMD内互相隔离的接触件与功率器件终端连接。第一金属化层与位于PA层内互相隔离的第二金属化层连接。为了连接芯片和外部刺激(例如电源、时钟、数据等),在PA层内形成与金属化层连接的芯片连接件。
在318A,翻转接合晶圆。
在320A,参照在前述步骤中形成的UHV功率器件图案化操作晶圆的表面。利用光刻胶涂覆操作晶圆的表面,操作晶圆的表面与包含图案的光掩模对准,该图案包括开口,该开口位于UHV功率器件的一部分上方的操作晶圆表面的一部分(即在正向取向中,位于UHV功率器件下方的操作晶圆表面的一部分)上方。将操作晶圆表面暴露于光以转印掩模图案至光刻胶。
在322A,使用中间氧化物层作为蚀刻停止件来根据图案对操作晶圆的表面进行蚀刻以在UHV功率器件上方的操作晶圆内形成凹槽。在一些实施例中,去除位于整个UHV功率器件上方的操作晶圆的部分。在一些实施例中,去除位于UHV功率器件的一部分(例如漏极)的上方的操作晶圆的部分。
在324A,将接合晶圆翻转回到正向取向,其中凹槽位于UHV功率器件的下方。
图3B示出制造UHV功率器件的方法300B的一些实施例的流程图。方法300B包括与方法300A相同的步骤,但是以不同的顺序执行这些步骤以获得等效的结果。302B-314B与302A-314A相同并且以相同的顺序执行从而使得方法300A和方法300B之间直到ILD沉积步骤(314A/B)无区别。然而,将方法300B中的剩余BEOL制造移动到相对于方法300A的最后步骤。以与方法300B中的顺序相同的顺序实施方法300A的剩余步骤(即在314B之后并且以与方法300A相同的方式和顺序实施316B-322B)。在翻转接合晶圆(316B),将操作晶圆表面上的图案化的光刻胶暴露于光(318B),去除功率器件相应的操作晶圆的部分(320B),以及翻转回去(322B)之后,在324B完成剩余的BEOL制造。
图4A示出对在接合晶圆上形成的功率器件400A的击穿电压测量的一些实施例。功率器件400A的栅极108和源极114与接地焊盘402连接。功率器件400A的漏极116与电源焊盘404连接,电源焊盘404为功率器件400A提供电压,从而形成功率器件400A的反偏压。在这些偏置条件下,“RESURF效应”在一部分功率器件400A的上方以朝向漏极116的横向方向分布电势线406A,并且导致电势线406A在击穿时的最佳分布。栅极108下方的高电流密度电势拥挤现象将导致电势线406A由于本领域普通技术人员公知的“柯肯效应(Kirk Effect)”的现象朝向漏极116移动。应该注意到,功率器件400A设置在包括通过中间氧化物层104(例如SiO2)接合至操作晶圆102的器件晶圆106(其厚度为大约20微米)的接合晶圆上,其中未去除操作晶圆102的任何部分。操作晶圆102和中间氧化物层104之间的界面处发生电势拥挤现象,从而将这次测量的击穿电压限制为大约465V。
图4B示出对在接合晶圆上形成的功率器件400B的击穿电压测量的一些实施例,其中操作晶圆(102)位于功率器件400B下方的部分被去除。另外,器件晶圆106已经被减薄至大约5μm的厚度。功率器件400B的偏置条件与功率器件400A的相同。然而,相比于图4A的实施例,所得到的从栅极发射的电势线406B在源极114和漏极116之间分布得基本上更均匀。具体地说,未观察到大量的电势拥挤现象或大量的柯肯效应。去除操作晶圆(102)结合减薄器件晶圆使功率器件400B的击穿电压增加至大于约500V的值。另外,图4A的电势线406A的横向分量被基本上去除,从而导致基本上垂直的电势线406B。该实施例的击穿电压经测量为大约525V。
图5示出图4A-图4B的实施例的功率器件的电场分布的图500。对于从图4A的实施例测量的第一分布曲线502和从图4B的实施例测量的第二分布曲线504,电场强度(即纵坐标,单位为V/cm)被示出为接合晶圆内的深度(即横坐标,单位是μm)的函数。每个相应的曲线502或504下面积得出相应的功率器件400A或400B的击穿值。第一分布曲线502下面积得出大约465V的击穿电压。第二分布线504下面积得出大约525V的击穿电压。
因此,对于其中对操作晶圆的表面进行选择性图案化以去除操作晶圆位于功率器件的一部分下方的部分和其中使器件晶圆从20μm的原始厚度减薄的接合晶圆上的功率器件(例如LIGBT),击穿电压改进得以证实。图6示出对于功率器件,击穿电压作为器件晶圆厚度的函数的图600。图600的纵坐标是功率器件的击穿电压(单位为V)。图600的横坐标是包括硅外延层(即epi)的器件晶圆的器件晶圆厚度(单位为μm)。数据点602-610表示根据图4A-图4B和图5的实施例的对各个器件晶圆的厚度测量的击穿电压。大约为3μm的第一器件晶圆厚度得出大约500V的第一击穿电压值602,大约为4μm的第二器件晶圆厚度得出大约500V的第二击穿电压值604,大约为5μm的第三器件晶圆厚度得出大约525V的第三击穿电压值606,大约为6.5μm的第四器件晶圆厚度给出大约520V的第四击穿电压值608,以及大约为8.75μm的第五器件晶圆厚度给出大约385V的第五击穿电压值610。因此,图6的实施例示出对于大约5μm的器件晶圆厚度最大击穿电压改进至约525V。
本领域普通技术人员在阅读和/或理解本说明书和附图的基础上还应该理解可以发生等效变化和/或改变。本文公开的内容包括所有这些改变和变化而且通常不打算受到这些改变和变化的限制。另外,虽然可以仅参照若干实施方式中的一种公开特定的特征或方面,但是可以预期,可以将这种特征或方面与其他实施方式的一个或多个其他特征和/或方面组合。另外,就本文使用的术语“包括”、“具有...的”、“具有”、“带有”和/或它们的变形来说;这些术语意图包括在类似“包含”的含义中。再者,“示例性”仅仅意味着表示实例,而不是最优的。应该理解,为了简明和便于理解,本文描述的部件、层和/或元件被示出为相对于另一部件、层和/或元件具有特定尺寸和/或方向,以及实际的尺寸和/或方向可以远远不同于本文示出的尺寸和/或方向实质上。
因此,本发明涉及增加半导体功率器件的击穿电压的方法和装置。通过利用中间氧化物层将器件晶圆接合至操作晶圆来形成接合晶圆。从器件晶圆的原始厚度大幅地减薄器件晶圆。通过半导体制造工艺在器件晶圆内形成功率器件。图案化操作晶圆以去除操作晶圆位于功率器件下方的部分,从而导致功率器件的击穿电压改进和功率器件的源极和漏极之间的均匀电势。
在一些实施例中,本发明涉及一种增加功率器件的击穿电压的方法,包括利用中间氧化物层将器件晶圆接合至操作晶圆,在器件晶圆上制造功率器件,以及去除操作晶圆位于功率器件下面的部分。操作晶圆的去除具有减轻操作晶圆和中间氧化物层之间的界面处的电势拥挤的效果,从而导致功率器件的沟道区域中的电势均匀性增加和击穿电压改进。
在一些实施例中,本发明涉及一种制造功率器件的方法,包括氧化器件晶圆的表面以产生中间氧化物层和利用中间氧化物层将器件晶圆接合至操作晶圆。将晶圆减薄至大约2μm和约10μm之间的厚度。在器件晶圆上制造功率器件并且利用ILD层使功率器件与周边环境隔离。选择性图案化操作晶圆的表面以去除操作晶圆位于功率器件的一部分下方的部分。器件晶圆减薄结合操作晶圆去除增加击穿电压值。
在一些实施例中,本发明涉及在利用中间氧化物层接合至操作晶圆的减薄的器件晶圆上设置的半导体器件,该半导体器件包括源极、漏极和栅极终端,以及在操作晶圆中形成的凹槽,其中已去除了位于半导体器件正下方的操作晶圆。
Claims (16)
1.一种功率器件,包括:
在器件晶圆的第一表面上设置的晶体管,所述晶体管包括在所述第一表面上方横向间隔设置的源极区、漏极区和沟道区,其中,所述器件晶圆被减薄,减薄后的所述器件晶圆具有2μm和10μm之间的器件晶圆厚度;以及
通过中间氧化物层接合至所述器件晶圆的第二表面的操作晶圆,所述操作晶圆包括位于所述晶体管附近的凹槽,
其中,所述凹槽位于所述晶体管的漏极区的上方并且仅仅横跨所述晶体管的沟道和所述晶体管的漏极之间的区域,
其中,在接近所述器件晶圆的所述第一表面处且在所述源极区和所述漏极区之间形成环形掺杂区域。
2.根据权利要求1所述的功率器件,其中,利用电介质沟槽隔离结构和包括中间氧化物层的BOX隔离件,所述功率器件的区域被横向隔离开。
3.根据权利要求1所述的功率器件,其中,所述晶体管还包括横向扩散金属氧化物半导体场效应晶体管或横向绝缘栅极双极型晶体管。
4.根据权利要求1所述的功率器件,其中,所述晶体管具有大于500V的击穿电压。
5.一种在利用中间氧化物层接合至操作晶圆的器件晶圆上设置的半导体器件,包括:
在所述半导体器件的源极上方设置的第一场氧化物层;
在所述半导体器件的漏极上方设置的第二场氧化物层;
在所述半导体器件的沟道上方且在栅极多晶硅下方设置的第三场氧化物层;以及
在所述操作晶圆中形成的凹槽,其中,已在所述半导体器件的一部分的下方去除所述操作晶圆的一部分,
其中,所述凹槽位于所述半导体器件的漏极区并且仅仅横跨所述半导体器件的所述沟道和所述半导体器件的漏极之间的区域,
其中,在所述第三场氧化物层下方且在所述半导体器件的源极区和所述半导体器件的漏极区之间形成环形掺杂区域,
其中,所述器件晶圆被减薄,减薄后的所述器件晶圆具有2μm和10μm之间的器件晶圆厚度。
6.根据权利要求5所述的半导体器件,还包括:
围绕所述半导体器件的埋氧层;
位于所述半导体器件的源极内且具有第一类型的第一导电性的第一阱;
位于所述第一场氧化物层下方且具有第二类型的第二导电性的第二阱;
在所述第一阱内邻近所述第一场氧化物层设置的包括第一过量的第一类型的载流子的第一掺杂区;
在所述第一阱内邻近所述栅极多晶硅设置的包括第二过量的第二类型的载流子的第二掺杂区;以及
在所述漏极内设置的包括过量的第一类型的载流子的第三掺杂区。
7.根据权利要求6所述的半导体器件,其中:
所述第一类型的导电性包括p型导电性;
所述第二类型的导电性包括n型导电性;
所述第一类型的载流子包括空穴;以及
所述第二类型的载流子包括电子。
8.根据权利要求7所述的半导体器件,其中,所述器件晶圆包括厚度在2μm和10μm之间的硅外延层。
9.根据权利要求8所述的半导体器件,其中,所述半导体器件具有大于500V的击穿电压。
10.根据权利要求8所述的半导体器件,还包括横向扩散金属氧化物半导体场效应晶体管。
11.根据权利要求8所述的半导体器件,还包括横向绝缘栅极双极型晶体管。
12.一种增加功率器件的击穿电压的方法,包括:
提供接合晶圆,所述接合晶圆包括利用中间氧化物层接合至操作晶圆的器件晶圆;
减薄所述器件晶圆,减薄后的所述器件晶圆具有2μm和10μm之间的器件晶圆厚度;
在所述器件晶圆上制造所述功率器件,所述功率器件为晶体管;以及
去除所述操作晶圆的一部分而形成凹槽,
其中,所述凹槽位于所述功率器件的漏极区的上方并且仅仅横跨所述功率器件的沟道和所述功率器件的漏极之间的区域,
其中,在所述器件晶圆的接近所述功率器件的表面区域处且在所述功率器件的源极区和所述功率器件的漏极区之间形成环形掺杂区域。
13.根据权利要求12所述的方法,去除所述操作晶圆的所述一部分还包括:
选择性地图案化所述操作晶圆的表面;以及
去除所述操作晶圆被选择性图案化的部分。
14.根据权利要求13所述的方法,还包括在所述功率器件的一部分的上方的区域中选择性地图案化所述操作晶圆。
15.根据权利要求14所述的方法,还包括:
用光刻胶涂覆所述操作晶圆的表面;
使所述操作晶圆的表面与包含图案的光掩模对准;
将所述操作晶圆的表面暴露于光以转印所述图案至所述光刻胶;以及
利用所述中间氧化物层作为蚀刻停止件根据所述图案对所述操作晶圆的表面进行蚀刻。
16.根据权利要求15所述的方法,还包括去除所述操作晶圆的所述一部分结合减薄所述器件晶圆以基本上去除从反偏置条件下所述功率器件的栅极发射的电势线的横向分量,其中测量所述击穿电压。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1470073A (zh) * | 2000-09-21 | 2004-01-21 | ���Ű뵼������˾ | 半导体器件及其制作方法 |
CN101414630A (zh) * | 2007-10-15 | 2009-04-22 | 天钰科技股份有限公司 | 横向扩散金属氧化物晶体管 |
CN101626032A (zh) * | 2008-07-09 | 2010-01-13 | 台湾积体电路制造股份有限公司 | 半导体结构 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01106466A (ja) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | 半導体装置の製造方法 |
US5004705A (en) * | 1989-01-06 | 1991-04-02 | Unitrode Corporation | Inverted epitaxial process |
US5807783A (en) * | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
US5776813A (en) * | 1997-10-06 | 1998-07-07 | Industrial Technology Research Institute | Process to manufacture a vertical gate-enhanced bipolar transistor |
US6265752B1 (en) * | 1999-05-25 | 2001-07-24 | Taiwan Semiconductor Manufacturing, Co., Inc. | Method of forming a HVNMOS with an N+ buried layer combined with N well and a structure of the same |
US6500717B2 (en) * | 2000-12-01 | 2002-12-31 | Agere Systems Inc. | Method for making an integrated circuit device with dielectrically isolated tubs and related circuit |
US6486034B1 (en) * | 2001-07-20 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method of forming LDMOS device with double N-layering |
AU2003241057A1 (en) * | 2002-06-26 | 2004-01-19 | Cambridge Semiconductor Limited | Lateral semiconductor device |
JP2004134672A (ja) * | 2002-10-11 | 2004-04-30 | Sony Corp | 超薄型半導体装置の製造方法および製造装置、並びに超薄型の裏面照射型固体撮像装置の製造方法および製造装置 |
US6919598B2 (en) * | 2003-03-10 | 2005-07-19 | Zia Hossain | LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance |
TWI229933B (en) * | 2004-06-25 | 2005-03-21 | Novatek Microelectronics Corp | High voltage device for electrostatic discharge protective circuit and high voltage device |
US20060022263A1 (en) * | 2004-07-30 | 2006-02-02 | International Rectifier Corporation | Selective substrate thinning for power mosgated devices |
GB2418063A (en) * | 2004-09-08 | 2006-03-15 | Cambridge Semiconductor Ltd | SOI power device |
WO2006038305A1 (ja) * | 2004-10-01 | 2006-04-13 | Tadahiro Ohmi | 半導体装置およびその製造方法 |
US7955969B2 (en) * | 2005-09-08 | 2011-06-07 | International Rectifier Corporation | Ultra thin FET |
US7476591B2 (en) * | 2006-10-13 | 2009-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral power MOSFET with high breakdown voltage and low on-resistance |
US7508032B2 (en) * | 2007-02-20 | 2009-03-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage device with low on-resistance |
US8304316B2 (en) * | 2007-12-20 | 2012-11-06 | Cambridge Semiconductor Limited | Semiconductor device and method of forming a semiconductor device |
US8174069B2 (en) * | 2008-08-05 | 2012-05-08 | Cambridge Semiconductor Limited | Power semiconductor device and a method of forming a power semiconductor device |
US8026549B2 (en) * | 2008-10-31 | 2011-09-27 | United Microelectronics Corp. | LDMOS with N-type isolation ring and method of fabricating the same |
JPWO2010140666A1 (ja) * | 2009-06-04 | 2012-11-22 | ミツミ電機株式会社 | 半導体基板及びその製造方法、並びに半導体装置及びその製造方法 |
US8816435B2 (en) * | 2010-07-19 | 2014-08-26 | The Board Of Trustees Of The University Of Illinois | Flexible hybrid plasma-semiconductor transistors and arrays |
JP2012124474A (ja) * | 2010-11-15 | 2012-06-28 | Denso Corp | 横型素子を有する半導体装置 |
-
2012
- 2012-12-06 US US13/706,975 patent/US8779555B2/en active Active
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2013
- 2013-05-10 CN CN201310173217.8A patent/CN103855140B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1470073A (zh) * | 2000-09-21 | 2004-01-21 | ���Ű뵼������˾ | 半导体器件及其制作方法 |
CN101414630A (zh) * | 2007-10-15 | 2009-04-22 | 天钰科技股份有限公司 | 横向扩散金属氧化物晶体管 |
CN101626032A (zh) * | 2008-07-09 | 2010-01-13 | 台湾积体电路制造股份有限公司 | 半导体结构 |
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