CN103855045B - The method for repairing and regulating of chip parameter on wafer - Google Patents

The method for repairing and regulating of chip parameter on wafer Download PDF

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Publication number
CN103855045B
CN103855045B CN201210499889.3A CN201210499889A CN103855045B CN 103855045 B CN103855045 B CN 103855045B CN 201210499889 A CN201210499889 A CN 201210499889A CN 103855045 B CN103855045 B CN 103855045B
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CN
China
Prior art keywords
chip
parameter
wafer
test
value
Prior art date
Application number
CN201210499889.3A
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Chinese (zh)
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CN103855045A (en
Inventor
辛吉升
桑浚之
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上海华虹宏力半导体制造有限公司
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Priority to CN201210499889.3A priority Critical patent/CN103855045B/en
Publication of CN103855045A publication Critical patent/CN103855045A/en
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Publication of CN103855045B publication Critical patent/CN103855045B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers

Abstract

The invention discloses a kind of method for repairing and regulating of chip parameter on wafer, comprise the following steps:All chips on test wafer are divided into multiple measuring units by the first step;Second step, a certain parameter that each chip in a certain measuring unit needs to trim is measured by probe card, obtains the characteristic value of the parameter of whole chips in the measuring unit;3rd step, parameter characteristic value to whole chips in the measuring unit is averaged, desired value is trimmed using the mean parameter as all chips in the measuring unit, write simultaneously in chip and used in follow-up test and normal work for chip, so as to complete trimming for a certain measuring unit on test wafer;4th step, repeats second step to the 3rd step, until completing trimming for whole measuring units on whole piece of test wafer.The present invention can improve the degree of accuracy for trimming while scale of mass production is ensured.

Description

The method for repairing and regulating of chip parameter on wafer
Technical field
The present invention relates to a kind of method of testing of large scale integrated circuit, and in particular to chip parameter repaiies on a kind of wafer Tune method.
Background technology
Some parameters that chip occurs when being tested, often in large scale integrated circuit need the phenomenon for trimming.Each Chip might have multiple different parameters to be needed to be trimmed, and such as includes reference voltage value, the function voltage of chip of chip Value, the current value of chip, chip frequency.Because the reason for production, the characteristic value of these parameters of chip may not be in the parameter Use scope within, it is necessary to the parameter value of chip is trimmed use scope to it within, use requirement could be met.
When trimming, some chips need to carry out it is negative trim, and some chips then need to carry out positive trimming;According to it The difference of value indicative, each chip to trim value also different.
But, large-scale logic testing instrument in test chip, from from the point of view of production, often using large-scale same When test, it is impossible to each chip is imposed respectively it is different trim value, cause the degree of accuracy trimmed during scale of mass production too low.Will Want to improve the degree of accuracy for trimming, each parameter that can only be respectively to each chip is trimmed, so again cause the testing time into Increase again, it is impossible to the need for meeting scale of mass production.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of method for repairing and regulating of chip parameter on wafer, and it can shorten Testing time.
In order to solve the above technical problems, the technical solution of the method for repairing and regulating of chip parameter is on wafer of the present invention:
Comprise the following steps:
The first step, all chips that can be covered every time with probe card are a measuring unit, by the institute on test wafer There is chip to be divided into multiple measuring units;
Second step, a certain parameter that each chip in a certain measuring unit needs to trim is measured by probe card, obtains the survey The characteristic value of the parameter of whole chips in examination unit;
The parameter of the chip is reference voltage value, the function magnitude of voltage of chip, the current value or chip of chip of chip Frequency.
3rd step, the parameter characteristic value to whole chip in the measuring unit is averaged, using the mean parameter as All chips trim desired value in the measuring unit, while for chip in follow-up test and normal work in writing chip In use, so as to complete trimming for a certain measuring unit on test wafer;
When averaging, if core number in measuring unit is no less than 32, remove a maximum and one most After small value, then the average value for calculating the measuring unit.
4th step, repeats second step to the 3rd step, and another measuring unit trims on completion test wafer;Until completing whole Whole measuring units trims on piece test wafer.
Or, comprise the following steps:
The first step, all chips that can be covered every time with probe card are a measuring unit, on selection test wafer Polylith region represents unit as test;
The distribution characteristics in polylith Regional Representative's wafer face on the test wafer;Press in wafer face in the polylith region Upper and lower, left and right, in position distribution, or polylith region is respectively positioned on the periphery of test wafer.
Second step, all tests is measured by probe card and represents a certain parameter that each chip in unit needs to trim respectively, Obtain testing the characteristic value for representing the parameter of whole chips in unit;
The parameter of the chip is reference voltage value, the function magnitude of voltage of chip, the current value or chip of chip of chip Frequency.
3rd step, the parameter characteristic value that whole chips in unit are represented to test is averaged, and the mean parameter is made Desired value is trimmed for the test wafer, while used in follow-up test and normal work for chip in writing chip, Complete trimming for whole piece of test wafer.
What the present invention can reach has the technical effect that:
The desired value unification that the present invention trims each parameter inside all measuring units, in chip is written into When, by the way of being written in parallel to, rather than can one by one be serially written, substantially reduce the testing time.
The present invention can improve the degree of accuracy for trimming while scale of mass production is ensured.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description:
Fig. 1 is the schematic diagram of the method for repairing and regulating of chip parameter on wafer of the present invention;
Fig. 2 is comprising 16 schematic diagrames of chip in each measuring unit;
Fig. 3 is the schematic diagram of another embodiment of the present invention.
Description of reference numerals in figure:
1 is measuring unit, and 10 is test wafer,
2 represent unit for test.
Specific embodiment
As shown in figure 1, on wafer of the present invention chip parameter method for repairing and regulating, comprise the following steps:
The first step, all chips that can be covered every time with probe card are a measuring unit, by test wafer 10 All chips are divided into multiple measuring units (being divided into 14 measuring units 1 in Fig. 1);
If as shown in Fig. 2 probe card can once prick 16 chips, 16 are contained up in each measuring unit Chip, such probe card is often pricked can once measure the parameter characteristic value of whole chips in measuring unit;
Second step, a certain parameter that each chip in a certain measuring unit needs to trim is measured by probe card, obtains the survey The characteristic value of the parameter of whole chips in examination unit;
The parameter of chip can be the reference voltage value of chip, the function magnitude of voltage of chip, the current value or chip of chip Frequency;
3rd step, the parameter characteristic value to whole chip in the measuring unit is averaged, using the mean parameter as All chips trim desired value in the measuring unit, while for chip in follow-up test and normal work in writing chip In use, so as to complete trimming for a certain measuring unit on test wafer 10;
If the core number in measuring unit is enough, such as more than 32 chips, a maximum and one can be removed After individual minimum value, then the average value for calculating the measuring unit;
4th step, repeats second step to the 3rd step, and another measuring unit trims on completion test wafer 10;Until completing Whole measuring units trims on whole piece of test wafer 10.
Test wafer is divided into multiple measuring units by the present invention, to all chip under test in each measuring unit using same One trims value, and a measuring unit is once trimmed, to shorten the testing time.
As another embodiment of the present invention, as shown in figure 3, the present invention is comprised the following steps:
The first step, all chips that can be covered every time with probe card are a measuring unit, on selection test wafer 10 Polylith region represent unit (in Fig. 3 select 5 tests represent unit 2) as test;
Polylith region on the test wafer 10 can represent the distribution characteristics in wafer face, and polylith region can be by wafer Upper and lower, left and right in face, in position distribution;
In view of wafer in processing peripheral characteristics situation poor than intermediate characteristic, it is middle to test the data for representing unit Can also be only for reference, and the several data for representing unit of testing in periphery are only taken as the data source of desired value;Or periphery is surveyed The hits that examination represents unit continues to increase to proper number;
Second step, measure that the test of whole (five) represents that each chip in unit needs to trim respectively by probe card is a certain Parameter, obtains testing the characteristic value for representing the parameter of whole chips in unit;
The parameter of chip can be the reference voltage value of chip, the function magnitude of voltage of chip, the current value or chip of chip Frequency;
3rd step, the parameter characteristic value that whole chips in unit are represented to test is averaged, and the mean parameter is made Desired value is trimmed for the test wafer 10, while in writing chip, making in follow-up test and normal work for chip With completing trimming for whole piece of test wafer 10.
The present invention trims desired value to all chip under test in whole piece of test wafer using same, can will trim target The analysis times of value are reduced to a certain extent (such as five times), to shorten the testing time.
The present invention realizes while carrying out the test that trims of whole piece of wafer.

Claims (6)

1. on a kind of wafer chip parameter method for repairing and regulating, it is characterised in that comprise the following steps:
The first step, all chips that can be covered every time with probe card are a measuring unit, by all cores on test wafer Piece is divided into multiple measuring units;
Second step, a certain parameter that each chip in a certain measuring unit needs to trim is measured by probe card, obtains the test list The characteristic value of the parameter of whole chip in position;
3rd step, the parameter characteristic value to whole chips in the measuring unit is averaged, using the mean parameter as the survey All chips trim desired value in examination unit, while make in follow-up test and normal work for chip in writing chip With so as to complete trimming for a certain measuring unit on test wafer;
4th step, repeats second step to the 3rd step, and another measuring unit trims on completion test wafer;Until completing whole piece of survey Whole measuring units trims on examination wafer.
2. on wafer according to claim 1 chip parameter method for repairing and regulating, it is characterised in that the parameter of the chip is The reference voltage value of chip, the function magnitude of voltage of chip, the current value or chip frequency of chip.
3. on wafer according to claim 1 chip parameter method for repairing and regulating, it is characterised in that the 3rd step is averaged During value, if core number in measuring unit is no less than 32, after removing a maximum and a minimum value, then calculate The average value of the measuring unit.
4. on a kind of wafer chip parameter method for repairing and regulating, it is characterised in that comprise the following steps:
The first step, all chips that can be covered every time with probe card are a measuring unit, the polylith on selection test wafer Region represents unit as test;
Second step, all tests is measured by probe card and represents a certain parameter that each chip in unit needs to trim respectively, is obtained Test represents the characteristic value of the parameter of whole chips in unit;
3rd step, the parameter characteristic value that whole chips are represented in unit to test is averaged, using the mean parameter as this Test wafer trims desired value, while being used in follow-up test and normal work for chip in writing chip, completes Whole piece of test wafer is trimmed.
5. on wafer according to claim 4 chip parameter method for repairing and regulating, it is characterised in that on the test wafer Distribution characteristics in polylith Regional Representative's wafer face;The polylith region press upper and lower, left and right in wafer face, in position point Cloth, or polylith region is respectively positioned on the periphery of test wafer.
6. on wafer according to claim 4 chip parameter method for repairing and regulating, it is characterised in that the parameter of the chip is The reference voltage value of chip, the function magnitude of voltage of chip, the current value or chip frequency of chip.
CN201210499889.3A 2012-11-29 2012-11-29 The method for repairing and regulating of chip parameter on wafer CN103855045B (en)

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Publication number Priority date Publication date Assignee Title
CN104538327B (en) * 2014-12-29 2017-08-08 上海华虹宏力半导体制造有限公司 A kind of method for repairing and regulating
CN105206305B (en) * 2015-09-22 2018-08-21 上海华虹宏力半导体制造有限公司 Increase the method for flash device windows by test program
CN105242192B (en) * 2015-10-09 2018-04-17 上海华虹宏力半导体制造有限公司 Crystal round test approach
CN105353293B (en) * 2015-10-09 2018-04-17 上海华虹宏力半导体制造有限公司 Crystal round test approach
CN105551993B (en) * 2015-12-23 2018-06-12 上海威伏半导体有限公司 The method for repairing and regulating and device of a kind of wafer parameters
CN109901650B (en) * 2017-12-07 2020-11-06 北京确安科技股份有限公司 Reference source trimming method of embedded flash chip
CN109085491A (en) * 2018-08-08 2018-12-25 上海华力微电子有限公司 A method of improving analog quantity Trimming program test efficiency
CN109613420B (en) * 2019-01-30 2021-04-06 上海华虹宏力半导体制造有限公司 Chip testing method

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JP2000009655A (en) * 1998-06-25 2000-01-14 Kobe Steel Ltd Visual inspection device
US6605479B1 (en) * 2001-07-27 2003-08-12 Advanced Micro Devices, Inc. Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same
JP4413130B2 (en) * 2004-11-29 2010-02-10 Okiセミコンダクタ株式会社 Semiconductor device inspection method using probe card and semiconductor device inspected by the inspection method
JP2007066923A (en) * 2005-08-29 2007-03-15 Matsushita Electric Ind Co Ltd Method and apparatus for burning in wafer level
CN100511622C (en) * 2007-02-15 2009-07-08 北京巨数数字技术开发有限公司 Method for emending output current by amending semiconductor pin test voltage
CN102662092B (en) * 2012-04-28 2014-12-31 无锡中星微电子有限公司 Device and method for testing wafer

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