CN103824937A - High speed nano two-end nonvolatile storage and manufacturing method thereof - Google Patents
High speed nano two-end nonvolatile storage and manufacturing method thereof Download PDFInfo
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- CN103824937A CN103824937A CN201410066746.2A CN201410066746A CN103824937A CN 103824937 A CN103824937 A CN 103824937A CN 201410066746 A CN201410066746 A CN 201410066746A CN 103824937 A CN103824937 A CN 103824937A
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Abstract
The invention discloses a high speed nano two-end nonvolatile storage and a manufacturing method thereof. The high speed nano two-end nonvolatile storage is characterized in that p-type doping one-dimensional nanomaterials, a graphene electrode and a metal electrode are distributed on an insulating substrate, and the graphene electrode is communicated with the metal electrode through the p-type doping one-dimensional nanomaterials; the p-type doping one-dimensional nanomaterials are p-type doping ZnS one-dimensional nanomaterials or p-type doping ZnSe one-dimensional nanomaterials; the metal electrode is a Cu electrode or a Ag electrode. The manufacturing method of the high speed nano two-end nonvolatile storage is simple, easy to control, high in rate of finished products and capable of being applied to large-scale integration conveniently. The manufactured storage has the excellent characteristics of being low in programming voltage, high in reading/writing speed, long in retention time and the like, thereby having a potential application prospect in development of a low-power dissipation, high speed and high integration density storage.
Description
Technical field
The invention belongs to technical field of semiconductor device, be specifically related to a kind of high speed nanometer two ends nonvolatile memory and preparation method thereof.
Background technology
Semiconductor memory is an important branch field in microelectronics research, plays information is stored and the function of processing, and is widely used in various microelectronic devices.Wherein nonvolatile storage is being played the part of more and more important role in semicon industry, is bringing into play great effect.Along with the high-tech develop rapidly of numeral, the performance of memory is also had higher requirement, as high-speed, high density, low-power consumption, long-life and less size etc.Especially when the characteristic size of device reduces, the problems such as the read or write speed of traditional floating gate structure memory device and the contradiction of reliability and gate medium electric leakage, have limited further developing of legacy memory to a great extent.Therefore, develop a kind of brand-new Information Access technology and caused researcher's broad interest.In the application study of current One, Dimensional Semiconductor Nano Materials, building high-performance nonvolatile memory is one of study hotspot.The report retrieving mainly concentrates on and builds [W.Y.Fu, Z.Xu, X.D.Bai, C.Z.Gu, E.G.Wang, Nano Lett.2009,9,921 on nano field-effect pipe; M.Rinkio, A.Johansson, G.S.Paraoanu, P.Torma, Nano Lett.2009,9,643; J.I.Sohn, S.S.Choi, S.M.Morris, J.S.Bendall, H.J.Coles, W.K.Hong, G.Jo, T.Lee, M.E.Welland, Nano Lett.2010,10,4316.], sum up mainly and adjust and keep trap-charge in storage medium, to realize charge storage ability by controlling grid, conventional storage medium has metallic nano crystal, ferroelectric thin film and high k insulating material etc.Due to nano field-effect pipe memory there is large-size, restive threshold voltage shift, high program voltage, compared with the long read/write time and preparation process is complicated the shortcoming such as is difficult to repeat and has seriously hindered its application.
Summary of the invention
The present invention is for avoiding the existing weak point of above-mentioned prior art, provide a kind of high speed nanometer two ends nonvolatile memory and preparation method thereof, to realizing the nanometer nonvolatile memory that preparation is simple in structure, size is little, program voltage is low, read/write speed is high.
The present invention is technical solution problem, adopts following technical scheme:
High speed nanometer of the present invention two ends nonvolatile memory, be characterized in: described memory is in dielectric substrate, to be distributed with p-type doped one-dimensional nano material, Graphene electrodes and metal electrode, described Graphene electrodes and metal electrode are communicated with by p-type doped one-dimensional nano material; Described p-type doped one-dimensional nano material is p-type doped ZnS monodimension nanometer material or p-type doped ZnS e monodimension nanometer material; Described metal electrode is Cu electrode or Ag electrode.
Memory of the present invention, its feature is also: described dielectric substrate is silicon chip or the surperficial silicon chip that is covered with silicon nitride layer that quartz glass, surface are covered with silicon oxide layer.
Described p-type doped ZnS monodimension nanometer material is Ag doped ZnS monodimension nanometer material or Cu doped ZnS monodimension nanometer material; Described p-type doped ZnS e monodimension nanometer material is Ag doped ZnS e monodimension nanometer material or Cu doped ZnS e monodimension nanometer material.
The thickness of described metal electrode (4) is 50-100nm.Confirm through great many of experiments, thickness of electrode is excessively thin is difficult to obtain excellent device performance, is blocked uply unfavorable for that device is integrated, and 50-100nm is optimal selection.
The preparation method of high speed nanometer of the present invention two ends nonvolatile memory, is characterized in carrying out as follows:
A, p-type doped one-dimensional nano material is dispersed in dielectric substrate;
B, by the electrode pattern of photoetching process photoetching metal electrode in the dielectric substrate of completing steps a, then prepare metal electrode by magnetron sputtering method or electron-beam vapor deposition method in the electrode pattern region of described metal electrode;
C, by the electrode pattern of photoetching process photoetching Graphene electrodes in the dielectric substrate of completing steps b, then Graphene is transferred to the electrode pattern region of Graphene electrodes;
D, by the dielectric substrate of completing steps c at N
2under atmosphere or under Ar atmosphere, anneal, 300～500 ° of C of annealing temperature, annealing time 5～15 minutes.Confirm through test of many times, pressure, is generally and is convenient to implement substantially without impact annealing effect, can select 0.01MPa～0.09MPa
High speed nanometer of the present invention two ends nonvolatile memory is to utilize interfacial reaction, between Cu or Ag electrode material and nano material, form nanoscale boundary layer, these boundary layers, under the effect of programming signal, produce conductive filament or conductive filament and disconnect the variation that realizes the high low-resistance of device.
Compared with the prior art, beneficial effect of the present invention is embodied in:
1, high speed nanometer of the present invention two ends nonvolatile memory preparation method simple, be easy to control, rate of finished products is high, it is integrated to be on a large scale convenient to be applied to, and the excellent specific properties such as the prepared memory of the present invention has that program voltage is low, read/write speed is fast and the retention time is long, by exploitation low-power consumption, at a high speed, there is potential application prospect in high integration memory;
2, the nano-interface layer forming between control Cu of the present invention or Ag electrode material and nano material is (as Cu
2s or Ag
2s etc.), realize the preparation of two ends nonvolatile memories, improve large, the restive threshold voltage shift of traditional nano field-effect pipe memory-size, the shortcoming such as program voltage is high, the read/write time is long and preparation process is complicated.
Accompanying drawing explanation
Fig. 1 is the structural representation of high speed nanometer of the present invention two ends nonvolatile memory;
Fig. 2 is the prepared memory current-voltage curve of embodiment 1;
Fig. 3 is the prepared memory open/close state electric current-cycle-index curve of embodiment 1;
Fig. 4 keeps curve at the prepared memory open/close state time of embodiment 1;
Fig. 5 is the prepared memory current-voltage curve of embodiment 2;
Fig. 6 is the prepared memory open/close state electric current-cycle-index curve of embodiment 2;
Fig. 7 keeps curve at the prepared memory open/close state time of embodiment 2;
Fig. 8 is the prepared memory current-voltage curve of embodiment 3;
Fig. 9 is the prepared memory open/close state electric current-cycle-index curve of embodiment 3;
Figure 10 keeps curve at the prepared memory open/close state time of embodiment 3;
Number in the figure: 1 dielectric substrate; 2p type doped one-dimensional nano material; 3 Graphene electrodes; 4 metal electrodes.
Specific embodiment
As shown in Figure 1, the structure of high speed nanometer two ends nonvolatile memory is: in dielectric substrate 1, be distributed with p-type doped one-dimensional nano material 2, Graphene electrodes 3 and metal electrode 4, Graphene electrodes 3 and metal electrode 4 are communicated with by p-type doped one-dimensional nano material 2; P-type doped one-dimensional nano material 2 is p-type doped ZnS monodimension nanometer material or p-type doped ZnS e monodimension nanometer material; Metal electrode 4 is Cu electrode or Ag electrode.
The present embodiment using the p-type ZnS nanobelt of Cu doping as p-type doped one-dimensional nano material 2, take Cu electrode as metal electrode 4, have thickness as the silicon chip of 300nm silicon oxide layer is as dielectric substrate 1 take surface length, prepared p-type ZnS nanobelt/Cu electrode high speed two ends nonvolatile memory, concrete steps are as follows:
(1) under room temperature, after having thickness to be the silicon chip ultrasonic cleaning totally of 300nm silica surface length, as dispersion liquid, p-type doped ZnS nanobelt synthetic chemical gaseous phase is added to dispersion liquid with alcohol, ultrasonic concussion is evenly suspended in dispersion liquid nanobelt; And the dispersion liquid that contains ZnS nanobelt is spin-coated on to clean length has on the silicon chip of silicon oxide layer;
(2) spin coating photoresist on the silicon chip that scribbles ZnS nanobelt, and make the electrode pattern of metal electrode (4) by lithography;
(3) prepare one deck Cu electrode by magnetron sputtering method in the electrode pattern region of the metal electrode 4 of photoetching, thickness is 50nm;
(4) adopt the electrode pattern of secondary light carving method photoetching Graphene electrodes 3 in the dielectric substrate of completing steps b, then Graphene is transferred to the electrode pattern region of Graphene electrodes 3;
(5) dielectric substrate of completing steps (4) is annealed under Ar atmosphere, 400 ° of C of annealing temperature, annealing time 10 minutes, obtains p-type ZnS nanobelt/Cu electrode high speed two ends nonvolatile memory.
For characterizing prepared p-type ZnS nanobelt/Cu electrode high speed two ends nonvolatile memory, the storage characteristics that the present embodiment utilizes KEITHLEY4200-SCS and Keithley3401 signal generator to test memory, Fig. 2 is the I-V characteristic of device, finds back that stagnant phenomenon is comparatively obvious; Fig. 3 and 4 is for program voltage is ± 2V, and programming time is the test result under 100ns, therefrom can obviously find out under lower program voltage, can realize and repeat stable quick read/write operation, and on off state current ratio is greater than 10
6, the retention time is longer than 10
5second.
The p-type ZnS nanobelt that the present embodiment adulterates using Ag is as p-type doped one-dimensional nano material 2, take Ag electrode as metal electrode 4, take quartz glass as dielectric substrate 1, prepared p-type ZnS nanobelt/Ag electrode high speed two ends nonvolatile memory, concrete steps are as follows:
(1) under room temperature, by after quartz glass ultrasonic cleaning totally, as dispersion liquid, p-type doped ZnS nanobelt synthetic chemical gaseous phase is added to dispersion liquid with alcohol, ultrasonic concussion is evenly suspended in dispersion liquid nanobelt; And the dispersion liquid that contains ZnS nanobelt is spin-coated on to clean quartz glass;
(2) spin coating photoresist on the silicon chip that scribbles ZnS nanobelt, and make the electrode pattern of metal electrode 4 by lithography;
(3) prepare one deck Ag electrode by magnetron sputtering method in the electrode pattern region of the metal electrode 4 of photoetching, thickness is 60nm;
(4) adopt the electrode pattern of secondary light carving method photoetching Graphene electrodes 3 in the dielectric substrate of completing steps b, then Graphene is transferred to the electrode pattern region of Graphene electrodes 3;
(5) by the dielectric substrate of completing steps (4) at N
2under atmosphere, anneal, 500 ° of C of annealing temperature, annealing time 15 minutes, obtains p-type ZnS nanobelt/Ag electrode high speed two ends nonvolatile memory.
For characterizing prepared p-type ZnS nanobelt/Ag electrode high speed two ends nonvolatile memory, the present embodiment utilizes the storage characteristics of KEITHLEY4200-SCS and Keithley3401 signal generator testing memory, Fig. 5 is the I-V characteristic of device, finds back that stagnant phenomenon is comparatively obvious; Fig. 6 and 7 is for program voltage is ± 2V, and programming time is the test result under 100ns, therefrom can obviously find out under lower program voltage, can realize and repeat stable quick read/write operation, and on off state current ratio is greater than 10
6, the retention time is longer than 10
5second.
The present embodiment using the p-type ZnSe nanobelt of Ag doping as p-type doped one-dimensional nano material 2, take Cu electrode as metal electrode 4, have thickness as the silicon chip of 300nm silicon nitride layer is as dielectric substrate 1 take surface length, prepared p-type ZnSe nanobelt/Cu electrode high speed two ends nonvolatile memory, concrete steps are as follows:
(1) under room temperature, after having thickness to be the silicon chip ultrasonic cleaning totally of 300nm silicon nitride surface length, as dispersion liquid, p-type doped ZnS e nanobelt synthetic chemical gaseous phase is added to dispersion liquid with alcohol, ultrasonic concussion is evenly suspended in dispersion liquid nanobelt; And the dispersion liquid that contains ZnSe nanobelt is spin-coated on to clean length has on the silicon chip of silica;
(2) spin coating photoresist on the silicon chip that scribbles ZnSe nanobelt, and make the electrode pattern of metal electrode 4 by lithography;
(3) prepare one deck Cu electrode by magnetron sputtering method in the electrode pattern region of the metal electrode 4 of photoetching, thickness is 50nm;
(4) adopt the electrode pattern of secondary light carving method photoetching Graphene electrodes 3 in the dielectric substrate of completing steps b, then Graphene is transferred to the electrode pattern region of Graphene electrodes 3;
(5) dielectric substrate of completing steps (4) is annealed under Ar atmosphere, 300 ° of C of annealing temperature, annealing time 5 minutes, obtains p-type ZnSe nanobelt/Cu electrode high speed two ends nonvolatile memory.
For characterizing prepared p-type ZnSe nanobelt/Cu electrode high speed two ends nonvolatile memory, the present embodiment utilizes the storage characteristics of KEITHLEY4200-SCS and Keithley3401 signal generator testing memory, Fig. 8 is the I-V characteristic of device, finds back that stagnant phenomenon is comparatively obvious; Fig. 9 and 10 is for program voltage is ± 2V, and programming time is the test result under 100ns, therefrom can obviously find out under lower program voltage, can realize and repeat stable quick read/write operation, and on off state current ratio is greater than 10
6, the retention time is longer than 10
5second.
Claims (5)
1. a high speed nanometer two ends nonvolatile memory, it is characterized in that: described memory is in dielectric substrate (1), to be distributed with p-type doped one-dimensional nano material (2), Graphene electrodes (3) and metal electrode (4), described Graphene electrodes (3) and metal electrode (4) are communicated with by p-type doped one-dimensional nano material (2); Described p-type doped one-dimensional nano material (2) is p-type doped ZnS monodimension nanometer material or p-type doped ZnS e monodimension nanometer material; Described metal electrode (4) is Cu electrode or Ag electrode.
2. memory according to claim 1, is characterized in that: described dielectric substrate (1) is silicon chip or the surperficial silicon chip that is covered with silicon nitride layer that quartz glass, surface are covered with silicon oxide layer.
3. memory according to claim 1, is characterized in that: described p-type doped ZnS monodimension nanometer material is Ag doped ZnS monodimension nanometer material or Cu doped ZnS monodimension nanometer material; Described p-type doped ZnS e monodimension nanometer material is Ag doped ZnS e monodimension nanometer material or Cu doped ZnS e monodimension nanometer material.
4. memory according to claim 1, is characterized in that: the thickness of described metal electrode (4) is 50-100nm.
5. a preparation method for the high speed nanometer two ends nonvolatile memory described in claim 1,2,3 or 4, is characterized in that carrying out as follows:
A, p-type doped one-dimensional nano material (2) is dispersed in dielectric substrate (1);
B, electrode pattern by photoetching process at the upper photoetching metal electrode (4) of the dielectric substrate (1) of completing steps a, then prepare metal electrode (4) by magnetron sputtering method or electron-beam vapor deposition method in the electrode pattern region of described metal electrode (4);
C, electrode pattern by photoetching process in the upper photoetching Graphene electrodes (3) of the dielectric substrate (1) of completing steps b, then transfer to Graphene the electrode pattern region of Graphene electrodes (3);
D, by the dielectric substrate of completing steps c (1) at N
2under atmosphere or under Ar atmosphere, anneal, 300～500 ℃ of annealing temperatures, annealing time 5～15 minutes.
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| CN104993048A (en) * | 2015-06-25 | 2015-10-21 | 南昌大学 | Resistor-type storage unit based on annealing adjustment, and preparation method |
| CN105118887A (en) * | 2015-07-14 | 2015-12-02 | 合肥工业大学 | Graphene/zinc selenide nanobelt schottky junction blue-ray photoelectric switch modified by indium nanoparticle array and preparation method thereof |
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Cited By (3)
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| CN104993048A (en) * | 2015-06-25 | 2015-10-21 | 南昌大学 | Resistor-type storage unit based on annealing adjustment, and preparation method |
| CN105118887A (en) * | 2015-07-14 | 2015-12-02 | 合肥工业大学 | Graphene/zinc selenide nanobelt schottky junction blue-ray photoelectric switch modified by indium nanoparticle array and preparation method thereof |
| CN105118887B (en) * | 2015-07-14 | 2016-11-30 | 合肥工业大学 | Graphene/zinc selenide nanobelt schottky junction blue light photoswitch that a kind of indium nanometer particle array is modified and preparation method thereof |
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