CN103824803A - Field oxide layer forming method - Google Patents
Field oxide layer forming method Download PDFInfo
- Publication number
- CN103824803A CN103824803A CN201410081176.4A CN201410081176A CN103824803A CN 103824803 A CN103824803 A CN 103824803A CN 201410081176 A CN201410081176 A CN 201410081176A CN 103824803 A CN103824803 A CN 103824803A
- Authority
- CN
- China
- Prior art keywords
- field oxide
- groove
- formation method
- semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 89
- 239000004065 semiconductor Substances 0.000 claims abstract description 117
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 63
- 230000003647 oxidation Effects 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001427 coherent effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
Abstract
The invention provides a field oxide layer forming method comprising the steps of providing a semiconductor substrate; forming a plurality of first grooves in the semiconductor substrate, and forming first semiconductor columns between every two adjacent first grooves; and carrying out thermal oxidation on the first semiconductor columns until the first semiconductor columns are completely oxidized to form thermal oxidation layers, wherein the thermal oxidation layers are connected with one other to form a field oxide layer filling the first grooves. The plurality of first grooves are formed by the forming method, so that the thermal oxidation area is greatly increased in a thermal oxidation process; in addition, the first semiconductor columns are relatively small in average width and are easily completely oxidized, so that the oxidation time can be greatly shortened, namely the whole process period is shortened, and the process efficiency is increased; moreover, the insulation property of the formed field oxide layer is good, so that the performance of a semiconductor device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially relate to a kind of formation method of field oxide.
Background technology
Along with reducing of dimensions of semiconductor devices, the insulation request of semiconductor device is more and more higher.For example, in the time manufacturing power transistor, need in Semiconductor substrate, form field oxide (field oxide), described field oxide is for isolation of semiconductor devices, its thickness is conventionally larger, to completely cut off tracking current, thereby prevent that field-effect transistor is because of situations such as tracking current open without reason.
The formation method of existing field oxide has two kinds, and a kind of method is sedimentation, but the field oxide that sedimentation forms is not only of poor quality, and thickness homogeneity (uniformity) is also poor; Another kind method is thermal oxidation method, but existing thermal oxidation method need to be through the very long especially process time in thermal oxidation furnace, increase process costs, and, in the time that field oxide is used in making power semiconductor, in thermal oxidation process, the ion that is arranged in Semiconductor substrate doped region can upwards diffuse to epitaxial loayer (EPI), therefore, conventionally need to use thicker epitaxial loayer, and thicker epitaxial loayer causes the hydraulic performance decline of the semiconductor device such as high-voltage power transistor.
For this reason, need a kind of formation method of new field oxide, to avoid the problem of hydraulic performance decline of the high and semiconductor device of process costs.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of field oxide, to improve the quality of field oxide, and shortens the process time, saves process costs.
For addressing the above problem, the invention provides a kind of formation method of field oxide, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form multiple the first grooves, between adjacent described the first groove, form the first semiconductor column;
Described the first semiconductor column is carried out to thermal oxidation technology and formed thermal oxide layer until described the first semiconductor column is all oxidized, described thermal oxide layer is interconnected to form the field oxide of filling full described the first groove.
Optionally, the mean breadth sum of described the first groove and described the first semiconductor column is more than or equal to technique pitch, and is less than or equal to 1 μ m.
Optionally, described formation method also comprises:
In forming described the first groove, in described Semiconductor substrate, form the second groove;
In forming described field oxide, form gate oxide at bottom and the sidewall of described the second groove.
Optionally, the mean breadth of described the first groove is less than or equal to the thickness of described gate oxide.
Optionally, the depth bounds of described the first groove is 0.5 μ m～2.5 μ m.
Optionally, all the width sum of described the first groove and whole described the first semiconductor column is the more than 5 times of described the second groove width.
Optionally, the temperature range that described thermal oxidation technology adopts comprises 800 ℃～1500 ℃, and the oxygen flow scope of employing comprises 0.1sccm～15sccm.
Optionally, described the first groove is dovetail grooved.
Optionally, described Semiconductor substrate is epitaxial loayer.
Optionally, the material of described Semiconductor substrate is silicon.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, adopt and in Semiconductor substrate, form multiple the first grooves, between adjacent described the first groove, form the first semiconductor column, then described the first semiconductor column is carried out to thermal oxidation technology and formed thermal oxide layer until described the first semiconductor column is all oxidized, described thermal oxide layer is interconnected to form the field oxide of filling full described the first groove.Owing to having formed multiple the first grooves, therefore in thermal oxidation technology process, thermal oxidation area significantly increases, and the first semiconductor column mean breadth is less, is easy to be all oxidized, therefore, can significantly shorten oxidization time, shorten whole process cycle, improve process efficiency, and the field oxide good insulation preformance forming, thereby the performance of raising semiconductor device.And, because being is inwardly oxidized and forms field oxide downwards, therefore, field oxide can be more not high than semiconductor substrate surface, thereby, after the making that completes field oxide, the surface profile of total is very smooth, thereby can further shorten the time of subsequent planarization technique.
Further, in forming described the first groove, in described Semiconductor substrate, form the second groove, in forming described field oxide, bottom and sidewall at described the second groove form gate oxide, in the forming process of field oxide, form gate oxide simultaneously, thereby have saved processing step, process simplification, further shortens the process time and saves process costs.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is the generalized section corresponding to the each step of formation method of one embodiment of the invention field oxide;
Fig. 3 to Fig. 4 is the generalized section corresponding to the each step of formation method of further embodiment of this invention field oxide.
Embodiment
In the formation method of existing field oxide, if adopt sedimentation, the field oxide of formation is not only of poor quality, and thickness homogeneity (uniformity) is also poor, if employing thermal oxidation method, needs the very long especially process time (unclear and coherent), process costs is high.
For this reason, the invention provides a kind of formation method of field oxide, described formation method forms multiple the first grooves in Semiconductor substrate, between adjacent described the first groove, form the first semiconductor column, then described the first semiconductor column is carried out to thermal oxidation technology and formed thermal oxide layer until described the first semiconductor column is all oxidized, described thermal oxide layer is interconnected to form the field oxide of filling full described the first groove.Owing to having formed multiple the first grooves, therefore in thermal oxidation technology process, thermal oxidation area significantly increases, and the first semiconductor column mean breadth is less, is easy to be all oxidized, therefore, can significantly shorten oxidization time, shorten whole process cycle, improve process efficiency, and the field oxide good insulation preformance forming, thereby the performance of raising semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The embodiment of the present invention provides a kind of formation method of field oxide, incorporated by reference to reference to figure 1 and Fig. 2.
Please refer to Fig. 1, Semiconductor substrate 100 is provided.
In the present embodiment, Semiconductor substrate 100 can be silicon substrate, germanium substrate or germanium silicon substrate etc., can be also semiconductor-on-insulator substrate 100, and the present embodiment is take silicon substrate as example, and the material of Semiconductor substrate 100 is silicon.Semiconductor substrate 100 provides a carrier for forming various semiconductor device.
Please continue to refer to Fig. 1, in Semiconductor substrate 100, form multiple the first grooves 101, between adjacent two the first grooves 101, form the first semiconductor column 102, and the first groove 101 is dovetail grooved.
In the present embodiment, if the first semiconductor column 102 mean breadth from top to bottom equates, it is so follow-up when the first semiconductor column 102 is carried out to thermal oxidation technology, the more difficult contact oxygen of the first semiconductor column 102 part more down, therefore common the first semiconductor column 102 is reduced from top to bottom gradually by the speed of complete oxidation, cause semiconductor column 102 base sections to be difficult to by complete oxidation, and whole oxidizing process medium velocity is unbalanced.
For this reason, the present embodiment, by controlling corresponding etch process, is controlled the first groove 101 etchings is to dovetail grooved, thereby make the first semiconductor column 102 between adjacent two the first grooves 101 will become inverted ladder type, and the first semiconductor column 102 is wide at the top and narrow at the bottom.Like this, more down cross-sectional area is larger for the first groove 101 on the one hand, is conducive to oxygen and contacts with the first semiconductor column 102; More down width is less for the first semiconductor column 102 on the other hand, more easily by complete oxidation.Therefore follow-up when the first semiconductor column 102 is carried out to thermal oxidation technology, the first semiconductor column 102 be can tune to substantially equal from top to bottom by the speed of complete oxidation, thereby makes the field oxide better quality forming.
It should be noted that, cannot all be filled full in order to prevent that the first groove 101 bottoms are too wide, the scope of the angle α of the present embodiment control the first groove 101 bottoms is 85 °～90 °, and guarantees that the sidewall of the first groove 101 is vertical plane or inclined-plane substantially.
In the present embodiment, the mean breadth W1 of the first semiconductor column 102 is less than the mean breadth W2 of the first groove 101, the mean breadth W2 of the first groove 101 is less than or equal to the thickness of gate oxide transistor layer in Semiconductor substrate 100, the mean breadth W2 sum of the mean breadth W1 of the first semiconductor column 102 and the first groove 101 is greater than or equal to technique pitch (pitch), and the mean breadth W2 sum of the mean breadth W1 of the first semiconductor column 102 and the first groove 101 is less than or equal to 1 μ m.
In the present embodiment, the depth bounds (not mark) of the first groove 101 can be 0.5 μ m～2.5 μ m, the degree of depth of the first groove 101 determines the thickness of the final field oxide forming, therefore, can need to set according to the thickness of field oxide the degree of depth of the first groove 101, and the thickness of the field oxide conventionally forming according to the method for the present embodiment is greater than the degree of depth of the first groove 101, and therefore, the degree of depth of the first groove 101 can be arranged to be slightly less than the thickness of the final field oxide that will form.
In the present embodiment, the forming process of the first groove 101 can be: exposed and developing process in the Semiconductor substrate 100 that scribbles photoresist by mask plate, form patterned photoresist (not shown), take patterned photoresist as mask, adopt chemical reaction ion etching Semiconductor substrate 100 to form again.The etching gas that described chemical reaction ion etching adopts can comprise Cl
2, SF
6with HBr etc.
Please refer to Fig. 2, the first semiconductor column 102 shown in Fig. 1 is carried out to thermal oxidation technology and form thermal oxide layers 111 until the first semiconductor column 102 quilts are all oxidized, the field oxide 110(adjacent heat oxide layer 111 that whole thermal oxide layers 111 are interconnected to form full the first groove 101 of filling separates to show difference with dotted line).
In the present embodiment, described thermal oxidation technology can be wet process oxidation technology, can be also the combination of wet process oxidation technology and dry oxidation technique.
The present embodiment is in the process of concrete oxidation, the first semiconductor column 102 is progressively oxidized in the middle of two side direction, therefore, (silicon) material thickness of actual oxidation is only the half of the first semiconductor column 102 mean breadth W1, but, need to guarantee after oxidation, what the oxidized layer of the first groove 101 grew is partially filled full the first groove 101, that is: make thermal oxide layer 111 be interconnected to form field oxide 110 simultaneously.
Concrete, the degree of depth that can make the first groove 101 is 1 μ m, selects the wet oxygen technique of growth 1 μ m, adopts the boiler tube of 8 inches to be oxidized.First Semiconductor substrate 100 is placed in to boiler tube, the temperature range of employing comprises 800 ℃～1500 ℃, and the oxygen flow scope of employing comprises 0.1sccm～15sccm, and can also have N in gas
2, H
2deng.
In the present embodiment, final field oxide 110 thickness that form can be greater than the degree of depth of the first groove 101, and (1 μ m), this be because, form in the process of field oxide 110 in oxidation, except the first semiconductor column 102 is oxidized to the part of field oxide 110, be positioned at an also part for oxidized formation field oxide 110 of Semiconductor substrate 100 for the first groove 101 bottoms, the thickness of this part is generally the half of the first semiconductor column 102 mean breadths, therefore, the concrete thickness of field oxide 110 be 1 μ m add again at least the first semiconductor column 102 mean breadth W1 1/2nd.
The formation method of the field oxide that employing the present embodiment provides, thermal oxidation area significantly increases, and meanwhile, the real material thickness being oxidized is only the half of the first semiconductor column 102 mean breadth W1, and therefore, oxidization time can be saved in a large number.In fact, oxidation rate along with the increase of oxide thickness presents the situation of successively decreasing, that is, supposes that oxidation generates the oxide layer of 2X thickness, and required oxidization time is more than oxidation generates the twice of X thickness oxide layer.Be oxidized conversely speaking, the oxide layer of X thickness, the needed time is less than 1/2nd of original oxidation 2X thickness oxide layer required time.Therefore, the present embodiment, by controlling the mean breadth of the first groove 101 and the mean breadth of the first Semiconductor substrate 100, can be controlled the time of thermal oxidation technology at 1min～10h.Concrete, be the first groove 101 of 1 μ m for the degree of depth, oxidization time approximately can be controlled in 1h～2h, and field oxide 110 thickness that form are greater than 1 μ m.And if be oxidized with existing method, for form thickness be the field oxide 110 of 1 μ m, oxidization time needs 5h～10h conventionally.
In the present embodiment, the width of field oxide 110 is the more than 5 times of transistor channel mean breadth in device region, to guarantee that field oxide 110 plays corresponding insulation protection effect.But meanwhile,, in order not make field oxide 110 thickness too large, thereby the mean breadth of control the first groove 101 is less.Concrete, control the mean breadth of the first groove 101 below 0.5 μ m, for example mean breadth of the first groove 101 is specially 0.3 μ m.Now, the first more groove 101 need to be set, to guarantee width the more than 5 times of transistor channel mean breadth in device region of field oxide 110, therefore conventionally the number of the first groove 101 can be arranged on more than 5.
In the formation method of the field oxide that the present embodiment provides, by first forming the first groove 101 and the first semiconductor column 102, again the first semiconductor column 102 is carried out to thermal oxidation technology until form the field oxide 110 of filling full the first groove 101, thereby the formation time of field oxide 110 is significantly shortened, conventionally can foreshorten to 1/5 to 1/2 of (by existing method) script required time, thereby saving process costs, and field oxide 110 quality that form are good, performance of semiconductor device is improved.
In addition, in the formation method of the field oxide that the present embodiment provides, because being is inwardly oxidized and forms field oxide 110 downwards, therefore, field oxide 110 can be more not high than Semiconductor substrate 100 surfaces, thereby, after completing the making of field oxide 110, the surface profile of total is very smooth, thereby can further shorten the time of subsequent planarization technique.
In addition, in the formation method of the field oxide that the present embodiment provides, if the field oxide forming 110 is the isolation as surface leakage, realizing required Semiconductor substrate 100 areas of isolation can, much smaller than the method that adds PN junction isolation with a tradition oxidation, save Semiconductor substrate 100 areas and naturally can in the Semiconductor substrate 100 by same size, make more chip.
Further embodiment of this invention provides the formation method of another field oxide, incorporated by reference to reference to figure 3 and Fig. 4.
Please refer to Fig. 3, Semiconductor substrate 210 is provided.
In the present embodiment, Semiconductor substrate 210 is epitaxial loayer, and Semiconductor substrate 210 is formed on semiconductor base 200, as shown in Figure 3.Semiconductor base 200 can be silicon base, germanium substrate or germanium silicon base etc., and the present embodiment is take silicon base as example, and the material of semiconductor base 200 is silicon, and now as the Semiconductor substrate 210 of epitaxial loayer, its material is also silicon.
Please continue to refer to Fig. 3, in Semiconductor substrate 210, form multiple the first grooves 211 and the second groove 213, between adjacent the first groove 211, form the first semiconductor column 212.
In the present embodiment, the first groove 211 and the first semiconductor column 212 are used to form field oxide, and the second groove 213 is used to form transistorized gate oxide and grid.
In the present embodiment, the first groove 211 is regular rectangular recess, therefore, can adopt single etching formula to carry out etching, simplifies etch process, and the first semiconductor column 212 between adjacent two the first grooves 211 is also regular rectangular shape naturally.
In the present embodiment, the forming process of the first groove 211 and the second groove 213 can be: exposed and developing process in the Semiconductor substrate 210 that scribbles photoresist by mask plate, form patterned photoresist, take patterned photoresist as mask, adopt chemical reaction ion etching Semiconductor substrate 210 to form again.The etching gas that described chemical reaction ion etching adopts can comprise Cl2, SF6 and HBr etc.
In the present embodiment, the mean breadth W3 of the first semiconductor column 212 is less than the mean breadth W4 of the first groove 211, and the mean breadth W4 of the first groove 211 is less than or equal to the thickness of the gate oxide of follow-up formation.The mean breadth W4 sum of the mean breadth W3 of the first semiconductor column 212 and the first groove 211 is greater than or equal to technique pitch, and the mean breadth W4 sum of the mean breadth W3 of the first semiconductor column 212 and the first groove 211 is less than or equal to 1 μ m.
The present embodiment forms the first groove 211 and the second groove 213 simultaneously, thereby saves processing step.And as shown in Figure 3, the overall width W5 of whole the first grooves 211 and whole the first semiconductor column 212 is the more than 5 times of the second groove 213 mean breadth W6.If adopt existing method to form field oxide, need to form width is 5 times of above grooves of the second groove 213 width, and then is oxidized, and the process time is very long especially.And in the present embodiment, the mean breadth W4 of each the first groove 211 is less, be easy to oxidation and fill, can significantly shorten oxidization time.
Please refer to Fig. 4, the first semiconductor column 212 shown in Fig. 3 is carried out to thermal oxidation technology and formed thermal oxide layer 221 until the first semiconductor column 212 is all oxidized, the field oxide 220(adjacent heat oxide layer 221 that thermal oxide layer 221 is interconnected to form full the first groove 211 of filling separates to show difference with dotted line).Meanwhile, the bottom to the second groove 213 and sidewall carry out thermal oxidation technology, until form gate oxide 230 at bottom and the sidewall of the second groove 213.Hence one can see that, and in the present embodiment, gate oxide 230 and field oxide 220 form simultaneously, further save processing step.
In the present embodiment, identical with previous embodiment, described thermal oxidation technology can be wet process oxidation technology, can be also the combination of wet process oxidation technology and dry oxidation.In the process of concrete oxidation, the first semiconductor column 212 is progressively oxidized in the middle of two side direction, and therefore, (silicon) material thickness of actual oxidation is only the half of the first semiconductor column 212 mean breadths.But, needing to guarantee after oxidation simultaneously, being partially filled that the oxidized layer of the first groove 211 grows is full, that is: make thermal oxide layer 221 be interconnected to form field oxide 220.
In the present embodiment, when forming after field oxide 220, the second groove 213 is not still filled, as shown in Figure 4, after thermal oxidation technology, the second groove 213 still for follow-up filled conductive material to form grid.
In the present embodiment, concrete, the mean breadth W4 of the first groove 211 can be 0.2 μ m, now, the mean breadth W3 of the first semiconductor column 2121 can be also 0.2 μ m, and the overall width of the final field oxide 220 forming is more than 5.0 μ m, the number of the first groove 211 is 5/ (0.2+0.2)=12.5, after rounding, known, the number of the present embodiment the first groove 211 can be more than 13.
In the present embodiment, the thickness range of the depth bounds of the first groove 211 and field oxide 220 can be with reference to previous embodiment corresponding contents.
In the present embodiment, final field oxide 220 thickness that form are greater than the degree of depth of the first groove 211, concrete, the concrete thickness of field oxide 220 be the degree of depth of the first groove 211 add again at least the first semiconductor column 212 mean breadths 1/2nd.
Due to the thickness different (thickness of field oxide is greater than the thickness of gate oxide conventionally) of common gate oxide and field oxide, both need to adopt different formation technique to form conventionally.But, in the formation method of the field oxide that the present embodiment provides, by form multiple the first grooves 211 and second groove 213 simultaneously, and between adjacent two the first grooves 211, form the first semiconductor column 212, therefore, only need bottom and the sidewall of simultaneous oxidation the first semiconductor column 212 and the second groove 213, just can form gate oxide 230 and field oxide 220 simultaneously, compared to previous embodiment, further save processing step, further cost-saving.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for field oxide, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form multiple the first grooves, between adjacent described the first groove, form the first semiconductor column;
Described the first semiconductor column is carried out to thermal oxidation technology and formed thermal oxide layer until described the first semiconductor column is all oxidized, described thermal oxide layer is interconnected to form the field oxide of filling full described the first groove.
2. the formation method of field oxide as claimed in claim 1, is characterized in that, the mean breadth sum of described the first groove and described the first semiconductor column is more than or equal to technique pitch, and is less than or equal to 1 μ m.
3. the formation method of field oxide as claimed in claim 1, is characterized in that, described formation method also comprises:
In forming described the first groove, in described Semiconductor substrate, form the second groove;
In forming described field oxide, form gate oxide at bottom and the sidewall of described the second groove.
4. the formation method of field oxide as claimed in claim 3, is characterized in that, the mean breadth of described the first groove is less than or equal to the thickness of described gate oxide.
5. the formation method of field oxide as claimed in claim 1, is characterized in that, the depth bounds of described the first groove is 0.5 μ m～2.5 μ m.
6. the formation method of field oxide as claimed in claim 3, is characterized in that, all the width sum of described the first groove and whole described the first semiconductor column is the more than 5 times of described the second groove width.
7. the formation method of field oxide as claimed in claim 1, is characterized in that, the temperature range that described thermal oxidation technology adopts comprises 800 ℃～1500 ℃, and the oxygen flow scope of employing comprises 0.1sccm～15sccm.
8. the formation method of field oxide as claimed in claim 1, is characterized in that, described the first groove is dovetail grooved.
9. the formation method of field oxide as claimed in claim 1, is characterized in that, described Semiconductor substrate is epitaxial loayer.
10. the formation method of field oxide as claimed in claim 1, is characterized in that, the material of described Semiconductor substrate is silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410081176.4A CN103824803A (en) | 2014-03-06 | 2014-03-06 | Field oxide layer forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410081176.4A CN103824803A (en) | 2014-03-06 | 2014-03-06 | Field oxide layer forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103824803A true CN103824803A (en) | 2014-05-28 |
Family
ID=50759792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410081176.4A Pending CN103824803A (en) | 2014-03-06 | 2014-03-06 | Field oxide layer forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103824803A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037142A (en) * | 2017-06-12 | 2018-12-18 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method that block is isolated |
| CN115385294A (en) * | 2022-10-08 | 2022-11-25 | 星中达半导体科技(山东)有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN117410347A (en) * | 2023-12-15 | 2024-01-16 | 无锡美偌科微电子有限公司 | Super junction power device with low terminal area and preparation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4139442A (en) * | 1977-09-13 | 1979-02-13 | International Business Machines Corporation | Reactive ion etching method for producing deep dielectric isolation in silicon |
| JPS59132142A (en) * | 1983-01-18 | 1984-07-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| CN102130010A (en) * | 2009-12-15 | 2011-07-20 | 万国半导体股份有限公司 | Method for filling large deep trench of semiconductor device with high-quality oxide |
-
2014
- 2014-03-06 CN CN201410081176.4A patent/CN103824803A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4139442A (en) * | 1977-09-13 | 1979-02-13 | International Business Machines Corporation | Reactive ion etching method for producing deep dielectric isolation in silicon |
| JPS59132142A (en) * | 1983-01-18 | 1984-07-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| CN102130010A (en) * | 2009-12-15 | 2011-07-20 | 万国半导体股份有限公司 | Method for filling large deep trench of semiconductor device with high-quality oxide |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037142A (en) * | 2017-06-12 | 2018-12-18 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method that block is isolated |
| CN115385294A (en) * | 2022-10-08 | 2022-11-25 | 星中达半导体科技(山东)有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN117410347A (en) * | 2023-12-15 | 2024-01-16 | 无锡美偌科微电子有限公司 | Super junction power device with low terminal area and preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103545216B (en) | Method for manufacturing groove type grid metal oxide semiconductor field effect transistor | |
| CN104916544B (en) | A kind of manufacture method of plough groove type point grid power device | |
| CN103943630A (en) | TFT substrate and manufacturing method thereof, and display panel | |
| CN105304481A (en) | Semiconductor element and manufacturing method therefor | |
| CN202434522U (en) | Termination region trench structure for schottky diode | |
| CN104103523A (en) | Method for manufacturing power device with U-shaped grooves | |
| CN104752218A (en) | Semiconductor device forming method | |
| CN107403721A (en) | Method for manufacturing power metal oxide semiconductor field effect transistor | |
| KR20150007520A (en) | Phase-change random access memory device and method of manufacturing the same | |
| CN103824803A (en) | Field oxide layer forming method | |
| CN104377245A (en) | Groove type MOS device and manufacturing method and terminal protecting structure thereof | |
| CN104617045A (en) | Manufacturing method of trench gate power device | |
| CN104517824B (en) | The manufacture method of groove type double-layer grid | |
| CN101656213B (en) | Trench gate metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN104103693A (en) | U-groove power device and manufacturing method thereof | |
| CN105789179A (en) | Active region contact windows of dynamic random access memory and manufacturing method of active region contact windows | |
| WO2023028825A1 (en) | Semiconductor device and preparation method therefor | |
| CN104779164B (en) | A kind of method for improving groove-shaped VDMOS grid oxide layers breakdown voltage | |
| CN206134689U (en) | Low pressure trench gate DMOS device of high integration | |
| CN102931195B (en) | Semiconductor element and manufacturing method thereof | |
| CN104701173A (en) | FinFET (fin field-effect transistor) device and forming method thereof | |
| CN204189799U (en) | A kind of groove type MOS device and terminal protection structure thereof | |
| CN103367261A (en) | Forming method of semiconductor structure | |
| TWI737855B (en) | Power transistor and manufacturing method thereof | |
| CN203850309U (en) | Trench-type Schottky chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140528 |
|
| RJ01 | Rejection of invention patent application after publication |