CN102931195B - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereof Download PDFInfo
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- CN102931195B CN102931195B CN201110234965.3A CN201110234965A CN102931195B CN 102931195 B CN102931195 B CN 102931195B CN 201110234965 A CN201110234965 A CN 201110234965A CN 102931195 B CN102931195 B CN 102931195B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 230000002262 irrigation Effects 0.000 claims description 56
- 238000003973 irrigation Methods 0.000 claims description 56
- 239000003989 dielectric material Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 239000007789 gas Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000010936 titanium Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a plurality of embedded-type bit lines, a plurality of bit-line contact windows, a plurality of dielectric layers and a plurality of embedded-type word lines. The embedded-type bit lines are arranged in substrates, are arranged in parallel and extend along the first direction. The bit-line contact windows are respectively arranged in the substrate on one side of the bit lines, and the embedded-type bit lines are respectively electrically connected with the substrate through the bit-line contact windows. The dielectric layers are respectively arranged on the embedded-type bit lines. The embedded-type word lines are arranged in the substrates and are positioned on the dielectric layers, are arranged in parallel and extend along the second direction different from the first direction, and a plurality of projections are arranged at the lower parts of the embedded-type word lines and are respectively positioned between two adjacent dielectric layers. By adopting the semiconductor element and the manufacturing method thereof, the on-state current can be improved, and the element efficiency can be further improved.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, and in particular to a kind of vertical channel transistor array and manufacture method thereof.
Background technology
Dynamic random access memory (dynamic random access memory, DRAM) belongs to a kind of volatile memory, and it is made up of multiple memory cell.Each memory cell is mainly made up of transistor AND gate capacitor manipulated by transistor, and each memory cell is electrically connected to each other by character line (word line, WL) and bit line (bit line, BL).
For improving the integration of dynamic random access memory (DRAM) to accelerate the service speed of element, and meeting the demand of consumer for miniaturized electronic device, the transistor channel section length in dynamic random access memory (DRAM) has the trend continuing to shorten.But, transistor can be made thus to suffer serious short-channel effect (short channel effect), and degradation problem under On current (on current).
Therefore, in order to overcome the problems referred to above, industry proposes the transistor arrangement transistor arrangement of horizontal direction being changed into vertical direction in recent years, for example, is formed in the deep trenches of substrate by vertical transistor structure.Thus, service speed and the integration of integrated circuit can be promoted, and can the problems such as short-channel effect be avoided.But vertical type bipolar transistor general at present controls to still have very large improvement space in structural design and raceway groove, the target of field institute active research for this reason.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of semiconductor element and manufacture method thereof, can On current be promoted, and improve element efficiency further.
The present invention proposes a kind of semiconductor element, and it comprises many embedded bit line, many contact window of bit lines, many dielectric layers and many flush type character lines.Embedded bit line is arranged in substrate, arranged in parallel and extend along first direction.Contact window of bit line is arranged in the substrate of the side of embedded bit line respectively, and embedded bit line is electrically connected substrate via contact window of bit line respectively.Dielectric layer is arranged in embedded bit line respectively.Flush type character line to be arranged in substrate and to be positioned on dielectric layer, flush type character line parallel arranges and extends along the second direction being different from first direction, wherein the bottom of each flush type character line has multiple protuberance, and each protuberance lays respectively between adjacent two dielectric layers.
The present invention separately proposes a kind of manufacture method of semiconductor element, and it comprises the following steps.In substrate, form multiple first irrigation canals and ditches, the first irrigation canals and ditches are arranged in parallel and extend along first direction.Many embedded bit line are formed in the bottom of the first irrigation canals and ditches.In the sidewall of the first irrigation canals and ditches, form many contact window of bit lines, contact window of bit line lays respectively at the side of embedded bit line to be electrically connected substrate.In substrate, form dielectric layer, dielectric layer covers embedded bit line and fills up the first irrigation canals and ditches.Remove part of substrate and dielectric layer, to form multiple second irrigation canals and ditches, the second irrigation canals and ditches arranged in parallel and along be different from first direction second direction extend, be wherein arranged in the upper surface of substrate of the second irrigation canals and ditches lower than the dielectric layer upper surface being arranged in the second irrigation canals and ditches.In the second irrigation canals and ditches, form many flush type character lines, the bottom of each flush type character line has multiple protuberance, and protuberance is formed in substrate.
Beneficial effect of the present invention is, based on above-mentioned, semiconductor element of the present invention and manufacture method thereof utilize be formed with multiple protuberance in the bottom of flush type character line and make grid groove can closer to or or even touch contact window of bit line, therefore, it is possible to improve element conductive electric current, and then improve element efficiency.In addition, the manufacturing approach craft of semiconductor element of the present invention is simple, and can be integrated in existing general technology.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 D is the semiconductor element fragmentary perspective schematic diagram from different perspectives according to one embodiment of the invention.
Fig. 2 A is the generalized section of A-A ' line segment in Figure 1B.
Fig. 2 B is the generalized section of B-B ' line segment in Figure 1B.
Fig. 2 C is the generalized section of C-C ' line segment in Figure 1B.
Fig. 2 D is the generalized section of D-D ' line segment in Figure 1B.
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate as according to the manufacturing process generalized section along A-A ' line segment in Figure 1B.
Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B illustrate as according to the manufacturing process generalized section along B-B ' line segment in Figure 1B.
Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C and Fig. 8 C illustrate as according to the manufacturing process generalized section along C-C ' line segment in Figure 1B.
Fig. 3 D, Fig. 4 D, Fig. 5 D, Fig. 6 D, Fig. 7 D and Fig. 8 D illustrate as according to the manufacturing process generalized section along D-D ' line segment in Figure 1B.
Fig. 9 A and Fig. 9 B illustrates the fragmentary perspective schematic diagram of different angles after formation second irrigation canals and ditches.
Wherein, description of reference numerals is as follows:
100,300: substrate
100a, 300a: semiconductor column
102,306: embedded bit line
102a, 108a, 306a, 320a: conductor layer
102b, 108b, 306b, 320b: barrier layer
104,308: contact window of bit line
104a, 308a: metal silicide layer
104b, 308b: doped polysilicon layer
104c, 308c: doped region
106,110,310,312: dielectric layer
107,314: lining
108,320: flush type character line
112,322: protuberance
114a, 324a: the first wire
114b, 324b: the second wire
114c, 324c: connecting portion
302,316: patterned mask layer
304: the first irrigation canals and ditches
312a: the first dielectric material
312b: the second dielectric material
312c: the three dielectric material
318: the second irrigation canals and ditches
318a: groove
D1: first direction
D2: second direction
Embodiment
Semiconductor element proposed by the invention is such as a kind of transistor array with vertical-channel, and can be used for dynamic random access memory.Hereafter describe embodiments of the invention in detail by the mode of perspective view collocation profile.
Figure 1A to Fig. 1 D is the semiconductor element fragmentary perspective schematic diagram from different perspectives according to one embodiment of the invention.Fig. 2 A is the generalized section of A-A ' line segment in Figure 1B.Fig. 2 B is the generalized section of B-B ' line segment in Figure 1B.Fig. 2 C is the generalized section of C-C ' line segment in Figure 1B.Fig. 2 D is the generalized section of D-D ' line segment in Figure 1B.It is noted that, for simplifying accompanying drawing, in Figure 1A to Fig. 1 D, only showing the main members such as embedded bit line, contact window of bit line, flush type character line, part of dielectric layer.
Please refer to Figure 1A to Fig. 1 D and Fig. 2 A to Fig. 2 D, the semiconductor element be arranged in substrate 100 comprises many embedded bit line 102, many contact window of bit lines 104, many dielectric layers 106 and many flush type character lines 108.Substrate 100 is such as silicon base or other semiconductor bases.In one embodiment, the top of substrate 100 can have multiple semiconductor column 100a, and wherein semiconductor column 100a is such as separated from one another and is arranged in array, using the active region as vertical-channel transistors.
Embedded bit line 102 is arranged in substrate 100, and embedded bit line 102 is arranged in parallel and extend along first direction D1.In one embodiment, between embedded bit line 102 and substrate 100, also comprise one dielectric layer 110, with isolated part embedded bit line 102 and substrate 100.Specifically, embedded bit line 102 comprises conductor layer 102a and barrier layer 102b, and wherein barrier layer 102b is arranged between conductor layer 102a and dielectric layer 110.The material of conductor layer 102a comprises metal material, such as tungsten, copper, aluminium, albronze etc.The material of barrier layer 102b is such as titanium nitride (TiN) or titanium (Ti).The material of dielectric layer 110 is such as silica.
Contact window of bit line 104 is arranged in the substrate 100 of the side of embedded bit line 102 respectively.In one embodiment, contact window of bit line 104 comprises metal silicide layer 104a, doped polysilicon layer 104b and doped region 104c, wherein metal silicide layer 104a is configured between doped polysilicon layer 104b and barrier layer 102b, and doped polysilicon layer 104b is configured between metal silicide layer 104a and doped region 104c.Metal silicide layer 104a directly contacts with barrier layer 102b, thus makes embedded bit line 102 can be electrically connected substrate 100 via contact window of bit line 104 respectively.The material of metal silicide layer 104a is such as titanium silicide.Doped polysilicon layer 104b and doped region 104c is such as doped with admixtures such as arsenic (As) or phosphorus (P).
Dielectric layer 106 is arranged in embedded bit line 102 respectively, contacts with each other in order to prevent embedded bit line 102 and flush type character line 108.The material of dielectric layer 106 is such as silica or silicon nitride.In one embodiment, around dielectric layer 106, lining 107 is also comprised.Lining 107 is such as at least between dielectric layer 106 and substrate 100 and between dielectric layer 106 and embedded bit line 102.The material of lining 107 is such as silicon nitride.
Flush type character line 108 to be arranged in substrate 100 and to be positioned on dielectric layer 106.Flush type character line 108 arranged in parallel and along be different from first direction D1 second direction D2 extend.Flush type character line 108 is such as be made up of conductor layer 108a and barrier layer 108b.The material of conductor layer 108a comprises metal material, such as tungsten, copper, aluminium or albronze etc., and the material of barrier layer 108b is such as titanium nitride (TiN) or titanium (Ti).
The bottom of each flush type character line 108 has multiple protuberance 112, and each protuberance 112 lays respectively between adjacent two dielectric layers 106.In one embodiment, flush type character line 108 and contact window of bit line 104 are the closer to better, and wherein the protuberance 112 of flush type character line 108 is such as the doped region 104c directly touching contact window of bit line 104.For example, the bottom profile of flush type character line 108 can have difference of height.Be positioned at flush type character line 108 and embedded bit line 102 staggered place, can be provided with dielectric layer 106 between flush type character line 108 and embedded bit line 102 and make both mutually isolated, therefore flush type character line 108 is higher in bottom profile herein.On the other hand, locate above between adjacent embedded bit line 102, the protuberance 112 of flush type character line 108 is such as directly contact with the contact window of bit line 104 being positioned at embedded bit line 102 side, and therefore flush type character line 108 is lower in bottom profile herein.
In addition, every bar flush type character line 108 is such as be made up of a first wire 114a, a second wire 114b and multiple connecting portion 114c.First wire 114a and the second wire 114b extends along second direction D2 respectively, and connecting portion 114c to lay respectively on dielectric layer 106 and connects the first adjacent wire 114a and the second wire 114b.Specifically, the adjacent first wire 114a connected by connecting portion 114c and the second wire 114b can connect same row semiconductor column 100a in a second direction d 2, and adheres to the adjacent first wire 114a of two different flush type character lines 108 separately and the second wire 114b is separated from one another is not in contact with each other.In each flush type character line 108, the first wire 114a connects a side of the semiconductor column 100a of same row on second direction D2, and the second wire 114b correspondence connects the relative another side of the semiconductor column 100a of same row on second direction D2.Hold above-mentioned, each flush type character line 108 has multiple protuberance 112 between adjacent two dielectric layers 106, and protuberance 112 like this is such as be positioned at the bottom of the first wire 114a and the bottom of the second wire 114b respectively accordingly.
Described hereinly be, double gate (double gate) structure of fin-shaped (fin) is formed because every bar flush type character line 108 adopts the both sides of the coated semiconductor column 100a of same row in a second direction d 2 of the first wire 114a and the second wire 114b, thus the electric field making the two side as the same row semiconductor column 100a of active region all can respond to grid to cause, and the On current of the element that is increased (on current), and reduce the problem of leakage current in raceway groove.In addition, on cross section view, similar H-shaped grid (as shown in Figure 2 A) is formed by being provided with multiple protuberance 112 in the bottom of flush type character line 108, therefore make grid groove can closer to or or even touch the doped region 104c of contact window of bit line 104, can contribute to more improving element conductive electric current, and then improve element efficiency while effectively isolating embedded bit line 102 and flush type character line 108.
Next the generalized section utilized along A-A ', the B-B ' of Figure 1B, C-C ', D-D ' line segment is illustrated the manufacturing process forming the semiconductor element shown in above-mentioned Figure 1A to Fig. 1 D, Fig. 2 A to Fig. 2 D.It is noted that, the manufacturing process of the semiconductor element of the following stated is mainly used for illustrating the formation method of the flush type character line with protuberance, implement according to this to enable those skilled in the art, but and be not used to limit scope of the present invention, as for other components as the generation type of embedded bit line, contact window of bit line, dielectric layer, lining etc. and order, all according to the fabrication techniques known to the technical staff in the technical field, and can be not limited to described in following embodiment.
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate as according to the manufacturing process generalized section along A-A ' line segment in Figure 1B.Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B illustrate as according to the manufacturing process generalized section along B-B ' line segment in Figure 1B.Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C and Fig. 8 C illustrate as according to the manufacturing process generalized section along C-C ' line segment in Figure 1B.Fig. 3 D, Fig. 4 D, Fig. 5 D, Fig. 6 D, Fig. 7 D and Fig. 8 D illustrate as according to the manufacturing process generalized section along D-D ' line segment in Figure 1B.
Please refer to Fig. 3 A to Fig. 3 D, provide substrate 300, it is such as silicon base or other semiconductor bases.Then, in substrate 300, patterned mask layer 302 is formed.The material of patterned mask layer 302 is such as silicon nitride, and its formation method is such as chemical vapour deposition technique.Then, with patterned mask layer 302 for mask removes part of substrate 300, to form multiple first irrigation canals and ditches 304 in substrate 300, wherein multiple first irrigation canals and ditches 304 are arranged in parallel and extend along first direction D1.
Please refer to Fig. 4 A to Fig. 4 D, many embedded bit line 306 are formed in the bottom of the first irrigation canals and ditches 304, and many contact window of bit lines 308 are formed in the sidewall of the first irrigation canals and ditches 304, contact window of bit line 308 lays respectively at the side of embedded bit line 306 to be electrically connected substrate 300.Embedded bit line 306 comprises conductor layer 306a and barrier layer 306b, and wherein barrier layer 306b is arranged between conductor layer 306a and dielectric layer 310.In one embodiment, contact window of bit line 308 comprises metal silicide layer 308a, doped polysilicon layer 308b and doped region 308c, and wherein doped polysilicon layer 308b is configured between metal silicide layer 308a and doped region 308c.
Specifically, contact window of bit line 308 and embedded bit line 306 can utilize following step and be formed, but the present invention is not limited to this.First, on the lower sides and bottom of the first irrigation canals and ditches 304, one dielectric layer 310 is formed.The material of dielectric layer 310 is such as silica, and its formation method is such as thermal oxidation method.Then, in dielectric layer 310 expose the doped polysilicon layer 308b wherein on one side sidewall formed doped with arsenic (As) or phosphorus (P) of the first irrigation canals and ditches 304 bottom, utilize thermal process to make the arsenic in doped polysilicon layer 308b (As) or phosphorus (P) dopant diffusion in the substrate 100 contacted with doped polysilicon layer 308b thereupon, in the wherein sidewall of the first irrigation canals and ditches 304 bottom, thus form the doped region 308c of contact window of bit line 308.Afterwards, on dielectric layer 310, form barrier layer 306b to compliance, barrier layer 306b covers on doped polysilicon layer 308b.Barrier layer 306b is such as titanium nitride (TiN) or titanium (Ti), and titanium (Ti) meeting wherein in barrier layer 306b and doped polysilicon layer 308b produce and react and form metal silicide 308a.Then, insert conductor layer 306a in the bottom of the first irrigation canals and ditches 304, wherein conductor layer 306a covers barrier layer 306b, thus completes the structure of contact window of bit line 308 and embedded bit line 306.The material of conductor layer 306a comprises metal material, such as tungsten, copper, aluminium or albronze etc.
Please refer to Fig. 5 A to Fig. 5 D, form dielectric layer 312 in substrate 300, dielectric layer 312 covers embedded bit line 306 and fills up the first irrigation canals and ditches 304.In one embodiment, dielectric layer 312 is such as multilayer dielectric layer, it at least comprises the first dielectric material 312a and the second dielectric material 312b with different etching selectivity, and the first dielectric material 312a is arranged between embedded bit line 306 and the second dielectric material 312b.First dielectric material 312a is such as the silica (HDP oxide) utilizing high-density plasma to be formed, and the second dielectric material 312b is such as the silica (SOD oxide) utilizing spin-coating method to be formed.In addition, dielectric layer 312 also can comprise the 3rd dielectric material 312c from the second dielectric material 312b with different etching selectivity.3rd dielectric material 312c covers in the second dielectric material 312b and patterned mask layer 302, and the second dielectric material 312b is sandwiched between the first dielectric material 312a and the 3rd dielectric material 312c.The 3rd dielectric material 312c from the second dielectric material 312b with different etching selectivity can be the material being same as the first dielectric material 312a, as utilize high-density plasma the silica (HDP oxide) that formed.
In one embodiment, before formation dielectric layer 312, can also optionally above embedded bit line 306 and the first irrigation canals and ditches 304 sidewall formed lining 314, lining 314 be such as compliance be formed between dielectric layer 312 and substrate 300 and be formed between dielectric layer 312 and embedded bit line 306.The material of lining 314 is such as silicon nitride, and its formation method is such as chemical vapour deposition technique.
Please refer to Fig. 6 A to Fig. 6 D, in substrate 300, form another pattern layers mask layer 316.The material of patterned mask layer 316 is such as carborundum, and its formation method is such as chemical vapour deposition technique.Then, with patterned mask layer 316 for mask removes part of substrate 300, dielectric layer 312, lining 314 and patterned mask layer 302, to form multiple second irrigation canals and ditches 318.Multiple second irrigation canals and ditches 318 are parallel in substrate 300, and extend along the second direction D2 being different from first direction D1.Second irrigation canals and ditches 318 are such as the tops being positioned at embedded bit line 306, and with embedded bit line 306 at a distance of a distance.In one embodiment, the second irrigation canals and ditches 318 and the common semiconductor column 300a upper part of substrate 300 being slit into multiple separation and arrayed of the first irrigation canals and ditches 304.
Special instruction, Fig. 9 A and Fig. 9 B illustrates the fragmentary perspective schematic diagram of different angles after formation second irrigation canals and ditches, and for simplifying accompanying drawing to clearly demonstrate, eliminates patterned mask layer 316 in Fig. 9 A and Fig. 9 B.As shown in Fig. 9 A and Fig. 9 B, in the second irrigation canals and ditches 318, the upper surface of the substrate 300 be exposed out lower than the upper surface of dielectric layer 312, thus can form multiple groove 318a in the bottom of each second irrigation canals and ditches 318.Specifically, multiple second irrigation canals and ditches 318 are such as carry out the dry etch process of multi-step with patterned mask layer 316 for mask and formed.
In one embodiment, after formation patterned mask layer 316, carry out the first etching step remove partially patterned mask layer 302, dielectric layer 312 and lining 314 and expose part of substrate 300, then carry out the second etching step and remove the part of substrate 300 that exposes until the required degree of depth, carry out the 3rd etching step afterwards and remove the part of dielectric layer 312 exposed, and complete the making of the second irrigation canals and ditches 318.Because substrate 300 has different etching selectivities from dielectric layer 312, therefore the second etching step only can remove a small amount of dielectric layer 312, and the 3rd etching step only can remove a small amount of substrate 300.Thus, namely by controlling the process conditions of the second etching step and the 3rd etching step, the substrate 300 and the dielectric layer 312 that make to be positioned at the second irrigation canals and ditches 318 have different upper level.
In practice, above-mentioned second etching step that carries out removes the part of substrate 300 exposed and can use CHF
3, HBr, Cl
2and SF
6as reacting gas, wherein CHF
3gas flow be such as the gas flow of 90sccm to 120sccm, HBr be such as 20sccm to 45sccm, Cl
2gas flow be such as 20sccm to 45sccm, SF
6gas flow be such as 8sccm to 13sccm.Carrying out the second etching step, to remove the part of substrate 300 exposed be such as carry out under the pressure of about 10mTorr to 30mTorr, and be such as apply about 1000W to 1500W and apply rf bias to be about 60W to 90W at electric pole plate in order to produce radio frequency (radio frequency, the RF) power of plasma in etching step.Carrying out the time that the second etching step removes the part of substrate 300 exposed is such as 20 seconds to 30 seconds.
On the other hand, above-mentioned the 3rd etching step that carries out removes the part of dielectric layer 312 exposed and can use CHF
3as reacting gas, wherein CHF
3gas flow be such as 300sccm to 500sccm.It is such as carry out under the pressure of about 10mTorr to 30mTorr that 3rd etching step removes the part of dielectric layer 312 exposed, and is such as apply about 200W to 500W and apply rf bias to be about 550W to 800W at electric pole plate in order to produce the radio-frequency power supply power of plasma in etching step.Carrying out the time that the 3rd etching step removes the part of dielectric layer 312 exposed is such as 35 seconds to 45 seconds.In addition, in the second etching step and the 3rd etching step, also can add further when passing into reacting gas if the inert gases such as argon gas (Ar) or helium (He) are as the use of diluent gas and carrier gas.
It is worth mentioning that, although be first carry out the second etching step to remove part of substrate 300 and carry out the 3rd etching step again and remove part of dielectric layer 312 and make the second irrigation canals and ditches 318 that bottom has multiple groove 318a for example and be described in the above-described embodiments, the present invention is not limited to this.In another embodiment, after exposing part of substrate 300 carrying out the first etching step to remove partially patterned mask layer 302, dielectric layer 312 and lining 314, also can be first carry out the 3rd etching step to remove the part of dielectric layer 312 that exposes until the required degree of depth, just carry out the second etching step afterwards and remove the part of substrate 300 that exposes to form the second irrigation canals and ditches 318, in these those skilled in the art when knowing that it changes according to previous embodiment, therefore repeat no more in this.
Please refer to Fig. 7 A to Fig. 7 D, remove the second dielectric material 312b, thus between the first dielectric material 312a and the 3rd dielectric material 312c, form opening, to make can be interconnected between the second adjacent irrigation canals and ditches 318.The method removing the second dielectric material 312b is such as carry out wet etching, and the hydrofluoric acid (dilute hydrofluoric acid, DHF) of dilution can be utilized as etching solution.Afterwards, form conductor layer 320a in substrate, conductor layer 320a to insert in the second irrigation canals and ditches 318 and is formed in the opening (former second dielectric material 312b place) between the first dielectric material 312a and the 3rd dielectric material 312c.Bottom due to the second irrigation canals and ditches 318 has multiple groove 318a, and therefore conductor layer 320a can insert in groove 318a, and forms multiple protuberance 322 in the bottom of conductor layer 320a.Protuberance 322 is such as that therefore protuberance 322 is preferably the doped region 308c directly touching contact window of bit line 308 with contact window of bit line 308 the closer to better.Before formation conductor layer 320a, also optionally between conductor layer 320a and substrate 300, between conductor layer 320a and dielectric material, form barrier layer 320b.Thus, conductor layer 320a and barrier layer 320b can be used as the material that subsequent step makes a reservation for the character line formed.
Please refer to Fig. 8 A to Fig. 8 D, patterning conductor layer 320a and barrier layer 320b, to form a first wire 324a and the second wire 324b extended along second direction D2 in each second irrigation canals and ditches 318 respectively, the conductor layer 320a in the opening (former second dielectric material 312b place) wherein between the first dielectric material 312a and the 3rd dielectric material 312c and barrier layer 320b then forms multiple connecting portion 324c.Multiple connecting portion 324c connects the first wire 324a and the second wire 324b that lay respectively in adjacent two second irrigation canals and ditches 318, thus forms a flush type character line 320, and completes the structure of the semiconductor element as shown in Figure 1A to Fig. 1 D.After formation comprises the semiconductor element of the components such as embedded bit line 306, contact window of bit line 308, flush type character line 320, also can continue to form capacitor above it and the making completing memory, know those skilled in the art when its application known and change, therefore repeat no more in this.
Hold above-mentioned, the adjacent first wire 324a connected by multiple connecting portion 324c and the second wire 324b can connect same row semiconductor column 300a in a second direction d 2, and adheres to the adjacent first wire 324a of two different flush type character lines 320 separately and the second wire 324b is separated from one another is not in contact with each other.The first wire 324a in every bar flush type character line 320 and the second wire 324b can coated same row in a second direction d 2 semiconductor column 300a relative both sides and form the dual gate structures of fin-shaped, can contribute to making the two side of same row semiconductor column 300a all can sense electric field, and increase the On current of element and reduce the problem of leakage current in raceway groove.Moreover, protuberance 322 due to conductor layer 320a can be inserted in the groove 318a bottom the second irrigation canals and ditches 318, therefore the first wire 324a in every bar flush type character line 320 and the second wire 324b by protuberance 322 closer to or even touch the doped region 308c of contact window of bit line 308, therefore, it is possible to improve element conductive electric current, and then improve element efficiency.
In sum, semiconductor element of the present invention and manufacture method thereof at least have following advantages:
1. the flush type character line of the semiconductor element of above-described embodiment has protuberance, can contribute to enabling grid groove closer to the doped region even directly touching contact window of bit line, therefore, it is possible to increase the On current of element, and then improve element efficiency while effectively isolating embedded bit line and flush type character line.
2. the manufacture method of the semiconductor element of above-described embodiment utilizes substrate and dielectric layer to have different etching selectivities, and only need can form protuberance in the bottom of flush type character line through the change of etch process conditions, therefore technique is simple and can be integrated in existing technique, and significantly can promote the element efficiency of follow-up formation.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (9)
1. a semiconductor element, comprising:
Many embedded bit line, are arranged in a substrate, described many embedded bit line arranged in parallel and along one first direction extend;
Many contact window of bit lines, are arranged in this substrate of the side of described many embedded bit line respectively, and described many embedded bit line are electrically connected this substrate via described many contact window of bit lines respectively;
Many dielectric layers, are arranged in described many embedded bit line respectively; And
Many flush type character lines, to be arranged in this substrate and to be positioned on this dielectric layer, described many flush type character line parallels arrange and extend along the second direction being different from this first direction, wherein the bottom of each described many flush type character lines has multiple protuberance, each described multiple protuberance lays respectively between adjacent two dielectric layers, and wherein said many flush type character lines directly contact described many contact window of bit lines.
2. semiconductor element as claimed in claim 1, it is characterized in that, each described flush type character line comprises:
One first wire and one second wire, extend along this second direction respectively; And
Multiple connecting portion, to be positioned on described many dielectric layers and to connect this adjacent first wire and this second wire.
3. semiconductor element as claimed in claim 1, it is characterized in that, each described flush type character line comprises a barrier layer and a conductor layer.
4. semiconductor element as claimed in claim 1, it is characterized in that, described contact window of bit line comprises doped region.
5. a manufacture method for semiconductor element, comprising:
In a substrate, form multiple first irrigation canals and ditches, described multiple first irrigation canals and ditches arranged in parallel and along one first direction extend;
Many embedded bit line are formed in the bottom of described multiple first irrigation canals and ditches;
In the sidewall of described multiple first irrigation canals and ditches, form many contact window of bit lines, described many contact window of bit lines lay respectively at the side of described many embedded bit line to be electrically connected this substrate;
In this substrate, form a dielectric layer, this dielectric layer covers described many embedded bit line and fills up described multiple first irrigation canals and ditches;
Remove this substrate of part and this dielectric layer, to form multiple second irrigation canals and ditches, described multiple second irrigation canals and ditches arranged in parallel and along be different from this first direction one second direction extend, be wherein arranged in this upper surface of substrate of described multiple second irrigation canals and ditches lower than this dielectric layer upper surface being arranged in described multiple second irrigation canals and ditches; And
In described multiple second irrigation canals and ditches, form many flush type character lines, the bottom of each described many flush type character lines has multiple protuberance, and described multiple protuberance is formed in this substrate.
6. the manufacture method of semiconductor element as claimed in claim 5, it is characterized in that, described many flush type character lines directly contact described many contact window of bit lines.
7. the manufacture method of semiconductor element as claimed in claim 5, it is characterized in that, this dielectric layer between adjacent described multiple second irrigation canals and ditches is multilayer dielectric layer, it comprises one first dielectric material and one second dielectric material with different etching selectivity, and this first dielectric material is arranged between described many embedded bit line and this second dielectric material.
8. the manufacture method of semiconductor element as claimed in claim 7, it is characterized in that, the manufacture method of described many flush type character lines comprises:
Remove this second dielectric material;
In this substrate, form a conductor layer, this conductor layer to be inserted in described multiple second irrigation canals and ditches and is formed on this first dielectric material; And
This conductor layer of patterning, to form one first wire and one second wire that extend along this second direction in each described multiple second irrigation canals and ditches respectively, this conductor layer be wherein positioned on this first dielectric material forms multiple connecting portion, lays respectively at this first wire in adjacent two second irrigation canals and ditches and this second wire to connect.
9. the manufacture method of semiconductor element as claimed in claim 5, it is characterized in that, described contact window of bit line comprises doped region.
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