CN103794556A - Array substrate, manufacturing method thereof and liquid crystal display device - Google Patents
Array substrate, manufacturing method thereof and liquid crystal display device Download PDFInfo
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- CN103794556A CN103794556A CN201410031062.9A CN201410031062A CN103794556A CN 103794556 A CN103794556 A CN 103794556A CN 201410031062 A CN201410031062 A CN 201410031062A CN 103794556 A CN103794556 A CN 103794556A
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- storage capacitance
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- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
The invention discloses an array substrate, a manufacturing method thereof and a liquid crystal display device, and relates to the technical field of liquid crystal display. Storage capacitance can be increased, and therefore the display effect of the display device is improved. The manufacturing method of the array substrate includes the steps that a TFT, a grid line and a data line are formed on the substrate; a plate-shaped electrode is formed on the substrate with the TFT, the grid line and the data line; an insulation layer is formed on the substrate with the plate-shaped electrode, and etching is performed on a storage capacitance area on the insulation layer so as to enable the thickness of the part, at the storage capacitance area, of the insulation layer to be smaller than the thickness of the part, outside the storage capacitance area, of the insulation layer; a slit electrode is formed on the substrate with the insulation layer, and the overlapping area of the slit electrode and the plate-shaped electrode is the storage capacitance area.
Description
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to a kind of array base palte and preparation method thereof and liquid crystal indicator.
Background technology
Senior super dimension field switch (Advanced-Super Dimensional Switching, being called for short ADS) pattern is the wide visual angle of plane electric fields core technology, be specially the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer and form multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal operating efficiency.ADS pattern is widely used in liquid crystal indicator, as depicted in figs. 1 and 2, wherein between plate electrode 1 and the overlapping region of gap electrode 2, form storage capacitance Cst, along with the resolution of liquid crystal indicator is more and more higher, be limited by pixel size, it is very large that storage capacitance cannot be done, and causes some display effect poor.
Summary of the invention
The invention provides a kind of array base palte and preparation method thereof and liquid crystal indicator, can increase storage capacitance, thereby improve the display effect of display unit.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
On the one hand, provide a kind of manufacture method of array base palte, comprising:
On substrate, form TFT, grid line and data wire;
On the substrate that comprises described TFT, grid line and data wire, form plate electrode;
On the substrate that comprises described plate electrode, form insulating barrier, etching is carried out in the storage capacitance region on described insulating barrier, make the thickness of insulating layer in described storage capacitance region be less than the thickness of insulating layer outside described storage capacitance region;
On the substrate that comprises described insulating barrier, form gap electrode, the overlapping region of described gap electrode and described plate electrode is described storage capacitance region.
Particularly, describedly on the substrate that comprises described plate electrode, form insulating barrier, etching is carried out in storage capacitance region on described insulating barrier, and the process that makes the thickness of insulating layer in described storage capacitance region be less than the thickness of insulating layer outside described storage capacitance region comprises:
Depositing insulating layer material on the substrate that comprises described plate electrode;
On the substrate that comprises described insulating layer material, deposit photoresist;
Photoresist to insulating barrier via area exposes completely, and the photoresist in described storage capacitance region is carried out to halftone exposure;
Photoresist is developed, the photoresist of described insulating barrier via area is removed completely, make the photoresist attenuation in described storage capacitance region;
The insulating layer material of described insulating barrier via area is carried out to etching, form insulating barrier via hole;
Described photoresist is carried out to ashing, the photoresist in described storage capacitance region is removed completely, the photoresist attenuation outside described storage capacitance region;
Insulating layer material to described storage capacitance region carries out etching, makes the thickness of insulating layer in described storage capacitance region be less than the thickness of insulating layer outside described storage capacitance region;
Remove remaining photoresist.
Alternatively, described plate electrode is pixel electrode, and described gap electrode is public electrode.
Alternatively, described plate electrode is public electrode, and described gap electrode is pixel electrode.
On the other hand, provide a kind of array base palte, comprise plate electrode, gap electrode and the insulating barrier between described plate electrode and gap electrode, it is characterized in that,
The thickness of insulating layer in storage capacitance region is less than the thickness of insulating layer outside described storage capacitance region, and the overlapping region of described gap electrode and described plate electrode is described storage capacitance region.
Alternatively, described plate electrode is pixel electrode, and described gap electrode is public electrode.
Alternatively, described plate electrode is public electrode, and described gap electrode is pixel electrode.
On the other hand, provide a kind of liquid crystal indicator, comprise above-mentioned array base palte.
Array base palte provided by the invention and preparation method thereof and liquid crystal indicator, by making the thickness attenuation of insulating barrier in storage capacitance region, reduce the distance between plate electrode and gap electrode, therefore increased storage capacitance, thereby improved the display effect of display unit.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of a kind of array base palte in prior art;
Fig. 2 be in Fig. 1 array base palte BB ' to sectional view;
Fig. 3 is the flow chart of a kind of array substrate manufacturing method in the embodiment of the present invention;
Fig. 4 is the structural representation that forms array base palte after plate electrode in the manufacture method of Fig. 3;
Fig. 5 be in Fig. 4 array base palte CC ' to sectional view;
Fig. 6 is the sectional view that in the manufacture method of Fig. 3, storage capacitance region on insulating barrier is carried out array base palte after etching;
Fig. 7 is the structural representation that forms array base palte after gap electrode in the manufacture method of Fig. 3;
Fig. 8 be in Fig. 7 array base palte CC ' to sectional view;
Fig. 9 is the particular flow sheet of a kind of manufacturing process of step 103 in the manufacture method of Fig. 3;
Figure 10 is the sectional view that deposits array base palte after photoresist in the manufacturing process of Fig. 9;
Figure 11 is the sectional view of array base palte after developing in the manufacturing process of Fig. 9;
Figure 12 is the sectional view of array base palte after ashing in the manufacturing process of Fig. 9;
Figure 13 is the sectional view that in the manufacturing process of Fig. 9, the insulating barrier in storage capacitance region is carried out array base palte after etching.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 3, the embodiment of the present invention provides a kind of manufacture method of array base palte, comprising:
Step 101, on substrate, form TFT, grid line and data wire;
Step 102, as shown in Figure 4 and Figure 5 forms plate electrode 1 on the substrate that comprises above-mentioned TFT, grid line and data wire;
Step 103, as shown in Figure 6 forms insulating barrier 3 on the substrate that comprises plate electrode 1, and the storage capacitance region A on insulating barrier 3 is carried out to etching, makes the thickness of insulating layer of storage capacitance region A be less than the thickness of insulating layer outside the A of storage capacitance region;
Step 104, as shown in Figure 7 and Figure 8 forms gap electrode 2 on the substrate that comprises insulating barrier 3, and gap electrode 2 is storage capacitance region A with the overlapping region of plate electrode 1.
The manufacture method of array base palte in the present embodiment, by making the thickness attenuation of insulating barrier in storage capacitance region, has reduced the distance between plate electrode and gap electrode, has therefore increased storage capacitance, thereby improves the display effect of display unit.
Further, as shown in Figure 9, above-mentioned steps 103, on the substrate that comprises plate electrode 1, form insulating barrier 3, the storage capacitance region A on insulating barrier 3 is carried out to etching, the process that makes the thickness of insulating layer of storage capacitance region A be less than the thickness of insulating layer outside the A of storage capacitance region comprises:
Particularly, plate electrode 1 is pixel electrode, and gap electrode 2 is public electrode; Or plate electrode 1 is public electrode, gap electrode 2 is pixel electrode.
Above-mentioned insulating barrier via hole is communicated with lower floor line related for the gap electrode that makes upper strata, in the process of making insulating barrier via hole, coordinate exposure and cineration technics to form the photoetching agent pattern in storage capacitance region by halftone exposure, realize the insulating barrier in etching storage capacitance region in making insulating barrier via hole, without the insulating barrier in the composition technique etching storage capacitance region by independent.
The manufacture method of array base palte in the present embodiment, by making the thickness attenuation of insulating barrier in storage capacitance region, has reduced the distance between plate electrode and gap electrode, has therefore increased storage capacitance, thereby improves the display effect of display unit.And the insulating barrier in etching storage capacitance region, without the insulating barrier in the composition technique etching storage capacitance region by independent, has simplified processing step in making insulating barrier via hole.
As shown in Figure 7 and Figure 8, the embodiment of the present invention also provides a kind of array base palte, comprises plate electrode 1, gap electrode 2 and the insulating barrier 3 between plate electrode 1 and gap electrode 2,
Insulating barrier 3 thickness of storage capacitance region A are less than insulating barrier 3 thickness outside the A of storage capacitance region, and gap electrode 2 is storage capacitance region A with the overlapping region of plate electrode 1.
Particularly, plate electrode 1 is pixel electrode, and gap electrode 2 is public electrode; Or plate electrode 1 is public electrode, gap electrode 2 is pixel electrode.
Array base palte in the present embodiment, by making the thickness attenuation of insulating barrier in storage capacitance region, has reduced the distance between plate electrode and gap electrode, has therefore increased storage capacitance, thereby improves the display effect of display unit.
The embodiment of the present invention also provides a kind of liquid crystal indicator, comprises above-mentioned array base palte.
The concrete structure of this array base palte is same as the previously described embodiments, does not repeat them here.
This liquid crystal indicator is specifically as follows: liquid crystal panel, LCD TV, liquid crystal display, Electronic Paper, DPF, mobile phone etc.
Liquid crystal indicator in the present embodiment, by making the thickness attenuation of insulating barrier in storage capacitance region, has reduced the distance between plate electrode and gap electrode, has therefore increased storage capacitance, thereby improves the display effect of display unit.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (8)
1. a manufacture method for array base palte, is characterized in that, comprising:
On substrate, form TFT, grid line and data wire;
On the substrate that comprises described TFT, grid line and data wire, form plate electrode;
On the substrate that comprises described plate electrode, form insulating barrier, etching is carried out in the storage capacitance region on described insulating barrier, make the thickness of insulating layer in described storage capacitance region be less than the thickness of insulating layer outside described storage capacitance region;
On the substrate that comprises described insulating barrier, form gap electrode, the overlapping region of described gap electrode and described plate electrode is described storage capacitance region.
2. the manufacture method of array base palte according to claim 1, is characterized in that,
Describedly on the substrate that comprises described plate electrode, form insulating barrier, etching is carried out in the storage capacitance region on described insulating barrier, the process that makes the thickness of insulating layer in described storage capacitance region be less than the thickness of insulating layer outside described storage capacitance region comprises:
Depositing insulating layer material on the substrate that comprises described plate electrode;
On the substrate that comprises described insulating layer material, deposit photoresist;
Photoresist to insulating barrier via area exposes completely, and the photoresist in described storage capacitance region is carried out to halftone exposure;
Photoresist is developed, the photoresist of described insulating barrier via area is removed completely, make the photoresist attenuation in described storage capacitance region;
The insulating layer material of described insulating barrier via area is carried out to etching, form insulating barrier via hole;
Described photoresist is carried out to ashing, the photoresist in described storage capacitance region is removed completely, the photoresist attenuation outside described storage capacitance region;
Insulating layer material to described storage capacitance region carries out etching, makes the thickness of insulating layer in described storage capacitance region be less than the thickness of insulating layer outside described storage capacitance region;
Remove remaining photoresist.
3. the manufacture method of array base palte according to claim 1 and 2, is characterized in that,
Described plate electrode is pixel electrode, and described gap electrode is public electrode.
4. the manufacture method of array base palte according to claim 1 and 2, is characterized in that,
Described plate electrode is public electrode, and described gap electrode is pixel electrode.
5. an array base palte, comprises plate electrode, gap electrode and the insulating barrier between described plate electrode and gap electrode, it is characterized in that,
The thickness of insulating layer in storage capacitance region is less than the thickness of insulating layer outside described storage capacitance region, and the overlapping region of described gap electrode and described plate electrode is described storage capacitance region.
6. array base palte according to claim 5, is characterized in that,
Described plate electrode is pixel electrode, and described gap electrode is public electrode.
7. array base palte according to claim 5, is characterized in that,
Described plate electrode is public electrode, and described gap electrode is pixel electrode.
8. a liquid crystal indicator, is characterized in that, comprises the array base palte as described in any one in claim 5 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410031062.9A CN103794556A (en) | 2014-01-22 | 2014-01-22 | Array substrate, manufacturing method thereof and liquid crystal display device |
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| CN201410031062.9A CN103794556A (en) | 2014-01-22 | 2014-01-22 | Array substrate, manufacturing method thereof and liquid crystal display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104460164A (en) * | 2014-12-31 | 2015-03-25 | 厦门天马微电子有限公司 | Thin film transistor array substrate, liquid crystal display device and manufacturing method for thin film transistor array substrate |
| CN106206618A (en) * | 2016-08-30 | 2016-12-07 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof and liquid crystal indicator |
| WO2019214580A1 (en) * | 2018-05-09 | 2019-11-14 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| CN111162096A (en) * | 2020-01-02 | 2020-05-15 | 昆山国显光电有限公司 | Array substrate and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104460164A (en) * | 2014-12-31 | 2015-03-25 | 厦门天马微电子有限公司 | Thin film transistor array substrate, liquid crystal display device and manufacturing method for thin film transistor array substrate |
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| CN111162096A (en) * | 2020-01-02 | 2020-05-15 | 昆山国显光电有限公司 | Array substrate and display panel |
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