CN111162096A - Array substrate and display panel - Google Patents
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- CN111162096A CN111162096A CN202010003349.6A CN202010003349A CN111162096A CN 111162096 A CN111162096 A CN 111162096A CN 202010003349 A CN202010003349 A CN 202010003349A CN 111162096 A CN111162096 A CN 111162096A
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 239000003990 capacitor Substances 0.000 claims abstract description 111
- 238000003860 storage Methods 0.000 claims abstract description 92
- 239000000463 material Substances 0.000 claims abstract description 62
- 239000010410 layer Substances 0.000 claims description 624
- 239000011229 interlayer Substances 0.000 claims description 61
- 239000010409 thin film Substances 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 9
- 239000010408 film Substances 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 description 26
- 230000000694 effects Effects 0.000 description 16
- 238000009413 insulation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
Abstract
The embodiment of the invention discloses an array substrate and a display panel, wherein the array substrate comprises: a substrate base plate having a capacitive region and a non-capacitive region; the storage capacitor is positioned in the capacitor area; the storage capacitor comprises a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are sequentially stacked along the direction far away from the substrate base plate, wherein the third electrode layer is electrically connected with the first electrode layer through a first through hole and is insulated from the second electrode layer; the capacitor further comprises an insulating layer located in the non-capacitance area, and the thickness of the first dielectric layer and/or the second dielectric layer is smaller than that of the insulating layer located in the non-capacitance area and arranged on the same layer and made of the same material. The technical scheme provided by the embodiment of the invention increases the capacitance value of the storage capacitor by combining the increase of the storage capacitor and the change of the thickness of the dielectric layer, so that the display panel keeps unchanged brightness within one frame time, and further displays stable pictures.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to an array substrate and a display panel.
Background
With the development of science and technology, display panels are more and more widely applied to display devices such as smart phones, tablet computers and notebook computers.
The display unit of the display panel displays a stable picture through the driving signal provided by the driving circuit.
The driving signal stability of the display unit in the existing display panel is poor, so that the technical problem of instability of a display picture exists.
Disclosure of Invention
In view of this, embodiments of the present invention provide an array substrate and a display panel, which solve the technical problem in the prior art that a display screen is unstable due to poor stability of a driving signal of a display unit in the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
the substrate comprises a capacitor area and a non-capacitor area arranged adjacent to the capacitor area;
the storage capacitor is positioned on one side of the substrate base plate and positioned in the capacitor area;
the storage capacitor comprises a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are sequentially stacked along the direction far away from the substrate base plate, wherein the third electrode layer is electrically connected with the first electrode layer through a first through hole and is insulated from the second electrode layer;
the array substrate further comprises an insulating layer located in the non-capacitance area, and the thickness of the first dielectric layer and/or the second dielectric layer is smaller than that of the insulating layer which is arranged on the same layer and is made of the same material and located in the non-capacitance area.
The technical scheme increases the capacitance value of the storage capacitor, and prompts the display panel to keep unchanged brightness within a frame time, thereby displaying stable pictures.
Optionally, the array substrate further includes a thin film transistor located in the non-capacitance region, the thin film transistor includes an active layer, a first insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode, the active layer is located between the substrate and the first insulating layer, the gate electrode is located on one side of the first insulating layer away from the active layer, the interlayer insulating layer covers the gate electrode, the source electrode and the drain electrode are located on a surface of the interlayer insulating layer on one side away from the active layer, and the source electrode and the drain electrode are respectively connected to the active layer through second via holes;
the first electrode layer and the grid electrode are positioned on the same layer and are made of the same material;
preferably, the first electrode layer is connected to the gate electrode.
According to the technical scheme, the thin film transistor is manufactured while the storage capacitor is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, the array substrate further includes a power line, the interlayer insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer, the first interlayer insulating layer covers the gate electrode, the second interlayer insulating layer covers the power line and the first interlayer insulating layer, the first dielectric layer and the first interlayer insulating layer are located in the same layer and have the same material, and the second electrode layer and the power line are located in the same layer and have the same material;
preferably, the second electrode layer is connected to the power supply line.
According to the technical scheme, the power line is manufactured while the second electrode layer of the storage capacitor is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, the second interlayer insulating layer and the second dielectric layer are located in the same layer and are made of the same material;
preferably, the thickness of the second dielectric layer is 100nm to 200 nm;
preferably, the third electrode layer and the source electrode and/or the drain electrode are located on the same layer and are made of the same material.
According to the technical scheme, the third electrode layer of the storage capacitor is manufactured, and meanwhile, the source electrode or the drain electrode of the thin film transistor is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, the storage capacitor further includes a third dielectric layer and a fourth electrode layer, the fourth electrode layer is located on a side of the third electrode layer away from the substrate, and the third dielectric layer is located between the third electrode layer and the fourth electrode layer;
the fourth electrode layer is electrically connected with the second electrode layer through a third through hole and is insulated from the third electrode layer;
preferably, the thickness of the third dielectric layer is smaller than that of an insulating layer which is arranged on the same layer and is made of the same material and is located in the non-capacitance region.
The technical scheme further increases the capacitance value of the storage capacitor, so that the display panel keeps unchanged brightness within a frame time, and further displays stable pictures.
Optionally, the array substrate further includes a second insulating layer covering the second interlayer insulating layer, and the third dielectric layer and the second insulating layer are located in the same layer and are made of the same material;
preferably, the thickness of the third dielectric layer is smaller than the thickness of the second insulating layer;
preferably, the thickness of the second insulating layer is 150nm to 300nm, and the thickness of the third dielectric layer is 100nm to 150 nm;
preferably, the material of the second insulating layer is SiNx.
According to the technical scheme, the second insulating layer is manufactured while the third dielectric layer of the storage capacitor is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, the array substrate further includes a first planarization layer covering the second interlayer insulating layer, and the third dielectric layer and the first planarization layer are located in the same layer and are made of the same material;
preferably, the thickness of the third dielectric layer is less than the thickness of the first planarization layer;
preferably, the first planarization layer has a thickness of 1.4 to 1.6 μm, and the third dielectric layer has a thickness of 0.5 to 1 μm.
According to the technical scheme, the first planarization layer is manufactured while the third dielectric layer of the storage capacitor is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, the fourth electrode layer comprises a laminated metal layer of Ti/Al/Ti;
preferably, the thickness of the fourth electrode layer is 500nm to 850 nm.
According to the technical scheme, the fourth electrode layer is formed in the capacitor area, the capacitance value of the large storage capacitor is increased, the display panel is enabled to keep unchanged brightness within one frame time, and then stable pictures are displayed.
Optionally, the array substrate further includes a second planarization layer covering the second interlayer insulating layer, and the insulating layer, which is disposed on the same layer as the second dielectric layer and has the same material as the second dielectric layer and is located in the non-capacitance region, is a stacked film layer of the second interlayer insulating layer and the second planarization layer;
preferably, the second dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer and the second interlayer insulating layer are located in the same layer and have the same material, and the second sub-dielectric layer and the second planarization layer are located in the same layer and have the same material; the thickness of the first sub-dielectric layer is smaller than that of the second interlayer insulating layer, and/or the thickness of the second sub-dielectric layer is smaller than that of the second planarization layer;
preferably, the thickness of the second sub-dielectric layer is 0.5 μm to 1 μm;
preferably, the third electrode layer comprises a laminated metal layer of Ti/Al/Ti;
preferably, the thickness of the third electrode layer is 500nm to 850 nm.
According to the technical scheme, the second interlayer insulating layer of the thin film transistor is manufactured while the first sub-dielectric layer of the storage capacitor is manufactured, and the second planarization layer is manufactured while the second sub-dielectric layer is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate according to any of the first aspects.
According to the technical scheme, the array substrate is used, the capacitance value of the storage capacitor is increased, the display panel is enabled to keep unchanged brightness within one frame time, and then stable pictures are displayed.
According to the technical scheme provided by the embodiment of the invention, the first electrode layer, the first dielectric layer and the second electrode layer in the array substrate form a first sub-storage capacitor, the second electrode layer, the second dielectric layer and the third electrode layer form a second sub-storage capacitor, and the third electrode layer is electrically connected with the first electrode layer through the first via hole and is insulated from the second electrode layer, so that the capacitance value of the storage capacitor is the sum of the capacitance value of the first sub-storage capacitor and the capacitance value of the second sub-storage capacitor, the capacitance value of the storage capacitor is increased, meanwhile, the thickness of the first dielectric layer and the thickness of the second dielectric layer are adjusted, the sum of the capacitance value of the first sub-storage capacitor and the capacitance value of the second sub-storage capacitor reaches an optimal value, and the display panel is enabled to keep unchanged brightness within one frame time by combining the increase of the storage capacitor and the adjustment of the thickness of the dielectric layer, thereby displaying a stable picture.
Drawings
FIG. 1 is a schematic diagram of a driving circuit of a display panel in the prior art;
fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention;
fig. 3-8 are schematic cross-sectional views illustrating steps of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 9-14 are schematic plan views illustrating the steps of a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 15 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 16 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the present invention;
fig. 17 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the present invention;
fig. 18 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the present invention;
fig. 19 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, the reason why the display panel has unstable display images due to the poor stability of the driving signal of the display unit in the prior art is found by the inventor through careful study, and fig. 1 is a schematic diagram of a driving circuit structure of a display panel in the prior art, and referring to fig. 1, the driving circuit is exemplified by 2T1C, and includes a driving thin film transistor M1, a switching thin film transistor M2, and a capacitor C for controlling and maintaining the stability of data, thereby maintaining the brightness of the display panel within a frame time. Wherein M1 and M2 are both P-type TFT tubes. Sn is a driving signal line, Dm is a data signal line, and OLED is an organic light-emitting diode. The larger the capacitance value of the capacitor C is, the more the display panel can maintain unchanged brightness within a frame time, and thus a stable picture can be displayed. The storage capacitance value in the drive circuit in the existing display panel is small, and the electric signal of the light emitting diode used for driving the light of the light emitting unit in the drive circuit is unstable, so that the light emitting unit is unstable in light emitting, and further the display picture is unstable.
In order to solve the technical problems, the invention provides the following solutions:
fig. 2 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the present invention, and referring to fig. 2, the structure of the array substrate includes: a substrate base plate 10, the substrate base plate 10 including a capacitance region a1 and a non-capacitance region a2 disposed adjacent to the capacitance region a 1; a storage capacitor 20 located at one side of the substrate base plate 10 and located in the capacitor area a 1; the storage capacitor 20 includes a first electrode layer 21, a first dielectric layer 22, a second electrode layer 23, a second dielectric layer 24, and a third electrode layer 25, which are sequentially stacked in a direction away from the substrate 10, wherein the third electrode layer 25 is electrically connected to the first electrode layer 21 through a first via 26 and insulated from the second electrode layer 23; the array substrate further comprises an insulating layer located in the non-capacitance region a2, and the thickness of the first dielectric layer 22 and/or the second dielectric layer 24 is less than that of the insulating layer located in the non-capacitance region a2 and formed on the same layer and made of the same material.
It can be known that the thickness of the first dielectric layer 22 and/or the second dielectric layer 24 is smaller than the thickness of the insulating layer located in the non-capacitance region a2 and disposed on the same layer and made of the same material, and the following three cases can be distinguished: the thickness of the first dielectric layer 22 is smaller than that of the insulating layer which is arranged on the same layer and is made of the same material and is positioned in the non-capacitance area A2; the thickness of the second dielectric layer 24 is smaller than that of the insulating layer which is arranged on the same layer and is made of the same material and is positioned in the non-capacitance area A2; the thickness of each of the first dielectric layer 22 and the second dielectric layer 24 is smaller than the thickness of the insulating layer located in the non-capacitance region a2 and disposed on the same layer and made of the same material. The specific arrangement is by reference to actual conditions and is not specifically limited herein.
Specifically, in the present embodiment (as shown in fig. 2), the second dielectric layer 24 and the third insulating layer 13 are located on the same layer and have the same material, and the third insulating layer 13 is fabricated while the second dielectric layer 24 is fabricated, so that the effects of simplifying the process flow and reducing the cost are achieved. The thickness of the second dielectric layer 24 is smaller than that of the third insulating layer 13, and the material corresponding to the thickness difference between the second dielectric layer 24 and the third insulating layer 13 is removed by a thinning process, and it can be known that the third insulating layer 13 in this embodiment is an insulating layer located in the non-capacitance region a2 and disposed on the same layer as the second dielectric layer 24 and having the same material.
In the present embodiment, the first electrode layer 21, the first dielectric layer 22 and the second electrode layer 23 constitute a first sub storage capacitor C11, the second electrode layer 23, the second dielectric layer 24 and the third electrode layer 25 constitute a second sub storage capacitor C22, since the third electrode layer 25 is electrically connected to the first electrode layer 21 through the first via hole 26 and insulated from the second electrode layer 23, the capacitance value of the storage capacitor 20 is the sum of the capacitance value of the first sub-storage capacitor C11 and the capacitance value of the second sub-storage capacitor C22, which increases the capacitance value of the storage capacitor 20, in addition, by adjusting the thickness of the first dielectric layer 22 and the second dielectric layer 24, the sum of the capacitance of the first sub-storage capacitor C11 and the capacitance of the second sub-storage capacitor C22 reaches an optimal value, so that the display panel keeps constant brightness within a frame time, and a stable picture is displayed.
The inventor researches and finds that the technical problem of instability of a display screen cannot be well solved by simply increasing the storage capacitor C22 or simply adjusting the thicknesses of the first dielectric layer 22 and the second dielectric layer 24, and only by combining the two methods of increasing the storage capacitor and adjusting the thicknesses of the dielectric layers, namely, increasing the storage capacitor C22 and adjusting the thicknesses of the first dielectric layer 22 and/or the second dielectric layer 24 to enable the thicknesses of the first dielectric layer 22 and/or the second dielectric layer 24 to be smaller than the thicknesses of insulating layers which are arranged on the same layer and are made of the same material and are positioned in the non-capacitance area a2, the display panel can be effectively promoted to keep constant brightness within one frame time, and the effect of displaying a stable screen is achieved.
It can be known that the array substrate further includes a first insulating layer 12 located on one side of the substrate 10, and the first insulating layer 12 is located in the capacitive region a1 and the non-capacitive region a 2.
It can be known that the array substrate further includes an active layer 11, the active layer 11 is located between the substrate base plate 10 and the first insulating layer 12, and the active layer 11 is located in the capacitive region a1 and the non-capacitive region a 2.
Optionally, on the basis of the above technical solution, referring to fig. 16, the array substrate further includes a thin film transistor 30 located in the non-capacitance region a2, the thin film transistor 30 includes an active layer 11, a first insulating layer 12, a gate electrode 31, an interlayer insulating layer 32, a source electrode 33, and a drain electrode 34, the gate electrode 31 is located on a side of the first insulating layer 12 away from the active layer 11, the interlayer insulating layer 32 covers the gate electrode 31, the source electrode 33 and the drain electrode 34 are located on a surface of the interlayer insulating layer 32 on a side away from the active layer 11, and the source electrode 33 and the drain electrode 34 are respectively connected to the active layer 11 through a second via 35; the first electrode layer 21 and the gate electrode 31 are located on the same layer and are made of the same material; preferably, the first electrode layer 21 is connected to the gate electrode 31.
It should be noted that the thin film transistor 30 in this embodiment may be an NMOS transistor or a PMOS transistor, and the channel type of the thin film transistor 30 is not limited in this embodiment. The exemplary set thin film transistor 30 in this embodiment employs a top gate structure.
Specifically, the preparation method of the array substrate shown in fig. 2 includes the following steps (the schematic cross-sectional structure of the array substrate in this embodiment is a schematic cross-sectional structure at a dotted line in fig. 10 to 14):
step 110, providing a substrate, wherein the substrate comprises a capacitor area and a non-capacitor area adjacent to the capacitor area.
Referring to fig. 3 and 9, a substrate base 10 is provided, the substrate base 10 including a capacitive region a1 and a non-capacitive region a2 disposed adjacent to the capacitive region a 1.
And step 120, forming an active layer on one side of the substrate base plate, wherein the active layer is positioned in the capacitance area and the non-capacitance area.
Referring to fig. 4 and 10, the active layer 11 is formed on one side of the base substrate 10 and is positioned in the capacitive region a1 and the non-capacitive region a 2.
Step 130, forming a first insulating layer on the side of the active layer away from the substrate base plate.
Referring to fig. 5 and 11, a first insulating layer 12 is formed on a side of the active layer 11 away from the base substrate 10.
Step 140, forming a storage capacitor on the side of the first insulating layer away from the substrate and in the capacitor region.
Referring to fig. 2, a storage capacitor 20 is formed at a side of the first insulating layer 12 away from the substrate base plate 10, and at a capacitor area a 1.
Optionally, on the basis of the foregoing technical solution, step 140 includes: forming a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are sequentially stacked along a direction far away from the active layer, wherein the third electrode layer is electrically connected with the first electrode layer through a first through hole and is insulated from the second electrode layer; the array substrate further comprises a third insulating layer located in the non-capacitance area, the second dielectric layer and the third insulating layer are located in the same layer and are made of the same material, and the thickness of the second dielectric layer is smaller than that of the third insulating layer.
Referring to fig. 6 and 12, a first electrode layer 21 and a first dielectric layer 22, which are sequentially stacked, are formed in a direction away from the active layer 11. Wherein, the first dielectric layer 22 further includes forming a first via 26 during the manufacturing process, and the specific process may be etching. It should be noted that the active layer 11 is patterned, and an orthographic projection of the first via 26 on the substrate 10 may or may not overlap with an orthographic projection of the active layer 11 on the substrate 10.
Referring to fig. 7 and 13, a second electrode layer 23 is formed over the first dielectric layer 22 in a direction away from the active layer 11. The second electrode layer 23 is patterned, and the second electrode layer 23 is insulated from the first electrode layer 21 by the first via hole 26.
Referring to fig. 8 and 14, a second dielectric layer 24 and a third electrode layer 25 are formed over the second electrode layer 23 in a direction away from the active layer 11. The second dielectric layer 24 is formed by forming a first via 26 during the manufacturing process, which may be etching. The third electrode layer 25 is electrically connected to the first electrode layer 21 through a first via 26 and insulated from the second electrode layer 23; the array substrate further comprises a third insulating layer 13 located in the non-capacitance area a2, the second dielectric layer 24 and the third insulating layer 13 are located in the same layer and have the same material, and the thickness of the second dielectric layer 24 is smaller than that of the third insulating layer 13. The third insulating layer 13 is formed while the second dielectric layer 24 is formed, so that the effects of simplifying the process flow and reducing the cost are achieved. The material corresponding to the difference in thickness between the second dielectric layer 24 and the third insulating layer 13 is removed by a thinning process. Illustratively, thinning may be achieved using a half tone mask (halftone mask) or a slit mask (slit mask) to obtain the second dielectric layer 24. In addition, the thinning process related to any embodiment of the invention can be realized by adopting a halftone mask or a slitmask.
The second electrode layer 23 is a patterned second electrode layer. In the process of forming the first via 26, after forming the first insulating layer 12 on the side of the active layer 11 away from the substrate 10, the first electrode layer 21, the first dielectric layer 22, the patterned second electrode layer 23, and the second dielectric layer 24 are formed on the first insulating layer 12 along the direction away from the active layer 11, and then the first via 26 is formed on the surface of the second dielectric layer 24 away from the second electrode layer 23 to expose the first electrode layer 21.
Optionally, on the basis of the above technical solution, referring to fig. 15, the array substrate further includes a buffer layer 18, and the buffer layer 18 may be an inorganic material, for example, silicon oxide and silicon nitride, or may also be a stack of silicon oxide and silicon nitride. It is understood that the material of buffer layer 18 includes, but is not limited to, the above examples. The thickness of the buffer layer 18 is selected, and the specific thickness of the buffer layer 18 can be adjusted according to the product requirement.
In the present embodiment, the thin film transistor 30 in the non-capacitance region a2 includes an active layer 11, a first insulating layer 12, a gate electrode 31, an interlayer insulating layer 32, a source electrode 33, and a drain electrode 34, the gate electrode 31 is located on a side of the first insulating layer 12 away from the active layer 11, the interlayer insulating layer 32 covers the gate electrode 31, the source electrode 33 and the drain electrode 34 are located on a surface of the interlayer insulating layer 32 on the side away from the active layer 11, and the source electrode 33 and the drain electrode 34 are electrically connected to the active layer 11 through a second via 35; the first electrode layer 21 and the gate 31 are located in the same layer and have the same material, so that the thin film transistor 30 is manufactured while the storage capacitor 20 is manufactured, thereby achieving the effects of simplifying the process flow and reducing the cost.
Preferably, the first electrode layer 21 is connected to the gate electrode 31. The first electrode layer 21 and the gate electrode have the same power supply signal.
Optionally, on the basis of the above technical solution, referring to fig. 16, the array substrate further includes a power line 14, the interlayer insulating layer 32 includes a first interlayer insulating layer 321 and a second interlayer insulating layer 322, the first interlayer insulating layer 321 covers the gate electrode 31, the second interlayer insulating layer 322 covers the power line 14 and the first interlayer insulating layer 321, the first dielectric layer 22 and the first interlayer insulating layer 321 are located in the same layer and have the same material, and the second electrode layer 23 and the power line 14 are located in the same layer and have the same material; preferably, the second electrode layer 23 is connected to the power supply line 14.
The power line 14 may be a transverse power line or a longitudinal power line. And is electrically connected to the source of the driving transistor in the thin film transistor 30 for supplying a power supply signal.
The first dielectric layer 22 and the first interlayer insulating layer 321 are located on the same layer and have the same material, the second electrode layer 23 and the power line 14 are located on the same layer and have the same material, the first interlayer insulating layer 321 of the thin film transistor 30 is manufactured while the first dielectric layer 22 of the storage capacitor 20 is manufactured, and the power line 14 is manufactured while the second electrode layer 23 of the storage capacitor 20 is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, on the basis of the above technical solution, referring to fig. 16, the second interlayer insulating layer 322 is located at the same layer and has the same material as the second dielectric layer 24. I.e., the thickness of the second interlayer insulating layer 322 is greater than the thickness of the second dielectric layer 24. Preferably, the thickness of the second dielectric layer 24 is 100nm to 200 nm. In this embodiment, the second interlayer insulating layer 322 is an insulating layer disposed on the same layer as the second dielectric layer 24 and having the same material in the non-capacitance region a 2.
The thickness of the second dielectric layer 24 being less than 100nm may result in poor insulation between the first electrode layer 21 and the second electrode layer 23, and the thickness of the second dielectric layer 24 being greater than 200nm may result in too small a capacitance value of the first sub-storage capacitor C22, which affects the capacitance value of the storage capacitor 20. Therefore, the thickness of the second dielectric layer 24 is 100nm to 200nm, and the capacitance value of the storage capacitor 20 is increased while the insulation of the second dielectric layer 24 is ensured.
Preferably, the third electrode layer 25 is located at the same layer and has the same material as the source electrode 33 or the drain electrode 34.
The third electrode layer 25 of the storage capacitor 20 is simultaneously formed, and the source 33 or the drain 34 of the thin film transistor 30 is formed, so that the process flow is simplified and the cost is reduced.
Optionally, on the basis of the above technical solution, referring to fig. 17, the storage capacitor 20 further includes a third dielectric layer 27 and a fourth electrode layer 28, the fourth electrode layer 28 is located on a side of the third electrode layer 25 away from the substrate base plate 10, and the third dielectric layer 27 is located between the third electrode layer 25 and the fourth electrode layer 28; the fourth electrode layer 28 is electrically connected to the second electrode layer 23 through the third via hole 29 and insulated from the third electrode layer 25.
Optionally, the thickness of the third dielectric layer 27 is smaller than that of the insulating layer located in the non-capacitance region a2 and disposed on the same layer and made of the same material.
In this embodiment, the first electrode layer 21, the first dielectric layer 22, the second electrode layer 23, the second dielectric layer 24, the third electrode layer 25, the third dielectric layer 27 and the fourth electrode layer 28 constitute a storage capacitor, wherein the first electrode layer 21, the first dielectric layer 22 and the second electrode layer 23 constitute a first sub-storage capacitor C11, the second electrode layer 23, the second dielectric layer 24 and the third electrode layer 25 constitute a second sub-storage capacitor C22, the third electrode layer 25, the third dielectric layer 27 and the fourth electrode layer 28 constitute a third sub-storage capacitor C33, the third electrode layer 25 is electrically connected to the first electrode layer 21 through the first via 26 and insulated from the second electrode layer 23, and the fourth electrode layer 28 is electrically connected to the second electrode layer 23 through the third via 29 and insulated from the third electrode layer 25, so that the capacitance value of the storage capacitor 20 is the capacitance value of the first sub-storage capacitor C11, The sum of the capacitance of the second sub-storage capacitor C22 and the capacitance of the third sub-storage capacitor C33 further increases the capacitance of the storage capacitor 20, and at the same time, the thicknesses of the first dielectric layer 22, the second dielectric layer 24 and the third dielectric layer 27 are adjusted to make the sum of the capacitance of the first sub-storage capacitor C11, the capacitance of the second sub-storage capacitor C22 and the capacitance of the third sub-storage capacitor C33 reach an optimal value.
The third electrode layer 25 is a patterned third electrode layer. During the formation of the third via 29, after the second dielectric layer 24, the patterned third electrode layer 25 and the third dielectric layer 27 are formed, the third via 29 is formed on the surface of the third dielectric layer 27 away from the third electrode layer 25, exposing the second electrode layer 23. It should be noted that the active layer 11 is patterned, and an orthographic projection of the third via 29 on the substrate 10 may or may not overlap with an orthographic projection of the active layer 11 on the substrate 10.
Optionally, on the basis of the above technical solution, referring to fig. 17, the array substrate further includes a second insulating layer 15 covering the second interlayer insulating layer 322, and the third dielectric layer 27 and the second insulating layer 15 are located on the same layer and have the same material.
The second insulating layer 15 is formed at the same time as the third dielectric layer 27 of the storage capacitor 20, so that the process flow is simplified and the cost is reduced.
Preferably, the thickness of the third dielectric layer 27 is less than the thickness of the second insulating layer 15.
The material corresponding to the difference in thickness between the thickness of the third dielectric layer 27 and the thickness of the second insulating layer 15 is removed by a thinning process.
It is to be understood that the second insulating layer 15 in this embodiment is an insulating layer disposed on the same layer and made of the same material as the third dielectric layer 27 and located in the non-capacitance region a 2.
Preferably, the thickness of the second insulating layer 15 is 150nm to 300nm, and the thickness of the third dielectric layer 27 is 100nm to 150 nm; the thickness of the third dielectric layer 27 being less than 100nm may result in poor insulation between the third electrode layer 25 and the fourth electrode layer 28, and the thickness of the third dielectric layer 27 being greater than 150nm may result in too small a capacitance value of the third sub-storage capacitor C33 formed by the third electrode layer 25, the third dielectric layer 27 and the fourth electrode layer 28, which affects the capacitance value of the storage capacitor 20.
Preferably, the material of the second insulating layer 15 is SiNx.
Optionally, on the basis of the above technical solution, referring to fig. 18, the array substrate further includes a first planarization layer 16 covering the second interlayer insulating layer 322, and the third dielectric layer 27 is located on the same layer and has the same material as the first planarization layer 16; the first planarization layer 16 is formed at the same time of forming the third dielectric layer 27 of the storage capacitor 20, thereby achieving the effects of simplifying the process flow and reducing the cost.
Preferably, the thickness of the third dielectric layer 27 is less than the thickness of the first planarization layer 16.
The material corresponding to the difference in thickness between the thickness of the third dielectric layer 27 and the thickness of the first planarization layer 16 is removed by a thinning process.
It is to be understood that the first planarization layer 16 in this embodiment is an insulating layer disposed on the same layer and made of the same material as the third dielectric layer 27 in the non-capacitance region a 2.
Preferably, the thickness of the first planarization layer 16 is 1.4 μm to 1.6 μm, and the thickness of the third dielectric layer 27 is 0.5 μm to 1 μm. The thickness of the third dielectric layer 27 matches that of the first planarizing layer 16, the first planarizing layer 16 being of the order of microns thick, and the third dielectric layer 27 also being of the order of microns thick. The thickness of the first planarization layer 16 is less than 1.4 μm, which does not form a flat cross section well, and is not favorable for forming an anode and a film corresponding to the display unit above the thin film transistor 30. The thickness of the first planarizing layer 16 is greater than 1.6 μm and is too thick, affecting the thickness of the entire array substrate.
Wherein the thickness of the third dielectric layer 27 is less than 0.5 μm, which may result in poor insulation between the third electrode layer 25 and the fourth electrode layer 28, and the thickness of the third dielectric layer 27 is greater than 1 μm, which may result in too small a capacitance value of the third sub-storage capacitor C33 formed by the third electrode layer 25, the third dielectric layer 27 and the fourth electrode layer 28, which may affect the capacitance value of the storage capacitor 20.
Optionally, on the basis of the above technical solution, the fourth electrode layer 28 includes a Ti/Al/Ti stacked metal layer, and the effect achieved by the Ti/Al/Ti stacked metal layer is more excellent than the effect achieved by a single Ti/Al metal layer, for example, the Ti/Al/Ti stacked metal layer has better conductivity and stronger stability. Note that the fourth electrode layer 28 is formed only in the capacitor region a 1. Wherein the first electrode layer 21, the first dielectric layer 22, the second electrode layer 23 constitute a first sub-storage capacitor C11, the second electrode layer 23, the second dielectric layer 24 and the third electrode layer 25 constitute a second sub-storage capacitor C22, the third electrode layer 25, the third dielectric layer 27 and the fourth electrode layer 28 constitute a third sub-storage capacitor C33, since the third electrode layer 25 is electrically connected to the first electrode layer 21 through the first via hole 26 and insulated from the second electrode layer 23, and the fourth electrode layer 28 is electrically connected to the second electrode layer 23 through the third via hole 29 and insulated from the third electrode layer 25, the capacitance value of the storage capacitor 20 is the sum of the capacitance value of the first sub-storage capacitor C11, the capacitance value of the second sub-storage capacitor C22 and the capacitance value of the third sub-storage capacitor C33, so that the sum of the capacitance values of the first sub-storage capacitor C11, the second sub-storage capacitor C22 and the third sub-storage capacitor C33 reaches an optimal value, the display panel is promoted to keep unchanged brightness within a frame time, and then stable pictures are displayed.
Preferably, the thickness of the fourth electrode layer 28 is 500nm to 850 nm. The thickness of the fourth electrode layer 28 is less than 500nm, so that the capacitance value of the third electrode layer 25, the third dielectric layer 27 and the fourth electrode layer 28 constituting the third sub-storage capacitance C33 is too small; the thickness of the fourth electrode layer 28 is greater than 850nm, affecting the thickness of the entire array substrate.
Optionally, on the basis of the above technical solution, referring to fig. 19, the array substrate further includes a second planarization layer 17 covering the second interlayer insulating layer 322.
It is to be understood that the stacked film layers of the second interlayer insulating layer 322 and the second planarizing layer 17 in this embodiment are an insulating layer structure located in the non-capacitance region a2 and disposed on the same layer as the second dielectric layer 24 and having the same material.
Preferably, the second dielectric layer 24 includes a first sub-dielectric layer 241 and a second sub-dielectric layer 242, the first sub-dielectric layer 241 and the second interlayer insulating layer 322 are located at the same layer and have the same material, and the second sub-dielectric layer 242 and the second planarization layer 17 are located at the same layer and have the same material; the thickness of the first sub-dielectric layer 241 is less than that of the second interlayer insulating layer 322, and/or the thickness of the second sub-dielectric layer 242 is less than that of the second planarization layer 17.
The second interlayer insulating layer 322 of the thin film transistor 30 is formed while the first sub-dielectric layer 241 of the storage capacitor 20 is formed, and the second planarization layer 17 is formed while the second sub-dielectric layer 242 is formed, so that the effects of simplifying the process flow and reducing the cost are achieved.
Wherein, the material of the first sub-dielectric layer 241 having the thickness corresponding to the difference between the thicknesses of the second interlayer insulating layers 322 is removed by the thinning process, and/or the material of the second sub-dielectric layer 242 having the thickness corresponding to the difference between the thicknesses of the second planarization layers 17 is removed by the thinning process.
In this embodiment, the first electrode layer 21, the first dielectric layer 22 and the second electrode layer 23 form a first sub-storage capacitor C11, the second electrode layer 23, the second dielectric layer 24 and the third electrode layer 25 form a second sub-storage capacitor C22, and since the third electrode layer 25 is electrically connected to the first electrode layer 21 through the first via 26 and is insulated from the second electrode layer 23, the capacitance value of the storage capacitor 20 is the sum of the capacitance value of the first sub-storage capacitor C11 and the capacitance value of the second sub-storage capacitor C22, and in addition, the sum of the capacitance value of the first sub-storage capacitor C11 and the capacitance value of the second sub-storage capacitor C22 reaches an optimal value by adjusting the thicknesses of the first dielectric layer 22 and the second dielectric layer 24, so that the display panel is prompted to maintain constant brightness within one frame time, and further display a stable picture.
Preferably, the thickness of the second sub-dielectric layer 242 is 0.5 μm to 1 μm.
The thickness of the second sub-dielectric layer 242 matches the thickness of the second planarization layer 17, the thickness of the second planarization layer 17 is in the order of micrometers, and the thickness of the second sub-dielectric layer 242 is also in the order of micrometers. A thickness of the second sub-dielectric layer 242 smaller than 0.5 μm may result in poor insulation between the second electrode layer 23 and the third electrode layer 25, and a thickness of the second sub-dielectric layer 242 larger than 1 μm may result in too small a capacitance value of the second electrode layer 23 and the third electrode layer 25 constituting the second sub-storage capacitor C22, which affects a capacitance value of the storage capacitor 20.
Preferably, the third electrode layer 25 comprises a laminated metal layer of Ti/Al/Ti. Note that the third electrode layer 25 is formed only in the capacitor region a 1. The third electrode layer 25 is not provided in the same layer as the source electrode 33 or the drain electrode 34 of the thin film transistor 30.
Optionally, the thickness of the third electrode layer 25 is 500nm to 850 nm.
The embodiment of the invention also provides a display panel which comprises the array substrate provided by any embodiment.
The display panel provided by the embodiment of the invention can be applied to display equipment with a display function, such as mobile phones, computers, intelligent wearable equipment and the like, and the embodiment of the invention is not limited to the display equipment.
The display panel provided by the embodiment of the invention comprises the array substrate provided by the embodiment of the invention, has the same functions and effects, and is not described again here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An array substrate, comprising:
the substrate comprises a capacitor area and a non-capacitor area arranged adjacent to the capacitor area;
the storage capacitor is positioned on one side of the substrate base plate and positioned in the capacitor area;
the storage capacitor comprises a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer which are sequentially stacked along the direction far away from the substrate base plate, wherein the third electrode layer is electrically connected with the first electrode layer through a first through hole and is insulated from the second electrode layer;
the array substrate further comprises an insulating layer located in the non-capacitance area, and the thickness of the first dielectric layer and/or the second dielectric layer is smaller than that of the insulating layer which is arranged on the same layer and is made of the same material and located in the non-capacitance area.
2. The array substrate of claim 1, further comprising a thin film transistor located in the non-capacitance region, wherein the thin film transistor comprises an active layer, a first insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode, the active layer is located between the substrate and the first insulating layer, the gate electrode is located on one side of the first insulating layer away from the active layer, the interlayer insulating layer covers the gate electrode, the source electrode and the drain electrode are located on the surface of the interlayer insulating layer on one side away from the active layer, and the source electrode and the drain electrode are respectively connected with the active layer through a second via hole;
the first electrode layer and the grid electrode are positioned on the same layer and are made of the same material;
preferably, the first electrode layer is connected to the gate electrode.
3. The array substrate of claim 2, further comprising a power line, wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second interlayer insulating layer, the first interlayer insulating layer covers the gate electrode, the second interlayer insulating layer covers the power line and the first interlayer insulating layer, the first dielectric layer and the first interlayer insulating layer are in the same layer and are of the same material, and the second electrode layer and the power line are in the same layer and are of the same material;
preferably, the second electrode layer is connected to the power supply line.
4. The array substrate of claim 3, wherein the second interlayer insulating layer and the second dielectric layer are located on the same layer and are made of the same material;
preferably, the thickness of the second dielectric layer is 100nm to 200 nm;
preferably, the third electrode layer and the source electrode and/or the drain electrode are located on the same layer and are made of the same material.
5. The array substrate of claim 3 or 4, wherein the storage capacitor further comprises a third dielectric layer and a fourth electrode layer, the fourth electrode layer is located on a side of the third electrode layer away from the substrate, and the third dielectric layer is located between the third electrode layer and the fourth electrode layer;
the fourth electrode layer is electrically connected with the second electrode layer through a third through hole and is insulated from the third electrode layer;
preferably, the thickness of the third dielectric layer is smaller than that of an insulating layer which is arranged on the same layer and is made of the same material and is located in the non-capacitance region.
6. The array substrate of claim 5, further comprising a second insulating layer covering the second interlayer insulating layer, wherein the third dielectric layer is located on the same layer and is the same material as the second insulating layer;
preferably, the thickness of the third dielectric layer is smaller than the thickness of the second insulating layer;
preferably, the thickness of the second insulating layer is 150nm to 300nm, and the thickness of the third dielectric layer is 100nm to 150 nm;
preferably, the material of the second insulating layer is SiNx。
7. The array substrate of claim 5, further comprising a first planarization layer covering the second interlayer insulating layer, wherein the third dielectric layer is in the same layer and material as the first planarization layer;
preferably, the thickness of the third dielectric layer is less than the thickness of the first planarization layer;
preferably, the first planarization layer has a thickness of 1.4 to 1.6 μm, and the third dielectric layer has a thickness of 0.5 to 1 μm.
8. The array substrate of claim 6 or 7, wherein the fourth electrode layer comprises a laminated metal layer of Ti/Al/Ti;
preferably, the thickness of the fourth electrode layer is 500nm to 850 nm.
9. The array substrate of claim 3, further comprising a second planarization layer covering the second interlayer insulating layer, wherein the insulating layer disposed in the same layer as the second dielectric layer and having the same material in the non-capacitance region is a stacked film layer of the second interlayer insulating layer and the second planarization layer;
preferably, the second dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer and the second interlayer insulating layer are located in the same layer and have the same material, and the second sub-dielectric layer and the second planarization layer are located in the same layer and have the same material; the thickness of the first sub-dielectric layer is smaller than that of the second interlayer insulating layer, and/or the thickness of the second sub-dielectric layer is smaller than that of the second planarization layer;
preferably, the thickness of the second sub-dielectric layer is 0.5 μm to 1 μm;
preferably, the third electrode layer comprises a laminated metal layer of Ti/Al/Ti;
preferably, the thickness of the third electrode layer is 500nm to 850 nm.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| CN202010003349.6A CN111162096A (en) | 2020-01-02 | 2020-01-02 | Array substrate and display panel |
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| CN202010003349.6A CN111162096A (en) | 2020-01-02 | 2020-01-02 | Array substrate and display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11393896B2 (en) * | 2020-01-17 | 2022-07-19 | Murata Manufacturing Co., Ltd. | Semiconductor device and module |
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| CN103794556A (en) * | 2014-01-22 | 2014-05-14 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display device |
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