CN106206618A - Array base palte and preparation method thereof and liquid crystal indicator - Google Patents
Array base palte and preparation method thereof and liquid crystal indicator Download PDFInfo
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- CN106206618A CN106206618A CN201610770008.5A CN201610770008A CN106206618A CN 106206618 A CN106206618 A CN 106206618A CN 201610770008 A CN201610770008 A CN 201610770008A CN 106206618 A CN106206618 A CN 106206618A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention discloses a kind of array base palte, including plate electrode, gap electrode and the insulating barrier between described plate electrode and described gap electrode, and each sub-pixel divided on described array base palte all includes main pixel region and sub-pixel region, described sub-pixel region comprises and drop-down shares electric capacity, the described drop-down thickness of insulating layer sharing region corresponding to electric capacity is less than the described drop-down thickness of insulating layer shared outside the region that electric capacity is corresponding, in described sub-pixel region, gap electrode and the overlapping region of described plate electrode are described drop-down to share the region that electric capacity is corresponding.The invention also discloses manufacture method and the liquid crystal indicator of a kind of array base palte.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of array base palte and preparation method thereof and liquid crystal display
Device.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) has that fuselage is thin, power saving, radiationless etc. numerous excellent
Point, is widely used.As, LCD TV, mobile phone, personal digital assistant (Personal Digital
Assistant, PDA), digital camera, computer screen or notebook computer screen etc., account for importantly in flat display field
Position.
Liquid crystal display major part on existing market is backlight liquid crystal display, and it includes housing, is located in housing
Display panels and the backlight module be located in housing.Display panels is the primary clustering of liquid crystal display, but liquid
LCD panel itself is the most luminous, needs the light source provided by backlight module to carry out show image.Generally display panels by
Colored filter substrate (Color Filter, CF), thin-film transistor array base-plate (Thin Film Transistor Array
Substrate, TFT Array Substrate) and liquid crystal layer (the Liquid Crystal that is configured between two substrates
Layer) constitute, and pixel electrode and public electrode are set in the relative inner of two substrates, and by applying Control of Voltage liquid crystal
Molecular changes direction, thus the light of backlight module is reflected generation picture.
Along with the fast development of LCD board industry, the size of display panels is done bigger and bigger, and user is to extensively regarding
Angle, low colour cast, low energy consumption requirement more and more higher, thus TFT device and pixel design also diversified development.At present, existing
The pixel design that technology uses multidomain (multi domain) to show mostly improves display panels color under big visual angle
Degree, typically has 4 farmlands, 8 farmlands partially.In pixel electrode patternization design, 8 farmlands there is no difference with 4 farmlands, and 8 farmlands need one
Individual sub-pixel is divided into main pixel (Main Pixel) and two regions of sub-pixel (Sub Pixel), by a sub-pixel
Main pixel region makes the liquid crystal on two 4 farmlands different and form 8 farmlands, further according to rotation amount from the pressure reduction in sub-pixel region
Ground, the main pixel region in a sub-pixel mainly shares sub-pixel by drop-down electric capacity of sharing with the pressure reduction in sub-pixel region
The electric charge in region realizes.
But, in each sub-pixel of existing array base palte and display panels, secondly in pixel region under
It is the thickest that pulling enjoys the insulating barrier between two battery lead plates of electric capacity so that the spacing between two battery lead plates is relatively big, therefore constitutes
The area of the drop-down two-plate sharing electric capacity is also required to be correspondingly arranged to can be only achieved more greatly the drop-down capacitance of setting, not only shadow
Ring pixel aperture ratio, and backlight power is big, relatively costly.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof and liquid crystal indicator, can reduce under composition
Pulling enjoys the spacing between the two-plate of electric capacity so that can reduce drop-down the two poles of the earth sharing electric capacity on the premise of same capacitance
The area of plate, thus increase pixel aperture ratio.
On the one hand, embodiments provide a kind of array base palte, including plate electrode, gap electrode be positioned at described
Each sub-pixel divided on insulating barrier between plate electrode and described gap electrode, and described array base palte all includes
Main pixel region and sub-pixel region, comprise drop-down electric capacity of sharing in described sub-pixel region, described drop-down to share electric capacity corresponding
The thickness of insulating layer in region less than the described drop-down thickness of insulating layer shared outside the region that electric capacity is corresponding, wherein, described time
Gap electrode in pixel region and the overlapping region of described plate electrode are described drop-down to share the region that electric capacity is corresponding.
Wherein, described plate electrode is pixel electrode, and described gap electrode is public electrode；Or, described plate electrode
For public electrode, described gap electrode is pixel electrode.
Wherein, the described insulating barrier between described plate electrode and described gap electrode includes the grid being cascading
Insulating barrier, at least one of which passivation layer and color blocking layer, wherein, the described drop-down color blocking layer in region corresponding to electric capacity of sharing is by completely
Remove.
Wherein, the described insulating barrier between described plate electrode and described gap electrode includes the grid being cascading
Insulating barrier and passivation layer, wherein, the described drop-down passivation layer sharing region corresponding to electric capacity is completely removed, described gate insulator
Layer is thinned.
Wherein, the described insulating barrier between described plate electrode and described gap electrode includes the grid being cascading
Insulating barrier and passivation layer, wherein, the described drop-down gate insulator sharing region corresponding to electric capacity is completely removed, described passivation
Layer is thinned.
On the other hand, the embodiment of the present invention additionally provides a kind of liquid crystal indicator with above-mentioned array base palte.
On the other hand, the embodiment of the present invention additionally provides the manufacture method of a kind of array base palte, comprises the following steps:
Form TFT, grid line and data wire on a substrate；
Plate electrode is formed on the basis of including described TFT, grid line and data wire；
The substrate including described plate electrode is formed insulating barrier, drop-down on described insulating barrier is shared electric capacity corresponding
Region perform etching, make the described drop-down thickness of insulating layer sharing region corresponding to electric capacity drop-down share electric capacity pair less than described
Thickness of insulating layer outside the region answered；
The substrate including described insulating barrier is formed gap electrode, in the sub-pixel region on array base palte, described
Gap electrode and the overlapping region of described plate electrode are described drop-down to share the region that electric capacity is corresponding.
Wherein, described formation insulating barrier on the substrate including described plate electrode, to the lower pulling on described insulating barrier
The region enjoying electric capacity corresponding performs etching, and makes the described drop-down thickness of insulating layer in region corresponding to electric capacity of sharing less than described drop-down
Share the thickness of insulating layer outside the region that electric capacity is corresponding, including:
Depositing insulating layer material on the substrate including described plate electrode；
The substrate including described insulating layer material deposits photoresist；
The described photoresist of insulating barrier via area is exposed completely, drop-down shares the region that electric capacity is corresponding to described
Described photoresist carry out halftone exposure；
Photoresist is developed, makes the photoresist of described insulating barrier via area remove completely, make described drop-down share
The photoresist in the region that electric capacity is corresponding is thinning；
The insulating layer material of described insulating barrier via area is performed etching, forms insulating barrier via；
Described photoresist is ashed, makes the described drop-down photoresist sharing region corresponding to electric capacity remove completely, institute
State the drop-down photoresist shared outside the region that electric capacity is corresponding thinning；
The described drop-down insulating layer material sharing region corresponding to electric capacity is performed etching, makes described drop-down to share electric capacity pair
The thickness of insulating layer in the region answered is less than the described drop-down thickness of insulating layer shared outside the region that electric capacity is corresponding；
Remove remaining photoresist.
Wherein, described insulating barrier includes gate insulator and the passivation layer being cascading, and described drop-down shares
The described passivation layer in the region that electric capacity is corresponding is completely removed, described gate insulator is thinned.
Wherein, described insulating barrier includes gate insulator and the passivation layer being cascading, and described drop-down shares
The described gate insulator in the region that electric capacity is corresponding is completely removed, described passivation layer is thinned.
Wherein, described insulating barrier includes gate insulator, at least one passivation layer and the color blocking layer being cascading, and
The described drop-down color blocking layer sharing region corresponding to electric capacity is completely removed.
The array base palte provided in the embodiment of the present invention and liquid crystal indicator, drop-down electric capacity of sharing in sub-pixel region
Thickness of insulating layer is less than the drop-down thickness of insulating layer shared outside electric capacity corresponding region, reduces the drop-down tabular sharing electric capacity of composition
Distance between electrode and gap electrode so that this drop-down area sharing electric capacity also can corresponding reduce, thus increases pixel
Aperture opening ratio, it is possible to energy efficient, reduce cost.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the drop-down cross-sectional view shared at electric capacity in array base palte of the present invention；
Fig. 2 is the drop-down cross-sectional view shared at electric capacity in array base palte in first embodiment of the invention；
Fig. 3 is the drop-down cross-sectional view shared at electric capacity in array base palte in second embodiment of the invention；
Fig. 4 is the flow chart of the manufacture method of the liquid crystal display pixel structure of the present invention；
Fig. 5 be the liquid crystal display pixel structure of the present invention manufacture method in the flow chart of step 403；
Fig. 6, Fig. 7 are corresponding to the schematic diagram of step 403 in Fig. 4.
Detailed description of the invention
Below in conjunction with the accompanying drawing in embodiment of the present invention, the technical scheme in embodiment of the present invention is carried out clearly
Chu, it is fully described by.Obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiment party
Formula.Based on the embodiment in the present invention, those of ordinary skill in the art are obtained on the premise of not making creative work
The every other embodiment obtained, all should belong to the scope of protection of the invention.
Additionally, the explanation of following embodiment is with reference to additional diagram, the spy implemented in order to illustrate the present invention may be used to
Determine embodiment.The direction term being previously mentioned in the present invention, such as, " on ", D score, "front", "rear", "left", "right", " interior ",
" outward ", " side " etc., be only the direction with reference to annexed drawings, and therefore, the direction term of use is in order to more preferably, more clearly say
Bright and understand the present invention rather than instruction or infer the device of indication or element must have specific orientation, with specific side
Position structure and operation, be therefore not considered as limiting the invention.
In describing the invention, it should be noted that unless otherwise clearly defined and limited, term " is installed ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be fixing connection, it is also possible to be detachably connected, or connect integratedly
Connect；Can be to be mechanically connected；Can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, in can being two elements
The connection in portion.For the ordinary skill in the art, above-mentioned term tool in the present invention can be understood with concrete condition
Body implication.
Additionally, in describing the invention, except as otherwise noted, " multiple " are meant that two or more.If this
Occurring the term of " operation " in description, it refers not only to independent operation, when cannot clearly distinguish with other operation, as long as
The effect desired by described operation that can realize then is also included within this term.It addition, in this specification with "～" numerical value that represents
Scope refer to using "～" before and after the scope that is included as minima and maximum of numerical value recorded.In the accompanying drawings, knot
The similar or identical unit of structure is indicated by the same numeral.
Embodiments provide a kind of array base palte, constitute in sub-pixel region drop-down can be reduced and share electric capacity
Two-plate between spacing so that the area of two-plate can be reduced under same capacitance premise, thus increase pixel openings
Rate.It is described in detail individually below.
Please refer to Fig. 1, present invention firstly provides a kind of array base palte, including plate electrode 10, gap electrode 30 and
Insulating barrier 50 between described plate electrode 10 and gap electrode 30, and each height divided on described array base palte
Pixel all includes main pixel region and sub-pixel region (not shown), comprises the drop-down electric capacity C that shares, institute in described sub-pixel region
State drop-down insulating barrier 50 thickness sharing electric capacity C corresponding region (the most drop-down share electric capacity C region) less than under described
Pulling enjoys the thickness of insulating layer outside electric capacity C region, in described sub-pixel region, and gap electrode 10 and described plate electrode 30
Overlapping region is described drop-down to share electric capacity 50 region.
Further, described plate electrode 10 is pixel electrode, and described gap electrode 30 is public electrode；Or described plate
Shape electrode 10 is public electrode, and described gap electrode 30 is pixel electrode.
Referring to Fig. 2, the array base palte of first embodiment of the invention, this array base palte uses COA (color filter
On array) technology, will be also formed on this array base palte by color blocking layer, wherein, described plate electrode 10 and described slit electricity
Insulating barrier 50 between pole 30 includes gate insulator 51, at least one of which passivation layer 53 and the color blocking layer 55 stacked gradually, and
And the described drop-down color blocking layer 55 sharing electric capacity C region is completely removed and reduces the thickness of insulating barrier 50 at this, described drop-down
Share insulating barrier 50 thickness beyond electric capacity C region constant.
It is appreciated that described passivation layer 53 can be one layer, it is also possible to be two-layer, in order to reduce plate electrode 10 and slit
Distance between electrode 30, being preferably provided with described passivation layer 53 is one layer.
The COA array base palte of the present embodiment, removes the drop-down color blocking layer 55 sharing electric capacity C region so that described drop-down
Share the spacing between the battery lead plate 10,30 of electric capacity C identical with regular array substrate (the most non-COA array base palte), therefore, described
Plate electrode 10 also can normally be arranged with the area of described gap electrode 30, and the most existing COA array base palte increases pixel
Aperture opening ratio.
Refer to Fig. 3, the array base palte of second embodiment of the invention, described plate electrode 10 and described gap electrode 30 it
Between insulating barrier 70 gate insulator 71 that includes stacking gradually and passivation layer 73, wherein said drop-down electric capacity C region of sharing
Passivation layer 73 is completely removed, gate insulator 71 is thinned (as shown in Figure 3)；Or the described drop-down grid sharing capacitor regions
Pole insulating barrier 71 is completely removed, passivation layer 73 is thinned (not shown).
It is appreciated that the material of described plate electrode 10 is the one in molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu)
Or multiple combination；The material of described insulating barrier 50,70 is silicon oxide (SiOx), silicon nitride (SiNx) or combination；Institute
The material stating gap electrode 30 is tin indium oxide (Indium Tin Oxide, ITO).
In the array base palte of the present embodiment, due to by one layer of (passivation layer in the drop-down insulating barrier 70 sharing electric capacity C region
Or gate insulator) remove, and remaining film layer (gate insulator or passivation layer) in thinning insulating barrier 70 so that described drop-down
Share the spacing between the battery lead plate 10,30 of electric capacity C to reduce, thus the area of two battery lead plates 10,30 also can be correspondingly arranged relatively
Little, thus increase pixel aperture ratio.
Referring to Fig. 4, the present invention also provides for the manufacture method of a kind of array base palte, and this array base palte can be by following steps system
Formed:
Step 401, form TFT, grid line and data wire on a substrate.
Specifically, the combination of one or more during the material of described TFT, grid line and data wire is Mo, Ti, Al, Cu.
Step 402, on the basis of including described TFT, grid line and data wire formed plate electrode 10.
The material of described plate electrode is the combination of one or more in Mo, Ti, Al, Cu.
Step 403, on the substrate including described plate electrode 10 formed insulating barrier 50, under on described insulating barrier 50
Pulling is enjoyed electric capacity C region and is performed etching, and makes described drop-down insulating barrier 50 thickness sharing electric capacity C region drop-down share less than described
The thickness of the insulating barrier 50 outside electric capacity C region.
Preferably, the material of described insulating barrier 50 is silicon oxide (SiOx), silicon nitride (SiNx) or combination.
Step 404, on the substrate including described insulating barrier 50 formed gap electrode 30, in sub-pixel region, described
Gap electrode 30 and the overlapping region of described plate electrode 10 are described drop-down to share electric capacity C region.
The material of described gap electrode 30 is tin indium oxide (Indium Tin Oxide, ITO).
The manufacture method of array base palte in the present embodiment, drop-down shares the thickness of insulating barrier 50 in electric capacity C region by making
Thinning, reduce the distance between plate electrode 10 and gap electrode 30, therefore also reduce the area of two-plate 10,30, from
And increase pixel aperture ratio.
Further, as it is shown in figure 5, above-mentioned steps 403, on the substrate including described plate electrode 10 formed insulating barrier
50, the drop-down electric capacity C region of sharing on described insulating barrier 50 is performed etching, makes the described drop-down insulation sharing electric capacity C region
Layer 50 thickness include less than the process of the thickness of the described drop-down insulating barrier 50 shared outside electric capacity C region:
Step 4031, on the substrate including described plate electrode 10 depositing insulating layer 50 material；
Step 4032, on the substrate including described insulating barrier 50 material deposit photoresist；
Step 4033, photoresist to insulating barrier via area expose completely, drop-down share electric capacity C region to described
Photoresist carry out halftone exposure；
Step 4034, photoresist is developed, make the photoresist of described insulating barrier via area remove completely, make described
The drop-down photoresist sharing electric capacity C region is thinning；
Step 4035, insulating layer material to described insulating barrier via area perform etching, and form insulating barrier via；
Step 4036, described photoresist is ashed, makes the described drop-down photoresist sharing electric capacity C region move completely
Removing, the described drop-down photoresist shared outside electric capacity C region is thinning；
Step 4037, described drop-down insulating barrier 50 material sharing electric capacity C region is performed etching, make described drop-down share
Insulating barrier 50 thickness in electric capacity C region is less than described drop-down insulating barrier 50 thickness shared outside capacitor regions；
Step 4038, remove remaining photoresist.
Specifically, described plate electrode 10 is pixel electrode, and described gap electrode 30 is public electrode；Or, described plate
Shape electrode 10 is public electrode, and described gap electrode 30 is pixel electrode.
Above-mentioned insulating barrier via connects, in making insulating barrier mistake with lower floor line related for making the gap electrode 30 on upper strata
During hole, exposure is coordinated to form the drop-down photoetching agent pattern sharing electric capacity C region with cineration technics by halftone exposure,
Realize etching the drop-down insulating barrier 50 sharing electric capacity C region while making insulating barrier via, it is not necessary to by single composition
Technique etches the drop-down insulating barrier 50 sharing electric capacity C region.
In an embodiment of the present invention, described insulating barrier 50 includes being cascading a gate insulator 51, at least
One layer of passivation layer 53 and colour cell layer 55 (referring to Fig. 2), and by above-mentioned top by the described drop-down color sharing electric capacity C region
Resistance layer 55 is removed to reduce the spacing between two battery lead plates 10,30.
In an alternative embodiment of the invention, described insulating barrier 70 includes gate insulator 71 and the passivation layer stacked gradually
73, and by said method, the described drop-down passivation layer 73 sharing electric capacity C region is removed and thinning gate insulator completely
71 reduce the spacing (seeing also Fig. 3) between two battery lead plates 10,30；Or by the described drop-down electric capacity C region of sharing
Gate insulator 71 removes completely and thinning passivation layer 73 reduces the spacing between two battery lead plates 10,30.Below in conjunction with Fig. 6,
The drop-down passivation layer 73 sharing electric capacity C region is removed and the concrete operations of thinning gate insulator 71 by Fig. 7 explanation.
See also Fig. 6, Fig. 7, specifically, by a half-tone light shield, the photoresist on insulating barrier is exposed
Light, and half-tone light shield is being just 85% printing opacity to drop-down sharing at capacitance positions C, and other region is light tight so that gold-tinted
After processing procedure, drop-down electric capacity location of C of sharing only remains a small amount of photoresist, and other position photoresist retains, thus shares electric capacity in drop-down
A groove is formed on the photoresist of location of C.Then this photoresist is ashed, thus shares (i.e. groove at electric capacity C by drop-down
Place) photoresist remove completely, the drop-down photoresist shared outside electric capacity C region thinning, then share electric capacity C region to drop-down
Insulating barrier 70 perform etching, until the passivation layer 73 in this region is removed completely, gate insulator 71 is thinned so that should
The drop-down insulating barrier 70 shared at electric capacity location of C only remain thinning after gate insulator 71.
Specifically, the thickness of described photoresist layer is generally 2um, after gold-tinted on this drop-down position sharing electric capacity C
Photoresist residual volume 0.03um, described passivation layer 73 is 0.6um with the thickness summation of gate insulator 71, therefore, this layer of dry corrosion
Etching speed selects than photoresist: SiNx=1:10, described drop-down share photoresist residual volume 0.03um on electric capacity location of C and is etched
Time, cross hole site SiNx and be etched 0.3um, the most drop-down passivation layer 73 sharing electric capacity location of C and gate insulator 71
Just starting to be etched, the most drop-down gate insulator 71 thickness shared at electric capacity location of C is close to 0.3um (i.e. tabular electricity
Spacing d2 between pole 47 and transparency electrode 63 is 0.3um), it is the half of original design scheme 0.6um, according to capacitance equation C
=ε 0 (ε * A/d), the most drop-down electric capacity C area A that shares can be designed as original 50%, the most drop-down electric capacity C area of sharing
50% just can be designed as Pixel ITO pattern, thus increases aperture opening ratio.
The manufacture method of above-mentioned liquid crystal display pixel structure, is patterned into the insulating barrier 70 on plate electrode 10 and only retains
After gate insulator 71 after thinning, then on the gate insulator 71 after this is thinning, form the slit relative with plate electrode 10
Electrode 30；Make to constitute the spacing between drop-down two battery lead plates (described plate electrode 10 and gap electrode 30) sharing electric capacity C
Reducing, this drop-down area sharing electric capacity C also can corresponding reduce, thus increases the aperture opening ratio of pixel, it is possible to energy efficient, fall
Low cost.
The embodiment of the present invention also provides for a kind of liquid crystal indicator, including above-mentioned array base palte.
The concrete structure of this array base palte is same as the previously described embodiments, does not repeats them here.
This liquid crystal indicator is specifically as follows: liquid crystal panel, LCD TV, liquid crystal display, Electronic Paper, digital phase
Frame, mobile phone etc..
Liquid crystal indicator in the present embodiment, drop-down shares the lower thickness of insulating barrier in capacitor regions by making, reduces
Distance between plate electrode and gap electrode, this drop-down area sharing electric capacity C also corresponding can reduce, thus increases picture
The aperture opening ratio of element, it is possible to energy efficient, reduces cost.
In the description of this specification, reference term " embodiment ", " some embodiments ", " example ", " specifically show
Example " or the description of " some examples " etc. means to combine this embodiment or example describes specific features, structure, material or feature
It is contained at least one embodiment or the example of the present invention.In this manual, the schematic representation of above-mentioned term is differed
Surely identical embodiment or example are referred to.And, the specific features of description, structure, material or feature can be any one
Individual or multiple embodiment or example combine in an appropriate manner.
Array base palte provided the embodiment of the present invention above and preparation method thereof and liquid crystal indicator have been carried out in detail
Thin introducing, principle and the embodiment of the present invention are set forth by specific case used herein, saying of above example
Bright method and the core concept thereof being only intended to help to understand the present invention；Simultaneously for one of ordinary skill in the art, foundation
The thought of the present invention, the most all will change, and in sum, this specification content is not
It is interpreted as limitation of the present invention.
Claims (11)
1. an array base palte, including plate electrode, gap electrode and between described plate electrode and described gap electrode
Insulating barrier, and on described array base palte divide each sub-pixel all include main pixel region and sub-pixel region, institute
State sub-pixel region comprises and drop-down share electric capacity, it is characterised in that the described drop-down insulating barrier sharing region corresponding to electric capacity
Thickness is less than the described drop-down thickness of insulating layer shared outside the region that electric capacity is corresponding, wherein, and narrow in described sub-pixel region
Seam electrode and the overlapping region of described plate electrode are described drop-down to share the region that electric capacity is corresponding.
2. array base palte as claimed in claim 1, it is characterised in that described plate electrode is pixel electrode, described slit electricity
Extremely public electrode；Or, described plate electrode is public electrode, and described gap electrode is pixel electrode.
3. array base palte as claimed in claim 1 or 2, it is characterised in that between described plate electrode and described gap electrode
Described insulating barrier include the gate insulator, at least one of which passivation layer and the color blocking layer that are cascading, wherein, described under
Pulling is enjoyed the color blocking layer in region corresponding to electric capacity and is completely removed.
4. array base palte as claimed in claim 1 or 2, it is characterised in that between described plate electrode and described gap electrode
Described insulating barrier include the gate insulator and the passivation layer that are cascading, wherein, described drop-down to share electric capacity corresponding
The passivation layer in region is completely removed, described gate insulator is thinned.
5. array base palte as claimed in claim 1 or 2, it is characterised in that between described plate electrode and described gap electrode
Described insulating barrier include the gate insulator and the passivation layer that are cascading, wherein, described drop-down to share electric capacity corresponding
The gate insulator in region is completely removed, described passivation layer is thinned.
6. a liquid crystal indicator, it is characterised in that include the array base palte as according to any one of claim 1-5.
7. the manufacture method of an array base palte, it is characterised in that including:
Form TFT, grid line and data wire on a substrate；
Plate electrode is formed on the basis of including described TFT, grid line and data wire；
The substrate including described plate electrode is formed insulating barrier, drop-down on described insulating barrier is shared the district that electric capacity is corresponding
Territory performs etching, and drop-down to share electric capacity corresponding less than described to make the described drop-down thickness of insulating layer sharing region corresponding to electric capacity
Thickness of insulating layer outside region；
The substrate including described insulating barrier is formed gap electrode, in the sub-pixel region of described array base palte, described narrow
Seam electrode and the overlapping region of described plate electrode are described drop-down to share the region that electric capacity is corresponding.
The manufacture method of array base palte the most according to claim 7, it is characterised in that described including described plate electrode
Substrate on formed insulating barrier, the drop-down region sharing electric capacity corresponding on described insulating barrier is performed etching, makes described drop-down
Share the thickness of insulating layer in region corresponding to electric capacity less than the described drop-down thickness of insulating layer shared outside the region that electric capacity is corresponding,
Including:
Depositing insulating layer material on the substrate including described plate electrode；
The substrate including described insulating layer material deposits photoresist；
The described photoresist of insulating barrier via area is exposed completely, to the described drop-down institute sharing region corresponding to electric capacity
State photoresist and carry out halftone exposure；
Photoresist is developed, makes the photoresist of described insulating barrier via area remove completely, make described drop-down to share electric capacity
The photoresist in corresponding region is thinning；
The insulating layer material of described insulating barrier via area is performed etching, forms insulating barrier via；
Described photoresist is ashed, makes the described drop-down photoresist sharing region corresponding to electric capacity remove completely, described under
The photoresist that pulling is enjoyed outside the region that electric capacity is corresponding is thinning；
The described drop-down insulating layer material sharing region corresponding to electric capacity is performed etching, makes that described drop-down to share electric capacity corresponding
The thickness of insulating layer in region is less than the described drop-down thickness of insulating layer shared outside the region that electric capacity is corresponding；
Remove remaining photoresist.
The manufacture method of array base palte the most according to claim 8, it is characterised in that described insulating barrier includes stacking gradually
The gate insulator arranged and passivation layer, and the described drop-down described passivation layer sharing region corresponding to electric capacity moved completely
Remove, described gate insulator is thinned.
The manufacture method of array base palte the most according to claim 8, it is characterised in that described insulating barrier includes layer successively
The folded gate insulator arranged and passivation layer, and the described drop-down described gate insulator sharing region corresponding to electric capacity is complete
Entirely remove, described passivation layer is thinned.
The manufacture method of 11. array base paltes according to claim 8, it is characterised in that described insulating barrier includes layer successively
Folded gate insulator, at least one passivation layer and the color blocking layer arranged, and the described drop-down color blocking sharing region corresponding to electric capacity
Layer is completely removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610770008.5A CN106206618A (en) | 2016-08-30 | 2016-08-30 | Array base palte and preparation method thereof and liquid crystal indicator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610770008.5A CN106206618A (en) | 2016-08-30 | 2016-08-30 | Array base palte and preparation method thereof and liquid crystal indicator |
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| CN106206618A true CN106206618A (en) | 2016-12-07 |
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| CN201610770008.5A Pending CN106206618A (en) | 2016-08-30 | 2016-08-30 | Array base palte and preparation method thereof and liquid crystal indicator |
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| WO2020135023A1 (en) * | 2018-12-25 | 2020-07-02 | 惠科股份有限公司 | Display device, array substrate and process method therefor |
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