CN103762239A - Radio-frequency power LDMOS device and manufacturing method thereof - Google Patents
Radio-frequency power LDMOS device and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a radio-frequency power LDMOS device and a manufacturing method of the radio-frequency power LDMOS device. The radio-frequency power LDMOS device comprises a source electrode, a grid electrode, a drain electrode, a silicon type substrate, a P-epi region, a P+sinker region, a P+base region, a gate oxide layer and an LDD region, wherein the LDD region is a drift region. Preferably, the edge of the gate oxide layer is provided with a beak structure and adopts a side wall process. On the condition of meeting the requirement of breakdown voltage, the radio-frequency power LDMOS device obviously reduces on resistance of the drift region and source leakage stray capacitance, evidently optimizes the characters of direct current and radio frequency, and has excellent performance and broad market prospects.
Description
Technical field
The present invention relates to radio-frequency power device and preparation method, more specifically say a kind of RF power LDMOS device and preparation method thereof.
Background technology
Radio-frequency power device is mainly used in the radio-frequency power amplifier of base stations in mobile communication system in wireless telecommunications.But due to the deficiency of CMOS radio-frequency power performance, on radiofrequency power semiconductor market, until the mid-90 in last century, radio-frequency power device is all also to use bipolar transistor or GaAs MOSFET.Until the later stage nineties, the appearance of silicon-based lateral diffusion transistor LDMOS has changed this situation.Compare with bipolar transistor or GaAs MOSFET, LDMOS device have withstand voltage compared with high, high frequency lower linear amplify that dynamic range is large, distortion is little, it is high to gain, power output, the advantage that cost is low, make it surpass the mainstream technology that GaAs power device becomes radio-frequency power MOSFET gradually.
LDMOS device is keeping, on the basis of MOS basic device structure, by horizontal double diffusion technique, forming channel region.At same photoetching window, carry out twice diffusion, an intermediate concentration high-energy boron (B) diffusion, the low-energy arsenic of high concentration (As) diffusion, because boron diffusion ratio arsenic is fast, so can transversely spread fartherly under grid border, form a raceway groove that has concentration gradient.The channel length of LDMOS device is not subject to the impact of lithographic accuracy, and by the control to technique, that channel length can be done is very little, thereby improves mutual conductance and the operating frequency of device.
The low-doped drift region of introducing between drain electrode and raceway groove, has improved the puncture voltage of LDMOS device, has reduced the parasitic capacitance between source-drain electrode, has improved the frequency characteristic of device.By to the length in LDD region and doping content, can adjust conducting resistance and the puncture voltage of device.
The connection of source electrode and substrate has been realized in the P-sinker region of LDMOS, the lead inductance of the source electrode when reducing radio frequency applications, and the RF gain that increases common-source amplifier, improves the performance of device.Because the resistance of source electrode and inductance all can produce negative feedback, reduce the power gain of device.Source electrode is connected and can on domain, saves the wiring of source electrode with the P+ substrate of ground connection simultaneously, so not only can reduce the parasitic parameter bringing due to wiring, can also reduce the area of whole domain, the service behaviour of device after flow is further improved.
Ldmos transistor also has good temperature characterisitic, and its temperature coefficient is negative, and negative feedback makes excessive local current can not form the second breakdown as bipolar device, and safety operation area is wide, Heat stability is good, and reliability is high.
LDMOS semiconductor process techniques towards the radio-frequency power amplifier of mobile telephone base station, is also widely used in HF, VHF and UHF broadcast reflector, digital TV transmitter and microwave and air line transistor except main.In addition, along with the continuous expansion of the LDMOS applying frequency upper limit, more make it carry out on a large scale marching other field, comprise emerging WiMax market, and ISM market.Along with the fast development of ng mobile communication and application more and more widely, RF power LDMOS has very optimistic market prospects.
For adapting to the demand for development of base station, need further to improve the performance of RF power LDMOS, specifically, need higher puncture voltage, higher power output, the same puncture voltage of better high frequency characteristics, particularly conducting resistance, mutual conductance with puncture and cut-off frequency between mutually the relation of restriction need to improve.
Summary of the invention
Object of the present invention comprises provides a kind of RF power LDMOS device, and further, object of the present invention comprises the preparation method that this RF power LDMOS device is also provided.RF power LDMOS device provided by the invention is greater than on the basis of 80V condition meeting puncture voltage, has significantly reduced drift region conducting resistance and source and has leaked parasitic capacitance, has obviously optimized the DC and microwave characteristics of device.
The object of the invention is to be achieved through the following technical solutions: a kind of RF power LDMOS device, comprise source electrode, grid, drain electrode, it is characterized in that, also comprise following structure: silicon type substrate, P-epi region, P+sinker region, P+base region, gate oxide, LDD region, described LDD region is drift region.
In one embodiment, described gate oxide edge has beak structure.
In another embodiment, its preparation comprises side wall technique, and described side wall technological operation, after P+base injects, was carried out before LDD injects.
Preferably, the thickness of described beak structure is about
In another embodiment, also comprise field plate, described field plate be field plate with the connected source field plate of source electrode (Source Field Plate) structure, described source field plate structure extends to drift region top by source metal and covers described drift region and form; Described drift region is to have LDD1 district adjacent one another are and the drift region in LDD2 district, and described LDD2 district is positioned at top, LDD1 district; Described LDD1 district is dark tie region, and LDD2 district is shallow junction region; The described drift region with LDD1 district adjacent one another are and LDD2 district forms by twice injection, the junction depth in LDD1 district approximately 1 μ m wherein, and, by using identical mask plate to carry out described twice injection.
In a preferred embodiment, described silicon type substrate is that doping content is the silicon type substrate of the P+ of 4e17; On it, be described P-epi region, described P-epi region doping concentration is that 1.2e15, thickness are 6 μ m; Described P+sinker region adopts high energy ion implantation B impurity, and high temperature forms after pushing away trap; Described gate oxide thickness is
described grid is formed by polysilicon deposit doping and etching, and etching length is preferably 1 μ m; Described drift region length is 3-5 μ m; The implantation concentration in described LDD1 district is 1e12 to 3e12cm
-2, the implantation concentration in described LDD2 district is 2e11 to 2e12cm
-2; Under described field plate, have oxide layer, its thickness is 0.5-1 μ m; Field plate length is 0-2 μ m; Preferably, described drift region length is 4 μ m, and the implantation concentration in described LDD1 district is 2e12cm
-2, the implantation concentration in described LDD2 district is 1.2e12cm
-2, described field plate length is 1.4-2 μ m.
Technical scheme of the present invention also comprises a kind of preparation method of RF power LDMOS device, and it comprises the following steps:
(1) extension p-epi region on the silicon type substrate of P+;
(2) high energy ion implantation B impurity, high temperature forms P+sinker region after pushing away trap;
(3) form gate oxide;
(4) carry out deposit doping and the etching of polysilicon, form gate electrode (grid);
(5) carry out injection and/or the diffusion in described P+base region, and, the injection of described drift region and/or diffusion;
Further, the preparation method of described RF power LDMOS device is for the preparation of any one above-mentioned RF power LDMOS device.
In one embodiment, after generating, grid also comprises thermal oxidation grid separator plate step, to form beak structure at gate edge.
In another embodiment, after injecting, P+base increases side wall technique, to reduce the diffusion under raceway groove of source electrode and drift region.
Further, above-mentioned steps (5) is further comprising the steps:
(5.1) carry out the injection in the injection of P+base and the described LDD1 district of described drift region;
(5.2) carry out the diffusion in P+base region and the diffusion in LDD1 region simultaneously;
(5.3) after diffusion process, carry out the injection in the described LDD2 district of described drift region.
Wherein, LDD2 district is used identical mask plate with LDD1 district;
And
Source metal covers the field plate of formation source, drift region field plate (Source Field Plate, SFP) structure.
Term explanation
In this article, term " LDMOS " represents Lateral Diffused Metal Oxide Semiconductor FieldEffect Transistor, i.e. transverse diffusion metal oxide semiconductor field effect transistor.
In this article, term " source electrode " and " source electrode " are interchangeable, are called for short in " source " or " Source "; Term " grid " and " gate electrode " are interchangeable, are called for short " grid " or " Gate "; Term " drain electrode " abbreviation " Drain ".
In this article, term " about " or " left and right " are illustrated in the deviation range of allowing in the manufacturing process of this area, or in the error range of relevant parameter (length, thickness, temperature etc.) metering or checkout gear, should be appreciated that, in fact cannot realize completely accurate Numerical Control and/or measurement." approximately " or " left and right " can represent special value (up and down) positive and negative 0.0001%, positive and negative 0.001%, positive and negative 0.01%, positive and negative 0.1%, positive and negative 0.2%, positive and negative 0.5%, positive and negative 1%, positive and negative 2%, positive and negative 5%, positive and negative 8%, positive and negative 10%, positive and negative 15%, positive and negative 20%, positive and negative 30%, positive and negative 50%, the selection of concrete positive and negative scope, determines according to technique known in the art.Under specific circumstances, wider scope is also possible.
The invention has the beneficial effects as follows: well improved the same puncture voltage of conducting resistance, mutual conductance with puncture and cut-off frequency between the relation of restriction mutually, make the device there is good DC and microwave characteristics.More particularly, there is following distinct advantages:
1) at gate edge, form beak structure, and increase side wall technique after P-base injects, reduce source electrode and the diffusion of drift region under raceway groove;
2) use same mask plate to carry out twice injection of drift region, form Yi Geshenjie LDD1 district and shallow junction LDD2 district, optimize output resistance meeting under breakdown condition;
3) adopt SFP(Source Field Plate) field plate, further optimized device drift region doping, improve DC characteristic and reduce parasitic gate leakage capacitance, improve radiofrequency characteristics.
Accompanying drawing explanation
Fig. 1 is twice injection SFP-LDMOS profile
Fig. 2 is the channel region that does not have optimizing process to form
Fig. 3 is side wall processing step
Fig. 4 is for increasing the channel region forming after side wall technique
Fig. 5 is that parasitic gate leakage capacitance Cgd is with the variation of gate oxide thickness Tox
Fig. 6 is the impact of oxidated layer thickness on puncture voltage under field plate
Fig. 7 is the impact of SFP length on drift region Electric Field Distribution
Fig. 8 is different drift regions injection condition and the impact of SFP field plate on puncture voltage
Fig. 9 is different drift regions injection condition and the impact of SFP field plate on source drain capacitance
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, it is exemplary and nonrestrictive should understanding following embodiment, is intended to explanation and explains design of the present invention and spirit.
It is 28V that the present invention is intended to design work voltage, and puncture voltage, higher than the LDMOS device of 80V, meeting under the condition puncturing, reduces output resistance and parasitic capacitance, to improve power output and the high frequency characteristics of device.Therefore, emphasis of the present invention has carried out the parameter optimization of channel region, notch cuttype drift region and SFP field plate.
The RF LDMOS structure of LDMOS device in the present invention based on traditional, and made on this basis some corrective measure, puncture voltage and conducting resistance with optimised devices, reach designing requirement.Main corrective measure comprises: 1) twice injection carried out in drift region, once form the LDD1 region of junction depth approximately 1.0 μ m, what once form in addition is shallow junction LDD2 region, and identical mask plate is used in twice injection; 2) adopt source field plate (SFP) structure, source electrode is extended to top, drift region.
LDMOS device concrete structure of the present invention is as shown in Figure 1: LDMOS is produced on the silicon type substrate of P+, extension p-epi region in the above, and high energy ion implantation B impurity then, high temperature forms P+sinker region after pushing away trap.Gate oxide is designed to 400A, makes the maximum grid voltage that device can bear higher than 12V, carry out afterwards deposit doping and the etching formation gate electrode of polysilicon.Next carry out the injection of the injection of P+base and the LDD1 of drift region.After the injection of P+base, do not carry out at once diffusion process and form channel region, the diffusion in the diffusion in P+base region and LDD1 region is carried out simultaneously.The junction depth in LDD1 district is deeply more a lot of than the conventional Drift district degree of depth (0.3 μ m), and the Electric Field Distribution that darker junction depth is conducive to optimize drift region improves the puncture voltage of device, and optimizes conducting resistance.After diffusion process, carry out the injection in LDD2 region, identical mask plate is used with LDD1 region in LDD2 region.Finally, source metal covers drift region and forms SFP structure field plate.
Embodiment 1
Channel region optimal design
One, grid oxygen optimal design
It is the important parameter of weighing this device amplifying power that LDMOS device is operated in saturation region mutual conductance.Its computing formula is:
It is the frequency of 1 o'clock that cut-off frequency is defined as short-circuit current gain, is the important radio frequency parameter of device, and computing formula is as follows:
From seeing two formula above, at the thickness of the gate oxide of LDMOS, be the most important factor that determines device mutual conductance and cut-off frequency.Adopt gate oxide thinner, Cox is larger, can bring the increase of device mutual conductance gm, but can also can increase grid leak parasitic capacitance Cgd and gate-source parasitic capacitance Cgs when gate oxide attenuate, affects the high frequency characteristics of device.Due to gate oxide attenuation, the electric field at grid edge is piled up more serious simultaneously, and puncture voltage reduces.Visible mutual conductance and cut-off frequency, puncture voltage are contradiction to the requirement of gate oxide thickness.
Contradiction gate oxide thickness being required for alleviating mutual conductance and cut-off frequency, puncture voltage, the LDMOS device in the present invention, after polysilicon gate deposit forms, the heat layer of oxide layer dividing plate of having grown, as shown in Figure 2.By growth thermal oxide layer dividing plate, at the sidewall of polysilicon, also formed oxide layer, therefore can reduce the overlapping of Shan Yu LDD district; In addition, in the marginal portion of grid, form beak structure, above not affecting raceway groove, in oxidated layer thickness, reduce parasitic grid source, gate leakage capacitance like this, thereby can reduce the contradiction of mutual conductance and cut-off frequency.
In simulation process, find, directly utilize the autoregistration of polysilicon, carry out after the injection of P-base and the injection of N-LDD, after a series of high-temperature diffusion process, drift region and source region impurity are all diffused into the region of the thin grid oxygen in grid below, and this will weaken the effect of gate oxide dividing plate.For this situation, need to again improve technological measure, after P-base injects, increase side wall technique, then carry out LDD injection, as shown in Figure 3.
By increasing after the side wall technique with CMOS process compatible, result as shown in Figure 4, can find, side wall technique can obviously be alleviated source region and the diffusion of drift region impurity below raceway groove, forms more satisfactory channel region.
Simulation increases before and after gate oxide dividing plate and side wall technique, and parasitic gate leakage capacitance Cgd is with the change curve of grid oxide layer thickness, as shown in Figure 5.
By simulation is found, process modification can obviously reduce the parasitic gate leakage capacitance of device.In addition, when gate oxide thickness increase can obviously reduce parasitic grid leak, but work as gate oxide thickness, be increased to a certain degree, referring to Fig. 5, after about 400A, parasitic capacitance reduces with the variation of gate oxide thickness.
Consider the requirement of cut-off frequency and mutual conductance, selecting grid oxide layer thickness is 400A, and the beak structural thickness forming at grid oxygen edge is about 1000A.By gate oxide dividing plate and side wall technique, source region and the drift region border below raceway groove has all obtained very large optimization, reduced the overlapping of grid homologous region and drift region, the beak structure at grid edge has also reduced grid leak, gate-source parasitic capacitance greatly, has improved the high frequency characteristics of device.
Two, raceway groove concentration optimization
The channel region of LDMOS device diffuses to form after injecting this twice injection by the injection of P-base district and source region, and its concentration is mainly that the concentration being diffused under raceway groove by P-base determines.The concentration in device channel region is the key factor that affects device grid-control ability.Raceway groove diffusion impurity concentration Nch, has determined the cut-in voltage of LDMOS pipe, sees formula:
Cut-in voltage and operating current that increasing LDMOS pipe needs according to device real work regulate.Shown that respectively simulation P-base is injecting the variation with P-base implantation concentration of the cut-in voltage of metering device while being respectively 6e12,8e12,1e13,2e13,3e13cm-2, mutual conductance.
By analog result, can learn, P-base implantation concentration is linear on the impact of cut-in voltage, and implantation concentration is larger, and the applied gate voltage that need to reach surperficial strong inversion needs is also higher.Simultaneously mutual conductance reduces along with the increase of input P-base concentration, this be because, when raceway groove concentration increases, cut-in voltage rises, and under same grid voltage, the electric charge that attracts raceway groove to form inversion layer also just reduces relatively, press C=dQ/dV and calculate, capacitance has also just diminished, and mutual conductance has reduced.Therefore, the doping of P raceway groove is risen cut-in voltage, and mutual conductance declines, and power output reduces.Consider the requirement of cut-in voltage and power output, the preferred P-base implantation concentration of LDMOS device architecture of the present invention's design is 1e13cm-2, and LDMOS cut-in voltage is 2V left and right.
Embodiment 2
Drift region design optimization
Research of the present invention is found: the withstand voltage and conducting resistance of LDMOS device is contradiction to the requirement of the concentration of drift region and thickness.High puncture voltage requires light dope, dark diffusion, long drift region, and low on-resistance requires heavy doping, shallow diffusion, short drift region.LDMOS device in the present invention can provide under the prerequisite that meets puncture voltage requirement in drift length design, and emphasis injects and is optimized for drift region doping.The way of twice injection is taked in the drift region of LDMOS of the present invention, forms LDD1 district and the surperficial heavily doped LDD2 region of dark knot, and twice injection adopts identical mask plate, lower mask body discussion LDMOS drift region design process.
One, drift region Design of length
Drift region length is one of principal element affecting device withstand voltage characteristic.LDMOS device in the present invention is mainly considered the requirement of device electric breakdown strength to the design of drift region length, therefore utilize TCAD software simulation drift region doping content be 2E16cm
-3, 4E16cm
-3, 8E16cm
-3, 1E17cm
-3time, drift region length is respectively in the situation of 3um, 4um, 5um, the puncture voltage of LDMOS under the off state of Vg=0V changes.
Result shows, along with the increase of drift region length, puncture voltage improves, and under the condition of identical drift region length, puncture voltage reduces along with the increase of drift region doping content.Drift region length increases, and doping content reduces to be conducive to raising and punctures.When the doping content of drift region excessive, can cause again puncture voltage and drift region length there is no too large relation, this is mainly to occur in drift region near the part of grid end because puncture, drift zone resistance is too small, drain voltage has mainly been concentrated on the PN junction that drift region contacts with raceway groove, puncture with drift region length and had nothing to do.The preferred drift region of the present invention length is 4um.Ensuing research contents is mainly to reduce drift zone resistance meeting under the condition of puncture voltage, increases the power output of device.
Two, the twice doping optimization in drift region
Traditional LDMOS drift region design is meeting under the condition of RESURF principle, is mainly to adopt a low concentration doping to inject P, and device can be exhausted completely whole drift region before puncturing, and reaches the object that improves puncture voltage.LDMOS device application of the present invention is in radio-frequency power field, and the requirement of puncture voltage can meet by drift region length parameter substantially, and the more important thing is on this basis conducting resistance is optimized, and reduces conducting resistance and increases power output.
Twice injection in drift region that the present invention adopts drift region design, once high-octane p type impurity injects and diffuses to form dark knot LDD1 region, once the shallow surface that is infused in drift region of low-yield p type impurity forms LDD2 region, and twice injection adopts identical mask plate.
First the injection metering of LDD1 is simulated the impact of puncture voltage, result demonstration, when the P concentration of injecting is 2e12cm-2, puncture voltage is maximum, and LDD1 district doping content is excessive or too small breakdown characteristics all can be degenerated, and this meets RESURF principle.When LDD region is by once injecting and form, optimize while reaching large puncture voltage, then LDD2 implantation concentration is simulated.The injection of LDD2 selects concentration to be respectively 2e11,4e11,6e11,8e11,1e12,2e12, and LDD1 implantation concentration is fixed as 2e12cm-2.
Result shows: the difference of injecting along with LDD2, implantation concentration at 2e11 in the process of 6e11, the puncture voltage of LDMOS device remains on original basis substantially, when LDD2 implantation concentration continues to increase again, puncture voltage significantly declines.
This shows, when first carry out after the injection and diffusion in LDD1 region drift region, this a part of concentration has determined the breakdown characteristics of device, and because this part degree of depth is darker, device is reduced the doping content susceptibility on surface, drift region, for the injection in LDD2 region, at 2e11, to this section of device electric breakdown strength of 6e11, relatively remain unchanged, more than maintaining 90V, and the conducting resistance of device is injected obviously and is declined with LDD2.
Comparative device is respectively 6e11 and 2e12 in LDD2 region implanted dopant concentration, Potential Distributing when puncturing, result shows: for LDD2 region, when doped in concentrations profiled concentration is moderate, drift region Electric Field Distribution is even, and when doping content is too high, drain electric concentrates on drift region near area of grid, and puncture in advance in this region, cause the degeneration of breakdown characteristic of device.In addition, drift region implanted dopant concentration also can exert an influence to the parasitic gate leakage capacitance of device, and when drift region doping content increases, the gate leakage capacitance of device increases thereupon.
The design in LDD2 region has brought the very big optimization of break-over of device resistance, but doping content is too high, also can cause drift region to puncture in advance near area of grid the unfavorable effect increasing with parasitic gate leakage capacitance, next embodiment, by LDMOS is added to source field plate, continues LDMOS device to be optimized design.
Embodiment 3
SFP field plate is optimized
The formation of SFP plate is when etching metal formation source electrode contacts with drain metal, thereby source plates is elongated to top, drift region, forms field plate.When adding SPF field plate above LDMOS device drift region when, because field plate is 0 with the connected electromotive force of source electrode, can find that drift region will be offset toward drain directions under the effect of field plate near drain region electric field line, so SFP field plate has the drift region of optimization near area of grid electric field action.The research of injecting by 2 pairs of drift region doping of embodiment, find in the time of the implanted dopant excessive concentration of LDD2 region, puncture and occur in just drift region near the region of grid, and research of the present invention is surprisingly found out that, can utilize SFP field plate to improve the doping on surface, drift region, therefore the present embodiment, in conjunction with field plate, is further optimized LDMOS device.
One, the optimization of oxidated layer thickness under SFP field plate
As shown in Figure 6, change the thickness of thick grid oxygen under SFP field plate, by research, find, when gate oxide thickness declines, the drift region concentration that breakdown point is corresponding increases.Under field plate, oxide layer attenuate can strengthen silicon face under field plate and exhausts, when the length that can see field plate is 1.5um, when the thickness of thick grid oxygen is from 0.9 μ m is reduced to 0.5 μ m, 2.4e12cm-2 can be brought up to from 1.9e12cm-2 in drift region corresponding to the highest breakdown point altogether implantation concentration.
Two, SFP field plate length optimization
Utilize ISE software under drift region doping content LDD1 region doping 2e12, LDD2 district As doping content 8e11,1e12,1.2e12,1.4e12,1.6e12 condition, different SFP length is simulated.As LDD1 district, device drift region doping 2e12, during LDD2 region doping 1.4e12, drift region Electric Field Distribution is as shown in Figure 7 when device breakdown to simulate different SFP plate length.
As can be seen from Figure 7, the electrostatic screen effect of SFP field plate has weakened grid below electric field greatly, has eliminated peak electric field excessive due to doping content and that produce below grid, has optimized the breakdown characteristics of the too high device causing of LDD2 region doping and has degenerated.But along with field plate length constantly increases, drift region constantly reduces near gate terminal peak surface electric field, the electric field of drift region and drain electrode handover region constantly increases, and device breakdown point now moves to drift region near the region of drain electrode.Particularly, when field plate length is greater than 2 μ m, drift region punctures in advance with drain electrode PN junction, has caused the degeneration of puncture voltage.
By the sunykatuib analysis to SFP field plate, the present invention finds, after adding field plate, the grid place that can effectively suppress to cause because LDD2 doping content is too high punctures in advance, be puncture voltage for the Reduced susceptibility of drift region doping content, therefore, selecting oxidated layer thickness under SFP field plate is 0.5 μ m, field plate length is under the condition of 1.6 μ m, again drift region is injected and is optimized.Simulation obtains breakdown characteristic of device curve as shown in Figure 8.
As seen from Figure 8, adding of SFP field plate, the puncture voltage device of LDMOS although do not increase significantly, add after field plate and puncture from 92V and brought up to 95V, but due to its electric Field Optimization effect to area of grid, the puncture voltage of LDMOS is declined to the injection susceptibility of drift region LDD2 part, can see, the doping content that breakdown point is corresponding has been brought up to 3.2e12cm-2 from 2e12cm-2.Therefore can under the requirement of same puncture voltage, improve the doping content of drift region, reach the object of optimizing conducting resistance.
The present invention has also studied the impact of SFP field plate on gate leakage capacitance, referring to Fig. 9, adopt and inject drift region twice, surface impurity concentration increases, under identical injection condition, than once injecting the drift region grid leak parasitic capacitance forming, increase, but add under the identical injection metering of being introduced in of SFP plate condition, reduced gate leakage capacitance, thereby can, when reducing break-over of device resistance, optimize the high frequency characteristics of device.
Embodiment 4
The preferred LDMOS design of the present invention
Shown in Fig. 1: LDMOS is produced on the silicon type substrate of P+ that doping content is 4e17, and epi dopant concentration is that 1.2e15, thickness are the p-epi region of 6 μ m in the above, high energy ion implantation B impurity then, high temperature forms P+sinker region after pushing away trap.Gate oxide is designed to 400A, makes the maximum grid voltage that device can bear carry out afterwards deposit doping and the etching formation gate electrode of polysilicon higher than 12V, and etching electrode length is 1 μ m.Next carry out the injection of the injection of P+base and the LDD1 of drift region.After the injection of P+base, do not carry out at once diffusion process and form channel region, in simulation process, adopt the diffusion in the diffusion in P+base region and LDD1 region is carried out simultaneously, choose suitable parameter and can obtain suitable channel doping concentration and the degree of depth in LDD1 region.The about 1um of junction depth in LDD1 district, is about 0.3 μ m than the conventional Drift district degree of depth deeply a lot, and the Electric Field Distribution that darker junction depth is conducive to optimize drift region improves the puncture voltage of device, and optimizes conducting resistance.After diffusion process, carry out the injection in LDD2 region, identical mask plate is used with LDD1 region in LDD2 region, and the impurity of this part mainly concentrates on surface, drift region, and Main Function is for reducing conducting resistance.Finally, source metal covers drift region and forms SFP structure field plate, to optimize drift region near the electric field of area of grid.
The particularly preferred LDMOS device parameters of the present invention is as shown in table 1.
Table 1LDMOS preferred parameter
| Outer layer doping concentration (cm -3） | 1.2e15 |
| Substrate doping (cm -3） | 4e17 |
| Epitaxy layer thickness (μ m) | 6 |
| The long L(μ of grid m) | 1 |
| Grid oxide layer thickness t ox1(A) | 400 |
| Drift region length L DD(μ m) | 4 |
| The drift region LDD1 degree of depth | 1 |
| Drift region LDD1 implantation concentration (cm -2） | 2e12 |
| Drift region LDD2 implantation concentration (cm -2） | 1.2e12 |
| Sinker layer doping content (cm -3） | 1.7e19 |
| Channel region implantation concentration (cm -2） | 1e13 |
| SFP field plate length (μ m) | 1.6 |
| Oxidated layer thickness under SFP field plate (μ m) | 0.5 |
All scopes disclosed by the invention are inclusives and capable of being combined.Although described the present invention with reference to one or more preferred embodiments, it will be understood by those skilled in the art that it is feasible carrying out multiple variation/variant, and key element can be replaced by its equivalent and not deviated from scope of the present invention.In addition, concrete situation or material can be applicable to instruction of the present invention and make many variations, and not deviate from its base region.Therefore, should not limit the invention to as the disclosed specific embodiments of preferred implementation of implementing the present invention, the present invention will comprise all whole embodiments that fall into claims scope.
Claims (10)
1. a RF power LDMOS device, comprises source electrode, grid, drain electrode, it is characterized in that, also comprises following structure: silicon type substrate, and P-epi region, P+sinker region, P+base region, gate oxide, LDD region, described LDD region is drift region.
2. RF power LDMOS device as claimed in claim 1, is characterized in that, described gate oxide edge has beak structure.
3. RF power LDMOS device as claimed in claim 1 or 2, is characterized in that, its preparation comprises side wall technique, and described side wall technological operation, after P+base injects, was carried out before LDD injects.
4. RF power LDMOS device as claimed in claim 2 or claim 3, is characterized in that, the thickness of described beak structure is about
5. as RF power LDMOS device in any one of the preceding claims wherein, it is characterized in that, also comprise field plate, described field plate be field plate with the connected source field plate of source electrode (Source Field Plate) structure, described source field plate structure extends to drift region top by source metal and covers described drift region and form; Described drift region is to have LDD1 district adjacent one another are and the drift region in LDD2 district, and described LDD2 district is positioned at top, LDD1 district; Described LDD1 district is dark tie region, and LDD2 district is shallow junction region; The described drift region with LDD1 district adjacent one another are and LDD2 district forms by twice injection, the junction depth in LDD1 district approximately 1 μ m wherein, and, by using identical mask plate to carry out described twice injection.
6. as RF power LDMOS device in any one of the preceding claims wherein, it is characterized in that, described silicon type substrate is that doping content is the silicon type substrate of the P+ of 4e17; On it, be described P-epi region, described P-epi region doping concentration is that 1.2e15, thickness are 6 μ m; Described P+sinker region adopts high energy ion implantation B impurity, and high temperature forms after pushing away trap; Described gate oxide thickness is
described grid is formed by polysilicon deposit doping and etching, and etching length is preferably 1 μ m; Described drift region length is 3-5 μ m; The implantation concentration in described LDD1 district is 1e12 to 3e12cm
-2, the implantation concentration in described LDD2 district is 2e11 to 2e12cm
-2; Under described field plate, have oxide layer, its thickness is 0.5-1 μ m; Field plate length is 0-2 μ m; Preferably, described drift region length is 4 μ m, and the implantation concentration in described LDD1 district is 2e12cm
-2, the implantation concentration in described LDD2 district is 1.2e12cm
-2, described field plate length is 1.4-2 μ m.
7. a preparation method for RF power LDMOS device, is characterized in that, comprises the following steps:
(1) extension p-epi region on the silicon type substrate of P+;
(2) high energy ion implantation B impurity, high temperature forms P+sinker region after pushing away trap;
(3) form gate oxide;
(4) carry out deposit doping and the etching of polysilicon, form gate electrode (grid);
(5) carry out injection and/or the diffusion in described P+base region, and, the injection of described drift region and/or diffusion;
Preferably, the preparation method of described RF power LDMOS device is for the preparation of the RF power LDMOS device as described in claim 1-6 any one.
8. the preparation method of RF power LDMOS device as claimed in claim 7, is characterized in that, after grid generates, also comprises thermal oxidation grid separator plate step, to form beak structure at gate edge.
9. the preparation method of RF power LDMOS device as claimed in claim 7 or 8, is characterized in that, increases side wall technique, to reduce the diffusion under raceway groove of source electrode and drift region after P+base injects.
10. the preparation method of the RF power LDMOS device as described in claim 7-9 any one, is characterized in that, described step (5) is further comprising the steps:
(5.1) carry out the injection in the injection of P+base and the described LDD1 district of described drift region;
(5.2) carry out the diffusion in P+base region and the diffusion in LDD1 region simultaneously;
(5.3) after diffusion process, carry out the injection in the described LDD2 district of described drift region.
Wherein, LDD2 district is used identical mask plate with LDD1 district;
And
Source metal covers the field plate of formation source, drift region field plate (Source Field Plate, SFP) structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104241377A (en) * | 2014-09-10 | 2014-12-24 | 上海联星电子有限公司 | Radio frequency LDMOS device and preparing method thereof |
| CN106298531A (en) * | 2015-06-03 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of rf-ldmos quasiconductor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104241377A (en) * | 2014-09-10 | 2014-12-24 | 上海联星电子有限公司 | Radio frequency LDMOS device and preparing method thereof |
| CN106298531A (en) * | 2015-06-03 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of rf-ldmos quasiconductor |
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