CN103050537A - Radio frequency lateral double-diffused field effect transistor and manufacturing method thereof - Google Patents
Radio frequency lateral double-diffused field effect transistor and manufacturing method thereof Download PDFInfo
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- CN103050537A CN103050537A CN2012105299082A CN201210529908A CN103050537A CN 103050537 A CN103050537 A CN 103050537A CN 2012105299082 A CN2012105299082 A CN 2012105299082A CN 201210529908 A CN201210529908 A CN 201210529908A CN 103050537 A CN103050537 A CN 103050537A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000005669 field effect Effects 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 230000009977 dual effect Effects 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Abstract
The invention discloses a radio frequency lateral double-diffused field effect transistor, which comprises P-type substrates. P-type epitaxial layers respectively grow on the P-type substrates; lightly doped drift regions are respectively formed in the P-type epitaxial layers; a first layer Faraday shield and a second layer Faraday shield are arranged above each P-type epitaxial layer; and each first layer Faraday shields and each second layer Faraday shield are respectively a polycrystalline silicon Faraday shield. According to the radio frequency lateral double-diffused field effect transistor disclosed by the invention, the grid-leak capacitance Cgd of a device can be effectively reduced, and therefore, the radio-frequency performance of the device is improved. The invention also discloses a manufacturing method for the transistor.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit and make device, particularly relate to a kind of radio frequency horizontal dual pervasion field effect transistor, the invention still further relates to this transistorized manufacture method.
Background technology
Radio frequency horizontal dual pervasion field effect transistor (RFLDMOS) device is the solid microwave power semiconductor product of the New Generation of Integrated that forms of semiconductor integrated circuit technology and microwave electron technological incorporation, has the linearity good, gain high, withstand voltage height, power output is large, Heat stability is good, efficient is high, the Broadband Matching performance is good, be easy to and the advantage such as MOS technique is integrated, and its price is far below GaAs device, it is a kind of very competitive power device, be widely used in GSM, PCS, the power amplifier of W-CDMA base station, and the aspects such as radio broadcasting and nulcear magnetic resonance (NMR).
The puncture voltage BV of RFLDMOS device, conducting resistance Rdson, gate leakage capacitance Cgd, grid source capacitor C gs and drain-source capacitor C ds etc. are the important parameters of weighing device performance.Wherein, the radio-frequency performance of gate leakage capacitance Cgd, grid source capacitor C gs and drain-source capacitor C ds and device is closely related, and directly has influence on the characteristics such as the power output of device and gain.Power output and gain that lower gate leakage capacitance Cgd, grid source capacitor C gs and drain-source capacitor C ds help to improve device.General RFLDMOS pipe adopts faraday's shield (G-shield) structure of double layer of metal, still in order to improve the puncture voltage BV of device, also is not in order to reduce the parasitic capacitance of device simultaneously.As shown in Figure 1, the substrate of high concentration p type impurity is mixed in employing, it is P type substrate 11, requirement according to device withstand voltage is different, on described P type substrate 11, the P type epitaxial loayer 12 of growth different-thickness and doping content by the photolithography plate definition, carries out Implantation and forms light dope drift region (NLDD) 13; With after heat oxide growth one deck grid oxic horizon 14; Depositing polysilicon adopts the photolithography plate definition and etches polysilicon gate 15; Utilize Implantation and diffusion technology to form respectively P trap 16, P+ zone 17, N+ source region 18 and N+ drain region 19; Then deposit layer of silicon dioxide layer 110, depositing metal or metal silicide, etch ground floor faraday shield 111, again deposit layer of silicon dioxide layer 110, depositing metal or metal silicide, etch second layer faraday shield 112, then define P type polysilicon plug or metal plug structure 113, and the deposit respective material; Carry out at last subsequent technique, form RFLDMOS.But want further to improve the radiofrequency characteristics of device, just need to reduce better its parasitic capacitance, as in circuit, having the gate leakage capacitance Cgd of feedback effect.
Summary of the invention
Technical problem to be solved by this invention provides a kind of radio frequency horizontal dual pervasion field effect transistor, can effectively reduce the gate leakage capacitance Cgd of device, thereby improves the radio-frequency performance of device.
For solving the problems of the technologies described above, a kind of radio frequency horizontal dual pervasion field effect transistor provided by the invention, comprise P type substrate, at described P type Grown P type epitaxial loayer, in described P type epitaxial loayer, form the light dope drift region, be provided with ground floor faraday shield and second layer faraday shield above described P type epitaxial loayer, described ground floor faraday shield and second layer faraday shield are polysilicon faraday shield.
Further, also comprise the grid oxic horizon and the polysilicon gate that are positioned at described P type epitaxial loayer top, be arranged in the P trap, P+ zone, N+ source region and the N+ drain region that utilize Implantation and diffusion technology to form respectively of described P type epitaxial loayer, and P type polysilicon plug or metal plug structure.
Further, to be in the partial-length directly over the described polysilicon gate be the 0.1-0.3 micron to described ground floor faraday shield.
Further, to be in the partial-length directly over the described polysilicon gate be the 0-0.3 micron to described second layer faraday shield.
A kind of as claimed in claim 1 transistorized manufacture method comprises:
The formation of step 2, P trap;
The formation in step 3, P+ zone, N+ source region and N+ drain region;
The formation of step 5, P type polysilicon plug or metal plug structure.
Further, carry out the N-type Implantation of the light dope LDD of a step higher-energy in the step 1, ion is phosphorus or arsenic, and energy is 50-300keV, and dosage is 5e
11-4e
12Cm
-2
Further, the trap of P described in the step 2 be formed with dual mode, a kind of is to form by injecting to advance with high temperature before polysilicon gate forms, another kind is to increase temperature to advance by self-registered technology to form.
Further, described P trap, ion are boron, and energy is 30-80keV, and dosage is 1e
12-1e
14Cm
-2
Further, the formation in the source region of N+ described in the step 3 and N+ drain region, ion is phosphorus or arsenic, and energy is 0-200keV, and dosage is 1e
13-1e
16Cm
-The formation in 2 described P+ zones, ion are boron or boron difluoride, and energy is 0-100keV, and dosage is 1e
13-1e
16Cm
-2
Further, the faraday of ground floor described in the step 4 shield, its length is the 0.5-1.5 micron, and thickness is 800-2500A, and impurity is phosphorus or arsenic, and doping content is 5e
18-1e
20Cm
-3Described second layer faraday shield, its length is the 1.5-2.5 micron, and thickness is 800-2500A, and impurity is phosphorus or arsenic, and doping content is 5e
18-1e
20Cm
-3
RFLDMOS device of the present invention by replacing metal to consist of G-shield with heavily doped polycrystalline silicon material, can reduce the gate leakage capacitance Cgd of device effectively, thereby improves the radio-frequency performance of device.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of existing RFLDMOS device;
Fig. 2 is RFLDMOS device architecture schematic diagram of the present invention;
Fig. 3 a is the ionization by collision schematic diagram of existing RFLDMOS device when puncturing;
Fig. 3 b is the ionization by collision schematic diagram of RFLDMOS device of the present invention when puncturing;
Fig. 4 is that RFLDMOS device of the present invention and existing RFLDMOS device are along the transverse electric field intensity distribution in NLDD zone;
Fig. 5 is the corresponding gate leakage capacitance curve comparison of RFLDMOS device of the present invention drain terminal voltages different from existing RFLDMOS device figure;
Fig. 6 is that the gate leakage capacitance of RFLDMOS device of the present invention is compared the percentage schematic diagram that reduces with existing RFLDMOS device under the different drain terminal voltage;
Fig. 7 a-7e is each step structural representation of RFLDMOS device making method of the present invention.
Main description of reference numerals:
P type substrate 11 P type epitaxial loayers 12
Light dope drift region 13 grid oxic horizons 14
Polysilicon gate 15 P traps 16
17 N+ source regions 18, P+ zone
N+ drain region 19 silicon dioxide layers 110
Ground floor faraday shield 111 second layer faraday shields 112
P type polysilicon plug or metal plug structure 113
P type substrate 21 P type epitaxial loayers 22
Light dope drift region 23 grid oxic horizons 24
Polysilicon gate 25 P traps 26
27 N+ source regions 28, P+ zone
N+ drain region 29 silicon dioxide layers 210
Ground floor faraday shield 211 second layer faraday shields 212
P type polysilicon plug or metal plug structure 213
P type substrate 71 P type epitaxial loayers 72
Grid oxic horizon 73 polysilicon gates 74
Light dope drift region 75 P traps 76
77 N+ source regions 78, P+ zone
N+ drain region 79 silicon dioxide layers 710
Ground floor faraday shield 711 second layer faraday shields 712
P type polysilicon plug or metal plug structure 713 photoresists 700
Embodiment
Understand and understanding for your auditor can be had further purpose of the present invention, feature and effect, below cooperate accompanying drawing to describe in detail as after.
As shown in Figure 2, be the structure of RFLDMOS device of the present invention, be included on the described P type substrate 21, the P type epitaxial loayer 22 of growth different-thickness and doping content; With after heat oxide growth one deck grid oxic horizon 24; Depositing polysilicon, the photolithography plate definition also etches polysilicon gate 25; By from inject forming light dope drift region (NLDD) 23; Utilize Implantation and diffusion technology to form respectively P trap 26, P+ zone 27, N+ source region 28 and N+ drain region 29; Then deposit layer of silicon dioxide layer 210, the heavily doped polysilicon of deposit one deck, etch ground floor faraday shield 211, again deposit layer of silicon dioxide layer 210, the heavily doped polysilicon of deposit, etch second layer faraday shield 212, then define P type polysilicon plug or metal plug structure 213, and the deposit respective material; Carry out at last subsequent technique, form RFLDMOS.Wherein to be in the partial-length directly over the polysilicon gate 25 be the 0.1-0.3 micron to ground floor faraday shield 211, and the partial-length that second layer faraday shield 212 is in directly over the polysilicon gate 25 is the 0-0.3 micron.The present invention is by replacing metal material to consist of faraday's shield with heavily doped polysilicon, in the situation that it is constant to guarantee that puncture voltage BV and other Static Electro are learned characteristic, can effectively reduce the gate leakage capacitance Cgd of device, thereby improve the radio-frequency performance of device, improve output gain and the efficient of device.This mainly is because the gate leakage capacitance Cgd of device is equivalent to a mos capacitance (MOS capacitor), for mos capacitance, there is work function difference between the metal on insulating barrier both sides and the semiconductor, thereby cause contact potential difference occurring between metal and the semiconductor, cause the flatband capacitanse C of C-V curve
FBSkew.And adopting heavily doped polysilicon to replace metal, the work function of polysilicon is different from the work function of metal, thereby it is different from contact potential difference between the semiconductor with the contact potential difference that occurs between metal and the semiconductor, makes flatband capacitanse C
FBWith respect to metal, larger to the reciprocal side-play amount of drain terminal voltage VD, thus causing in the situation of identical drain terminal voltage, resulting gate leakage capacitance Cgd is less.Wherein the C-V curve is in the situation that characteristic frequency, the curve of the corresponding gate leakage capacitance Cgd of different drain terminal voltages.
Shown in Fig. 3 a, 3b, be respectively existing RFLDMOS device and RFLDMOS device of the present invention ionization by collision schematic diagram when puncturing, contrasting above-mentioned two width of cloth accompanying drawings can find, its ionization by collision does not have significant change; In conjunction with shown in Figure 4, existing RFLDMOS device and RFLDMOS device of the present invention are almost completely consistent along the transverse electric field distribution in NLDD zone, corresponding area is also almost identical, and namely existing RFLDMOS device and RFLDMOS device of the present invention have almost identical puncture voltage BV.
As shown in Figure 5, RFLDMOS device of the present invention and existing RFLDMOS device are in the situation that frequency is 1MHz, the corresponding gate leakage capacitance curve C of different drain terminal voltage VD gd comparison diagram, wherein curve a representative has the RFLDMOS device now, curve b represents RFLDMOS device of the present invention, as seen from the figure, curve b has lower gate leakage capacitance Cgd, and namely RFLDMOS device of the present invention has lower gate leakage capacitance Cgd.
As shown in Figure 6, under the different drain terminal voltage, the gate leakage capacitance Cgd of RFLDMOS device of the present invention compares the percentage schematic diagram that reduces with existing RFLDMOS device, as seen from the figure, under most drain terminal voltage VD, electric capacity of the present invention all than the low 30%-40% of the latter, has better radio-frequency performance.
The manufacture method of RFLDMOS device of the present invention shown in Fig. 7 a-7e, comprising:
The formation of step 2, P trap 76 can have dual mode, and a kind of is to form by injecting with the high temperature propelling before polysilicon gate 74 forms, and another kind is to increase temperature to advance by self-registered technology to form.Its impurity is boron, and energy is 30-80keV, and dosage is 1e
12-1e
14Cm
-2, shown in Fig. 7 b.
The formation in step 3, P+ zone 77, N+ source region 78 and N+ drain region 79 is specially the zone that goes out N+ and P+ by lithographic definition, injects the N+ of source drain terminal, and impurity is phosphorus or arsenic, and energy is 0-200keV, and dosage is 1e
13-1e
16Cm
-2When injecting P+, impurity is boron or boron difluoride, and energy is 0-100keV, and dosage is 1e
13-1e
16Cm
-2, shown in Fig. 7 c.
Abovely by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. radio frequency horizontal dual pervasion field effect transistor, comprise P type substrate, at described P type Grown P type epitaxial loayer, in described P type epitaxial loayer, form the light dope drift region, above described P type epitaxial loayer, be provided with ground floor faraday shield and second layer faraday shield, it is characterized in that, described ground floor faraday shield and second layer faraday shield are polysilicon faraday shield.
2. radio frequency horizontal dual pervasion field effect transistor as claimed in claim 1, it is characterized in that, also comprise the grid oxic horizon and the polysilicon gate that are positioned at described P type epitaxial loayer top, be arranged in the P trap, P+ zone, N+ source region and the N+ drain region that utilize Implantation and diffusion technology to form respectively of described P type epitaxial loayer, and P type polysilicon plug or metal plug structure.
3. radio frequency horizontal dual pervasion field effect transistor as claimed in claim 3 is characterized in that, the partial-length that described ground floor faraday shield is in directly over the described polysilicon gate is the 0.1-0.3 micron.
4. radio frequency horizontal dual pervasion field effect transistor as claimed in claim 3 is characterized in that, the partial-length that described second layer faraday shield is in directly over the described polysilicon gate is the 0-0.3 micron.
5. a transistorized manufacture method as claimed in claim 1 is characterized in that, comprising:
Step 1, at P type Grown P type epitaxial loayer; Behind the gate oxidation layer growth, depositing polysilicon by photolithography plate definition and etch polysilicon gate, after etching is finished, carries out the N-type Implantation of the light dope LDD of a step higher-energy, forms the light dope drift region;
The formation of step 2, P trap;
The formation in step 3, P+ zone, N+ source region and N+ drain region;
Step 4, on described P type epitaxial loayer whole deposit layer of silicon dioxide layer, the heavily doped polysilicon of deposit one deck again consists of ground floor faraday shield to described polysilicon by chemical wet etching; Subsequently, whole deposit layer of silicon dioxide layer again on described ground floor faraday shield, then the heavily doped polysilicon of deposit one deck consists of second layer faraday shield to described polysilicon by chemical wet etching;
The formation of step 5, P type polysilicon plug or metal plug structure.
6. manufacture method as claimed in claim 5 is characterized in that, carries out the N-type Implantation of the light dope LDD of a step higher-energy in the step 1, and ion is phosphorus or arsenic, and energy is 50-300keV, and dosage is 5e
11-4e
12Cm
-2
7. the manufacture method shown in claim 5 is characterized in that, the trap of P described in the step 2 be formed with dual mode, a kind of is to form by injecting to advance with high temperature before polysilicon gate forms, another kind is to increase temperature to advance by self-registered technology to form.
8. the manufacture method shown in claim 7 is characterized in that, described P trap, ion are boron, and energy is 30-80keV, and dosage is 1e
12-1e
14Cm
-2
9. the manufacture method shown in claim 1 is characterized in that, the formation in the source region of N+ described in the step 3 and N+ drain region, and ion is phosphorus or arsenic, and energy is 0-200keV, and dosage is 1e
13-1e
16Cm
-2, the formation in described P+ zone, ion is boron or boron difluoride, and energy is 0-100keV, and dosage is 1e
13-1e
16Cm
-2
10. manufacture method as claimed in claim 1 is characterized in that, the faraday of ground floor described in the step 4 shield, and its length is the 0.5-1.5 micron, and thickness is 800-2500A, and impurity is phosphorus or arsenic, and doping content is 5e
18-1e
20Cm
-3Described second layer faraday shield, its length is the 1.5-2.5 micron, and thickness is 800-2500A, and impurity is phosphorus or arsenic, and doping content is 5e
18-1e
20cm
-3
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716180A (en) * | 2013-12-12 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | Radio frequency LDMOS device and technological method |
| CN104752499A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method |
| CN104966736A (en) * | 2015-06-01 | 2015-10-07 | 电子科技大学 | Radio frequency LDMOS device and manufacturing method thereof |
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| CN102237410A (en) * | 2010-04-29 | 2011-11-09 | Nxp股份有限公司 | Semiconductor transistor comprising two electrically conductive shield elements |
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| CN104716180A (en) * | 2013-12-12 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | Radio frequency LDMOS device and technological method |
| CN104752499A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method |
| CN104966736A (en) * | 2015-06-01 | 2015-10-07 | 电子科技大学 | Radio frequency LDMOS device and manufacturing method thereof |
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