CN103762160B - Deep silicon etching method - Google Patents
Deep silicon etching method Download PDFInfo
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- CN103762160B CN103762160B CN201410042467.2A CN201410042467A CN103762160B CN 103762160 B CN103762160 B CN 103762160B CN 201410042467 A CN201410042467 A CN 201410042467A CN 103762160 B CN103762160 B CN 103762160B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 266
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 266
- 239000010703 silicon Substances 0.000 title claims abstract description 266
- 238000005530 etching Methods 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 52
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 26
- 239000008367 deionised water Substances 0.000 claims abstract description 21
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 21
- 238000004140 cleaning Methods 0.000 claims abstract description 14
- 230000007797 corrosion Effects 0.000 claims description 83
- 238000005260 corrosion Methods 0.000 claims description 83
- 238000003760 magnetic stirring Methods 0.000 claims description 38
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- 238000003756 stirring Methods 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000001035 drying Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 abstract 6
- 239000000243 solution Substances 0.000 description 119
- 238000006243 chemical reaction Methods 0.000 description 21
- 239000002253 acid Substances 0.000 description 12
- 230000003628 erosive effect Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 239000007788 liquid Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 238000013517 stratification Methods 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 238000011010 flushing procedure Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 polypropylene Polymers 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002242 deionisation method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011236 particulate material Substances 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00539—Wet etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0128—Processes for removing material
- B81C2201/013—Etching
- B81C2201/0133—Wet etching
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Weting (AREA)
Abstract
The invention relates to the field of silicon wafer etching, in particular to a deep silicon etching method and device. The deep silicon etching method comprises the following steps of placing an etchant solution into a water bath, heating the etchant solution to the preset temperature, stirring the etchant solution through a magnetic stirrer, enabling the temperature inside the etchant solution to be even, vertically placing silicon wafers with masks into the etchant solution to be etched, cleaning the etched silicon wafers with deionized water, drying the silicon wafers with nitrogen, and obtaining the finished silicon wafers. According to the deep silicon etching method and device, compared with the prior art, the structures, graphs and sizes of the etched silicon wafers are consistent respectively.
Description
Technical field
The present invention relates to silicon chip erosion field, in particular to deep silicon etching method and its device.
Background technology
With the high speed development of science and technology, electronic devices and components gradually develop to miniaturization, integrated direction, MEMS
(Micro Electro Mechanical System, MEMS) becomes micro- devices such as making micromechanics, sensor, control circuit
Part, and above-mentioned device is integrated in the key technology of chip.The wet etching grown up according to silicon anisotropic etching characteristic
Technique is exactly a kind of important means for making MEMS.
The wet-etching technology being usually used now is first to apply one layer of mask in silicon chip surface, by needed for wet etching
Utensil is cleaned, and then adds etchant solution in the reactor.After starting etching, directly silicon chip is placed in etchant solution
Portion, is performed etching to silicon chip using etchant solution, and etching takes out silicon chip after a period of time, and etching is completed after flushing.
But in etch stages, etchant solution internal temperature is uneven, can produce the situation of thermal stratification so that in difference
The silicon chip surface corrosion rate of temperature layer is different, and the structure that causes to etch, figure, size are inconsistent, it is impossible to reach what is wanted
Corrosion results.
The content of the invention
It is an object of the invention to provide deep silicon etching method and its device, above-mentioned to solve the problems, such as.
Deep silicon etching method is provided in an embodiment of the present invention, is comprised the steps：
Etchant solution is placed in water-bath and is heated to predetermined temperature, and etchant solution is stirred by magnetic stirring apparatuss
Mix, make etchant solution internal temperature uniform；
Silicon chip with mask is vertically placed to corrode in etchant solution；
The silicon chip deionized water corroded is cleaned and Jing nitrogen is dried up, obtain finished product silicon chip.
Preferably, the silicon chip with mask is vertically placed to corrode in etchant solution by step, specifically includes following steps：
Side is vertically placed to corrode in etchant solution with the first mask, silicon chip of the opposite side with the second mask, is made
Silicon slice corrosion predetermined thickness, the aperture position of the first mask are different from the aperture position of the second mask；
Taking-up is vertically placed to the silicon chip in etchant solution, and remembers that predetermined thickness is H1, remembers that silicon chip is placed in etchant solution
Time is T；
Again silicon chip is placed in inside etchant solution, and timing；
When again being reached the anticaustic time time that silicon chip is placed in inside etchant solution, silicon chip is taken out again, is gone
Fall the mask with the second mask open opposite position on the first mask, remove corresponding with the first mask open on the second mask
The mask of position, and the corrosion depth of silicon chip that note is taken out again is H2, wherein anticaustic time=(silicon chip gross thickness-H1-
H3 the 15%-20% of) * T/H1, H3 for silicon chip gross thickness；
Silicon chip of the corrosion depth for H2 is placed in etchant solution, and timing；
The silicon chip in etchant solution is taken out when the time of timing remaining time is reached, the silicon chip for having corroded is obtained, it is remaining
The calculation of time is, remaining time=(silicon chip gross thickness-H2) * T/H1.
Preferably, side is vertically placed to into corrosion with the first mask, silicon chip of the opposite side with the second mask in step
Corrode in solution, after making silicon slice corrosion predetermined thickness, also wrapped before step takes out the silicon chip being vertically placed in etchant solution
Include step, interim cleaning silicon chip, specially：
The silicon chip with mask is taken out, and is cleaned with high-purity deionized water and Jing nitrogen is dried up；
The silicon chip with mask that Jing nitrogen is dried up is again placed in the etchant solution.
Preferably, the interim cleaning silicon chip of step is multiple.
Preferably, Tetramethylammonium hydroxide etchant solution of the etchant solution for mass concentration 25%.
Preferably, step is placed in etchant solution in water-bath and is heated to predetermined temperature, and by magnetic stirring apparatuss to corrosion
Solution is stirred, and in making etchant solution internal temperature uniform, predetermined temperature is spent for 80 degree -85.
The embodiment of the present invention additionally provides a kind of deep silicon etching device for realizing deep silicon etching method provided by the present invention,
Including reactor, reactor cap, corrosion rack, stirrer, magnetic stirring apparatuss and etcher,
Hollow barrel of the etcher in one end open；
Magnetic stirring apparatuss are in the inside for being placed in etcher, and contact surface of the etcher by magnetic stirring apparatuss with etcher is propped up
Support magnetic stirring apparatuss；
Hollow barrel of the reactor in one end open, reactor are placed in inside etcher, and magnetic stirring apparatuss pass through magnetic force
Agitator supports reactor with the contact surface of etcher；
Stirrer is in the form of a column, and is placed in reactor bottom；
Long striped groove is provided with corrosion rack, is also set up on the corrosion rack in the direction contrary with the opening of long striped groove
There is support member, corrosion rack is connected with reactor bottom by support member, and corrosion rack is more than with the distance of reactor bottom and stir
The diameter of sub cross section along its length is mixed, and is rotated stirrer；
Reactor cap is engaged with the opening of reactor, and is flexibly connected, and makes reactor form the hollow cavity of sealing.
Preferably, stirrer is along its length from middle-end to the tapered American football shape in two ends.
Describe the technical scheme of exclusive rights
Directly the silicon chip with mask is prevented in deep silicon etching method provided in an embodiment of the present invention, with prior art
Perform etching inside etchant solution and compare, which makes the temperature of etchant solution by using the method that heating in water bath and stirrer are stirred
Become uniform with liquor strength, so that the structure of the silicon chip for etching, figure, consistent size, that is, solve existing
Deficiency in technology.
Description of the drawings
Fig. 1 shows the deep silicon etching method basic flow sheet of the embodiment of the present invention；
Fig. 2 shows the etching process flow chart of the deep silicon etching method of the embodiment of the present invention；
Fig. 3 shows the structure chart of the deep silicon etching device of the embodiment of the present invention；
Fig. 4 shows the finished product enlarged drawing performed etching to silicon chip using the method for prior art；
Fig. 5 shows the finished product enlarged drawing performed etching to silicon chip using method provided by the present invention.
In figure：1st, etcher；2nd, magnetic stirring apparatuss；3rd, stirrer；4th, corrosion rack；5th, reactor；6th, reactor cap；7th, silicon
Piece.
Specific embodiment
Below by specific embodiment and combine accompanying drawing the present invention is described in further detail.Shown in Fig. 1, this
Invention provides deep silicon etching method, including following basic step：
S101, etchant solution is placed in water-bath and is heated to predetermined temperature, and etchant solution is entered by magnetic stirring apparatuss
Row stirring, makes etchant solution internal temperature uniform；
S102, the silicon chip with mask is vertically placed to corrode in etchant solution；
S103, the silicon chip deionized water corroded is cleaned and Jing nitrogen is dried up, obtain finished product silicon chip.
The effect of step S101 is that etchant solution is heated to the predetermined reaction temperature that can be performed etching, it is to avoid straight
The uneven and temperature uncontrollability of being heated that heating is caused is connect, etchant solution can be allow smoothly using immersion method heating
It is heated to predetermined reaction temperature.During heating in water bath, heat is the four circumferential middle part conduction from etchant solution, is still probably temperature
Degree is not uniform enough, and it is well known that reaction temperature determines the speed of reaction, by using magnetic stirring apparatuss to etchant solution
It is stirred so as to which internal temperature becomes more uniform, it is ensured that etching reaction is that the temperature inside etchant solution is equal
Under conditions of start, make the corrosion rate on corrosion of silicon surface equal everywhere.
The effect of step S102 is that, after predetermined temperature is heated to, silicon chip to be corroded is put in etchant solution to be carried out
Corrosion, while magnetic stirring apparatuss are still in operating, magnetic stirring apparatuss are to be constantly in working condition in the overall process of etching reaction
, always etchant solution is being stirred, is making temperature and concentration inside etchant solution equal everywhere.As etching reaction is
Heat release, and the concentration and reaction temperature of etchant solution determine corrosion efficiency, by the rotation of magnetic stirring apparatuss, make corrosion molten
Temperature and solution concentration inside liquid keeps stable, it is ensured that the concordance of silicon chip different piece corrosion rate.
The effect of step S103 is after corrosion has carried out a period of time, by the silicon chip extracting for having corroded, and using going
Ionized water is cleaned to the silicon chip for having corroded, then which is dried up with nitrogen, and the corrosion for eliminating silicon chip surface residual is molten
Liquid so as to can be preserved for a long time.
Wherein step S102 can also be refined, as shown in Fig. 2 being specially
Silicon chip with mask is vertically placed to corrode in etchant solution, following steps are specifically included：
S201, side is vertically placed in etchant solution with the first mask, silicon chip of the opposite side with the second mask rotten
Erosion, makes silicon slice corrosion predetermined thickness, and the aperture position of the first mask is different from the aperture position of the second mask；
S202, taking-up are vertically placed to the silicon chip in etchant solution, and remember that predetermined thickness is H1, remember that silicon chip is placed in etchant solution
In time be T；
S203, is placed in silicon chip inside etchant solution again, and timing；
S204, when again being reached the anticaustic time time that silicon chip is placed in inside etchant solution, takes out silicon again
Piece, removes the mask with the second mask open opposite position on the first mask, remove on the second mask with the first mask open
The mask of opposite position, and the corrosion depth of silicon chip that note is taken out again is H2；Wherein anticaustic time=(silicon chip total thickness
Degree-H1-H3) * T/H1,15%-20%s of the H3 for silicon chip gross thickness；
S205, silicon chip of the corrosion depth for H2 is placed in etchant solution, and timing；
S206, takes out the silicon chip in etchant solution, obtains the silicon chip for having corroded when the time of timing remaining time is reached,
The calculation of remaining time is, remaining time=(silicon chip gross thickness-H2) * T/H1.
During performing etching to silicon chip, it is important that a link be determine etching the time point for completing, such as
The time of fruit etching is too short, then silicon chip can be caused directly cannot to use, also in need on silicon chip to carve disconnected, but and not carved off connection
Place, may now need to perform etching again, or directly discard silicon chip, cause the waste of resource；If etching when
Between it is long, then the phenomenon carved can occur, crossed the silicon chip carved as its structure there occurs change, be to realize which is due
Effect, cannot also use, can only discard, this equally causes the waste of resource.
For the problem for overcoming etch period determine, solved in the application as follows.By side
It is vertically placed to corrode in etchant solution with the first mask, silicon chip of the opposite side with the second mask, makes the predetermined thickness of silicon slice corrosion
Degree, the aperture position of the first mask are different from the aperture position of the second mask.Wherein, the first mask, silicon chip, the second masking sequence
Connection.The silicon chip surface covered by the first mask will not be reacted with etchant solution, and opposite side is covered with second
The silicon chip surface covered by film also will not be reacted with etchant solution.Due to the aperture position and the second mask of the first mask
Aperture position it is different so that although the surface not covered by mask by both sides silicon chip there occurs reaction with etchant solution,
With by the first mask open position another side surface of the corresponding silicon chip of exposed silicon chip surface covered by the second mask,
It is same be by the first mask institute by another side surface of the corresponding silicon chip of the exposed silicon chip surface of the second mask open position institute
Cover, that is, one side etching is being carried out equivalent to the both sides of silicon chip.
Taking-up is vertically placed to the silicon chip in etchant solution, and remembers that predetermined thickness is H1, remembers that silicon chip is placed in etchant solution
Time is T.Take out after the corrosion regular hour, it is clear that when defining that in subsequent step next time takes out, silicon chip is etched
Depth in 80%-85% or so, so, this time taking out silicon chip needs to carry out before 80% in the depth being etched, specifically
The time of taking-up can be voluntarily held by staff.Certainly, can not further take out after silicon chip is etched and breaks, otherwise cannot
Carry out follow-up etching work.The purpose this time taken out is the corrosion rate for calculating silicon chip surface, is continued after concrete calculating process
It is bright.The silicon chip deionized water of taking-up is cleaned up, then the liquid for remaining in the surface of silicon chip is blown with high pure nitrogen again
Totally, then with step instrument the thickness that silicon chip is corroded is measured, and the corrosion thickness is recorded for H1.Record the silicon chip and be placed in and corrode molten
Time in liquid is T.Wherein, the thickness being corroded refers to, the silicon chip being corroded apart from most portionafrom theasurface a little and its original table
Vertical dimension between face, as the two sides of silicon chip is corroded simultaneously, and due to the concentration of the material and etchant solution of silicon chip it is equal
It is identical everywhere, it is possible to be interpreted as, in the equal time, the thickness that silicon chip surface is corroded is identical, that is,
H1, corrosion rate i.e. in the unit interval, erodes the depth of silicon chip, i.e. H1/T.
After reordering the silicon chip of taking-up is again placed in etchant solution, when again silicon chip is placed in inside etchant solution
When time reaches the anticaustic time, take out silicon chip again, remove on the first mask with the second mask open opposite position
Mask, removes the mask with the first mask open opposite position on the second mask, and remembers the corrosion depth of the silicon chip for taking out again
Spend for H2, wherein anticaustic time=(silicon chip gross thickness-H1-H3) * T/H1,15%-20%s of the H3 for silicon chip gross thickness.The
It is secondary that silicon chip is placed in etchant solution, and according to corrosion rate V for having calculated, it is precisely calculated silicon slice corrosion depth
Reach the time required for 80%-85%, its calculation is, the anticaustic time equal to the thickness for needing to be corroded divided by
Corrosion rate.Wherein need the gross thickness that the thickness being corroded is equal to silicon chip to deduct the first thickness H1 for eroding, then deduct
The remaining thickness after anticaustic, when being to ensure secondary taking-up silicon chip, the thickness for having corroded is 80%-85%, so
After anticaustic, remaining thickness is the 15%-20% of the gross thickness of silicon chip.Corrosion rate V=H1/T is brought into, that is,
The anticaustic time=(silicon chip gross thickness-H1-H3) * T/H1.When corrosion depth reaches 80%-85%, taking-up is placed in corrosion
Silicon chip in solution, and remove the mask on the first mask with the second mask open opposite position, remove on the second mask with
The mask of the first mask open opposite position, makes silicon chip removing the mask of correspondence position, and here is placed in etchant solution
The silicon chip for only carrying out originally single-sided corrosion can be made afterwards to carry out two-sided etching, meanwhile, 80%- is reached in the corrosion depth of silicon chip
When 85%, by silicon chip extracting after, in order to more accurately measure the depth corroded, will also be to taking out the corrosion depth of silicon chip
H2 is measured, and to be precisely calculated final etching time, final etching time is discussed in greater detail hereinafter.Wherein corrosion depth
Refer to, vertical dimension a little and between its initial surface of the silicon chip being corroded apart from most portionafrom theasurface.It is anisotropic by silicon chip
Affect, it is a plane that a side of etching silicon wafer can make 111 faces of the silicon chip being etched, if otherwise directly carrying out two-sided
Etching, 111 faces are then a curved surface.And 111 faces for plane silicon chip when in use, effect be better than 111 faces be curved surface silicon
Piece.When corrosion depth reaches the 80%-85% of silicon chip gross thickness, remove position corresponding with the second mask open on the first mask
The mask put, removes the mask with the first mask open opposite position on the second mask, then proceeds by the surface of silicon chip
Two-sided etching, on the premise of 111 faces that ensure that are plane, the technique for completing etching.
The silicon chip that corrosion depth is H2 will be recorded to be placed in etchant solution, while reclocking, now, covered due to first
With mask with the first mask open opposite position on the mask and the second mask of the second mask open opposite position on film
It has been removed, protecting film is removed from the surface of silicon chip, so original tape has protecting film and the position that is removed starts and corruption
Erosion solution reacts, that is, the two sides of silicon chip is performing etching.Reach when the time of reclocking, that is, remaining time
During to (silicon chip gross thickness-H2) * T/H1, the silicon chip is taken out.Now the silicon chip is both the finished product silicon chip for completing to etch.
Can obtain there remains by the difference for calculating silicon chip gross thickness with measure corrosion depth H2 for obtaining for the second time many
The silicon chip of few thickness is not corroded, and combines speed V for having calculated, and the silicon chip that can obtain residual thickness is also needed to
How long can be corroded, i.e. remaining time=(silicon chip gross thickness-H2)/V, bring V=H1/T into the formula, that is,
Remaining time=(silicon chip gross thickness-H2) * T/H1.Certainly, now remaining corrosion depth is the 15%- of silicon chip gross thickness
20%.By the position that can be more accurately determined two-sided etching cross point remaining time for calculating etching, make etched
The phenomenon carved will not occur in journey, and then the defect rate of the silicon chip of the etching for making to complete declined.So far, how to determine that silicon chip is carved
The problem of erosion time is just solved.
When etchant solution corrodes to the silicon chip with mask, that is, there is chemistry with silicon chip in etchant solution
When reaction, a certain amount of reactant can be produced, reactant is in black particle shape, if not by the material of the black particle shape
Clean out, then black particle shape material can affect silicon chip to proceed reaction with etchant solution, make the concordance that silicon chip is etched
It is deteriorated.In order to overcome the problem, the silicon chip with mask is vertically placed to corrode in etchant solution in step so as to which corrosion is predetermined
After thickness, also include step before step takes out the silicon chip with mask being vertically placed in etchant solution, it is interim to clean
Silicon chip, specially：
The silicon chip with mask is taken out, and is cleaned with high-purity deionized water and Jing nitrogen is dried up；
The silicon chip with mask that Jing nitrogen is dried up is again placed in the etchant solution.
After corrosion certain hour, silicon chip is taken out with strong alkali-acid resistance tweezers, then is rinsed well with high-purity deionized water,
Silicon chip high pure nitrogen is blown clean after the completion of flushing to reappose and continue corrosion in etchant solution.It should be noted that many
The interim cleaning step of secondary repetition can reduce the black particle shape material produced on silicon chip surface during silicon chip erosion, improve overall
The concordance of silicon chip erosion.Certainly, if repeat number of times it is excessively frequent, temporal waste can be caused, through measuring and calculating and
Experiment show that interim cleaning was carried out once per 30 minutes just can be delayed while fully cleaning particulate material is ensured
Normal etch period.Certainly, the work of interim cleaning in the whole process of corrosion, can be carried out to silicon chip, to remove its surface
Black particle shape material.Interim cleaning can occur after being vertically placed to corrode in etchant solution by the silicon chip with mask,
Before taking-up is vertically placed to the silicon chip with mask in etchant solution；Can also occur to be vertically placed in etchant solution in taking-up
The silicon chip with mask after, until etching is completed, before taking out the silicon chip that corroded.
In deep silicon etching method provided by the present invention, the material of mask is SiO2, Tetramethylammonium hydroxide etchant solution pair
The corrosion rate of SiO2 is extremely low, is especially suitable for deep silicon etching.Draw through measuring and calculating and experiment, etchant solution is mass concentration 25%
Tetramethylammonium hydroxide etchant solution.
It is to be driven by magnetic stirring apparatuss to the stirrer that etchant solution is stirred, if its rotating speed is too high, corrodes
Current in solution can affect the concentration of etchant solution, and rotating speed is too low, then do not have the effect of stirring.According to experiment measuring and calculating, magnetic
The rotating speed of power agitator is that 160 turns/min-220 turns/min.
Temperature is an essential condition for affecting etchant solution and silicon chip reaction, can further be controlled by controlling reaction temperature
Reaction processed carries out speed, and step is placed in etchant solution in water-bath and is heated to predetermined temperature, and by magnetic stirring apparatuss to corrosion
Solution is stirred, and in making etchant solution internal temperature uniform, predetermined temperature is spent for 80 degree -85.When predetermined temperature at 80 degree extremely
When between 85 degree, the speed of corrosion is relatively reasonable.
The silicon chip deionized water corroded is cleaned and Jing nitrogen is dried up, obtain finished product silicon chip.
After corrosion certain hour, the tweezers of the silicon chip strong alkali-acid resistance for having corroded are taken out, and deionized water
Cleaned, dried up with nitrogen after cleaning again.Now the silicon chip through drying up is both the silicon chip for completing etching technics.
It should be noted that in the overall process of reaction, it is understood that drive after stirrer rotation for magnetic stirring apparatuss,
Before the tweezers of the silicon chip strong alkali-acid resistance that will have corroded take out, as etchant solution carries out corruption to the silicon chip with mask
It is that the hotter part of temperature can flow up in heat release, and etchant solution during erosion, and then in causing corrosion solution
Temperature is not equal everywhere, that is, the phenomenon of thermal stratification.Meanwhile, the solute in etchant solution has precipitation to be occurred, and enters
And the concentration in causing corrosion solution is not equal everywhere, that is, the phenomenon of concentration stratification.Though this kind of phenomenon can directly cause
It is substantially equal everywhere that so silicon chip is put into the time in etchant solution, but the corrosion depth of the different piece on silicon chip is different
, it is impossible to overcoming the problem of thermal stratification and concentration stratification directly result in the silicon chip for etching cannot use.
To overcome the problem of non-uniform temperature and uneven concentration, the stirrer driven by magnetic stirring apparatuss is in etching reaction
The whole process for carrying out all in rotation so that temperature of the etchant solution in reactor in etching process is constantly in identical everywhere
State and etchant solution are isocyatic state everywhere, it is ensured that the etching reaction carried out by each position of silicon chip is mutually synchronized
Rate, and then the concordance of the structure and figure of the silicon chip for making to etch is more preferable.Fig. 4 shows the method pair using prior art
The finished product enlarged drawing that silicon chip is performed etching, Fig. 5 are shown
Finished product enlarged drawing.Very intuitively it can be seen that using the structure of the silicon chip etched after provided by the present invention but method,
Figure, size concordance it is more preferable.
As shown in Figure 3 present invention also offers the deep silicon etching for realizing deep silicon etching method provided by the present invention is filled
Put, the device includes
Reactor 5, reactor cap 6, corrosion rack 4, stirrer 3, magnetic stirring apparatuss 2 and etcher 1,
Hollow barrel of the etcher 1 in one end open；
Magnetic stirring apparatuss 2 are in being placed in the inside of etcher 1, and the connecing by magnetic stirring apparatuss 2 and etcher 1 of etcher 1
Contacting surface supports magnetic stirring apparatuss 2；
Hollow barrel of the reactor 5 in one end open, reactor 5 is placed in inside etcher 1, and magnetic stirring apparatuss 2 pass through
Magnetic stirring apparatuss 2 support reactor 5 with the contact surface of etcher 1；
Stirrer 3 is in the form of a column, and is placed in 5 bottom of reactor；
Long striped groove is provided with corrosion rack 4, is also set on the corrosion rack 4 in the direction contrary with the opening of long striped groove
Support member is equipped with, corrosion rack 4 is connected with 5 bottom of reactor by support member, and makes corrosion rack big with the distance of 5 bottom of reactor
In the diameter of the cross section along its length of stirrer 3, and rotated stirrer 3；
Reactor cap 6 is engaged with the opening of reactor 5, and is flexibly connected, and makes reactor 5 form the middle cavity of sealing
Body.
Wherein, etcher 1 goes to conduct the ionized water used by heat to etchant solution in heating in water bath for containing, by magnetic force
Agitator 2 keeps flat the bottom into etcher 1, and in the present invention, magnetic stirring apparatuss 2 is preferably shaped to rectangle, naturally it is also possible to be
Other can support the shape of reactor 5.Control box of the magnetic stirring apparatuss 2 by wire with outside is electrically connected, and control box can
To control the rotating speed of magnetic stirring apparatuss 2.Etchant solution is injected in reactor 5, the etchant solution of injection reaches and do not stand
7 most significant end of silicon chip that formula is placed, to ensure that silicon chip 7 can carry out corrosion reaction everywhere.Herein what deserves to be explained is, forward direction it is rotten
The liquid level of the deionized water injected in erosion device 1 should be higher than that the liquid level of the etchant solution in reactor 5, or hold with which
It is flat, and less than edge on the wall of cup of reactor 5, make deionized water while heat is conducted to etchant solution, may not flow into corruption
Inside erosion solution.Again reactor 5 is placed into above magnetic stirring apparatuss 2, stirrer 3 and corrosion rack 4 in reactor 5, is placed.It is rotten
Erosion frame 4 can be arbitrary shape, and its function is fixed reaction silicon chip 7 used, meanwhile, corrosion rack 4 can not affect stirring
Son 3 is rotated.The position that stirrer 3 is placed is corresponding with magnetic stirring apparatuss 2, is to drive stirring by magnetic stirring apparatuss 2
Son 3 is rotated.
Now just can open magnetic stirring apparatuss 2 and set rotating speed, treat that temperature reaches predetermined temperature in etcher 1
During value, on the corrosion rack 4 that silicon chip 7 is put in reactor 5, then reactor 5 is covered with reactor cap 6, start the quarter to silicon chip 7
Erosion.
What deserves to be explained is, the material of reactor 5 is preferably polypropylene material, the reactor 5 that this kind of material is supported not with
There is chemical reaction in reaction solution, would not also have influence on the etching of silicon chip 7.2 shell of magnetic stirring apparatuss is preferably stainless steel
Matter, with silica gel sealing at its junction or gap so as to depth water-proof function, and the cable carried by agitator and control
Box processed connects to control rotating speed.Support is polytetrafluoroethylmaterial material, anticorrosive, above has long striped groove, and the width of groove is slightly larger
In 7 thickness of silicon chip.Silicon chip 7 is vertical to be positioned on corrosion rack 4, side by side with the spaced and parallel placement of identical.
Certainly, stirrer 3 is less with the contact area of reactor 5, and stirrer 3 is produced with reactor 5 when rotation
Frictional force it is less, stirrer 3 is along its length from middle-end to the tapered American football shape in two ends.The stirrer 3 of this kind of shape
Can ensure which and at the uniform velocity rotated clockwise with level, and rotate it is more unobstructed.
Deep silicon etching method provided by the present invention is illustrated below by a specific embodiment：
The equipment that will be used in experiment is preferably first carried out by deep silicon etching method provided by the present invention before start
Pretreatment.Reactor, graduated cylinder, stirrer, strong alkali-acid resistance tweezers, corrosion rack, thermometer etc. are placed on into ultrasound wave first generally
Vessel cleaning is carried out in cleaning machine, ultrasonic power is set to 600W, and electric current is about 2A, is cleaned by ultrasonic time about 20min.
Then inject etchant solution again in reactor, concrete grammar is：The tetramethyl hydrogen of certain capacity is measured with graduated cylinder
Amine-oxides etchant solution, mass concentration are 25%, and beaker inclines 45 degree, and graduated cylinder is poured slowly into beaker along walls of beaker, will finally stir
Mix son, corrosion rack tweezers and clamp and be put in beaker, magnetic stir plate level is put into into corrosion trench bottom, external rotating speed control
Box processed, to the rotary speed for adjusting magnetic stirring apparatuss.
Then add deionized water into etching tank, liquid level should maintain an equal level or liquid level slightly above in beaker, arrange
Good heating-up temperature, opens heater switch and begins to warm up.
Etchant solution is placed in water-bath and is heated to predetermined temperature, and etchant solution is stirred by magnetic stirring apparatuss
Mix, make etchant solution internal temperature uniform.
By the ready reactor for filling etchant solution be put into the magnetic stirring apparatuss in etching tank on carry out at preheating
Reason, about 30 minutes preheating time, while opening magnetic stirring apparatuss, now the stirrer in beaker at the uniform velocity turns in a clockwise direction
It is dynamic, stirrer rotation is driven by magnetic stirring apparatuss, the etchant solution in reactor is quickly heated, and make etchant solution
Temperature is more uniform.
After up to preheating 30 minutes, default temperature whether is reached with thermometer measure beaker internal corrosion solution, and examined
Temperature is tested whether stable, generally the temperature range of temperature should be less than 0.5 DEG C and can carry out follow-up etching work.
It is after etchant solution temperature reaches predetermined temperature, and temperature stabilization, strong with cleaned resistance to strong acid
Alkali tweezers clamping clean up with mask silicon chip, it is vertical, vertical be put on corrosion rack start corrosion.Silicon chip with mask
It is good through lithography process, side is with the first mask, silicon chip of the opposite side with the second mask, and cleans through deionized water
The silicon chip crossed, wherein the aperture position of the first mask is different from the aperture position of the second mask.Vertical placement refers to, by silicon chip with
Trimming downwardly direction, perpendicular to corrosion rack, is put in the fluting of support, and this kind of modes of emplacement can make the silicon chip with mask
It is more steady with the contact of corrosion rack.Certainly, the groove width of corrosion rack is larger than silicon wafer thickness, it is ensured that do not scratch silicon chip table
Face, and silicon chip is less than or equal to 5 degree with the vertical angle of fluting.
After corrosion certain thickness, the silicon chip with mask is taken out with the tweezers of strong alkali-acid resistance, and use high-purity deionization
Simultaneously Jing nitrogen is dried up for water cleaning；
The silicon chip with mask that Jing nitrogen is dried up is again placed in the etchant solution.
After corrosion certain thickness, the silicon chip being vertically placed in etchant solution is taken out with the tweezers of strong alkali-acid resistance, with high-purity
Simultaneously Jing nitrogen is dried up the cleaning of degree deionized water, and remembers that predetermined thickness is H1, remembers that the time that silicon chip is placed in etchant solution is T；
The silicon chip with mask is taken out with the tweezers of strong alkali-acid resistance, and cleaned with high-purity deionized water and Jing nitrogen blows
It is dry；
The silicon chip with mask that Jing nitrogen is dried up is again placed in the etchant solution.
Again silicon chip is placed in inside etchant solution, and timing；
The silicon chip with mask is taken out with the tweezers of strong alkali-acid resistance, and cleaned with high-purity deionized water and Jing nitrogen blows
It is dry；
The silicon chip with mask that Jing nitrogen is dried up is again placed in the etchant solution.
When again being reached the anticaustic time time that silicon chip is placed in inside etchant solution, with the tweezer of strong alkali-acid resistance
Son takes out silicon chip again, and is cleaned with high-purity deionized water and removed Jing after nitrogen is dried up on the first mask and open with the second mask
The mask of mouth opposite position, removes the mask with the first mask open opposite position on the second mask, and note is taken out again
Silicon chip corrosion depth be H2, wherein anticaustic time=(silicon chip gross thickness-H1-H3) * T/H1, H3 be silicon chip gross thickness
15%-20%；
Silicon chip of the corrosion depth for H2 is placed in etchant solution, and timing；
The silicon chip with mask is taken out with the tweezers of strong alkali-acid resistance, and cleaned with high-purity deionized water and Jing nitrogen blows
It is dry；
The silicon chip with mask that Jing nitrogen is dried up is again placed in the etchant solution.
When the time of timing remaining time is reached, the silicon chip in etchant solution is taken out with the tweezers of strong alkali-acid resistance, is obtained
To the silicon chip for having corroded, the calculation of remaining time is, remaining time=(silicon chip gross thickness-H2) * T/H1.
By the silicon chip extracting for having corroded, and the silicon chip for having corroded is cleaned using deionized water, then with nitrogen to which
Dried up, eliminated the etchant solution of silicon chip surface residual so as to can be preserved for a long time.
Deep silicon etching method provided by the present invention, by the basis of prior art, by using heating in water bath
The temperature and liquor strength of etchant solution is made to become uniform with the method for stirrer stirring, so that the knot of the silicon chip for etching
Structure, figure, consistent size, that is, solve deficiency of the prior art.
The preferred embodiments of the present invention are these are only, the present invention is not limited to, for those skilled in the art
For member, the present invention can have various modifications and variations.All any modifications within the spirit and principles in the present invention, made,
Equivalent, improvement etc., should be included within the scope of the present invention.
Claims (5)
1. deep silicon etching method, it is characterised in that comprise the steps：
Etchant solution is placed in water-bath and is heated to predetermined temperature, and the etchant solution is stirred by magnetic stirring apparatuss
Mix, make the etchant solution internal temperature uniform；
Silicon chip with mask is vertically placed to corrode in the etchant solution；
The silicon chip deionized water corroded is cleaned and Jing nitrogen is dried up, obtain finished product silicon chip；
Silicon chip with mask is vertically placed to corrode in the etchant solution by the step, specifically includes following steps：
Side is vertically placed to corrode in the etchant solution with the first mask, silicon chip of the opposite side with the second mask, is made
Silicon slice corrosion predetermined thickness, the aperture position of first mask are different from the aperture position of second mask；
The silicon chip being vertically placed to described in taking out in the etchant solution, and the predetermined thickness is remembered for H1, the note silicon chip
The time being placed in the etchant solution is T；
Again the silicon chip is placed in inside the etchant solution, and timing；
When again being reached the anticaustic time time that the silicon chip is placed in inside the etchant solution, take out again described
Silicon chip, removes the mask with the second mask open opposite position on first mask, removes on second mask
With the mask of the first mask open opposite position, and remember that the corrosion depth of the silicon chip for taking out again is H2,
Wherein described anticaustic time=(silicon chip gross thickness-H1-H3) * T/H1,15%-20%s of the H3 for silicon chip gross thickness；
The silicon chip of the corrosion depth for H2 is placed in the etchant solution, and timing；
The silicon chip in the etchant solution is taken out when the time of the timing remaining time is reached, the silicon for having corroded is obtained
Piece, the calculation of the remaining time is, remaining time=(silicon chip gross thickness-H2) * T/H1.
2. deep silicon etching method according to claim 1, it is characterised in that side is covered with first in the step
The silicon chip of film, opposite side with the second mask corrodes in being vertically placed to the etchant solution, after making silicon slice corrosion predetermined thickness,
Also include step before the silicon chip being vertically placed in the etchant solution described in taking out in the step, clean silicon temporarily
Piece, specially：
Take out the silicon chip with mask, and cleaned with high-purity deionized water and Jing nitrogen is dried up；
By Jing nitrogen dry up described in be again placed in the etchant solution with the silicon chip of mask.
3. deep silicon etching method according to claim 2, it is characterised in that the interim cleaning silicon chip of the step is multiple.
4. deep silicon etching method according to claim 1, it is characterised in that the etchant solution is mass concentration 25%
Tetramethylammonium hydroxide etchant solution.
5. deep silicon etching method according to claim 1, it is characterised in that the step is placed in etchant solution in water-bath
Predetermined temperature is heated to, and the etchant solution is stirred by magnetic stirring apparatuss, make the etchant solution internal temperature
In uniform, the predetermined temperature is spent for 80 degree -85.
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| CN104609365B (en) * | 2015-02-14 | 2016-12-07 | 苏州工业园区纳米产业技术研究院有限公司 | Deep silicon etching board and chip protection device thereof |
| CN104821349A (en) * | 2015-03-31 | 2015-08-05 | 山西南烨立碁光电有限公司 | Four-element LED chip wet etching method |
| CN109962007A (en) * | 2017-12-26 | 2019-07-02 | 东莞市广信知识产权服务有限公司 | A kind of manufacture craft of semiconductor |
| CN109437085A (en) * | 2018-10-25 | 2019-03-08 | 西南交通大学 | A kind of not damaged friction induction nanoprocessing method |
| CN112086387B (en) * | 2020-08-14 | 2021-06-04 | 北京智创芯源科技有限公司 | Chip cleaning device and cleaning method |
| CN114184613A (en) * | 2021-12-07 | 2022-03-15 | 江苏天鼎检测科技有限公司 | Method capable of clearly displaying carbide |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59179788A (en) * | 1983-03-31 | 1984-10-12 | Fujitsu Ltd | Chemical etching device |
| JPS60119728A (en) * | 1983-11-30 | 1985-06-27 | Matsushita Electric Works Ltd | Etchant stirring device |
| JPH05160095A (en) * | 1991-12-10 | 1993-06-25 | Sharp Corp | Cleaning and drying method of semiconductor wafer |
| JPH0661218A (en) * | 1992-08-07 | 1994-03-04 | Nippondenso Co Ltd | Etching method for semiconductor and device thereof |
| CN1399311A (en) * | 2002-08-29 | 2003-02-26 | 中国科学院上海技术物理研究所 | Etching equipment and method for deep mesa of dual-waveband mercury-cadmium-telluride IR detector |
| JP2003279149A (en) * | 2002-03-26 | 2003-10-02 | Masao Uratani | Fluid heating system |
| CN1545134A (en) * | 2003-11-12 | 2004-11-10 | 四川大学 | Surface etching apparatus for semiconductor film |
| CN1564310A (en) * | 2004-03-18 | 2005-01-12 | 中国科学院上海技术物理研究所 | Appts. for silicon anisotropic corrosion |
| CN101299405A (en) * | 2008-06-16 | 2008-11-05 | 吉林大学 | Method for constructing anti-reflection structure on substrate surface |
| CN102157352A (en) * | 2011-03-23 | 2011-08-17 | 北京大学 | Wet etching method and device for micro-nano structure |
| CN202297838U (en) * | 2011-10-21 | 2012-07-04 | 上海欧普泰科技创业有限公司 | Photo-assisted electrochemical etching device |
-
2014
- 2014-01-28 CN CN201410042467.2A patent/CN103762160B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59179788A (en) * | 1983-03-31 | 1984-10-12 | Fujitsu Ltd | Chemical etching device |
| JPS60119728A (en) * | 1983-11-30 | 1985-06-27 | Matsushita Electric Works Ltd | Etchant stirring device |
| JPH05160095A (en) * | 1991-12-10 | 1993-06-25 | Sharp Corp | Cleaning and drying method of semiconductor wafer |
| JPH0661218A (en) * | 1992-08-07 | 1994-03-04 | Nippondenso Co Ltd | Etching method for semiconductor and device thereof |
| JP2003279149A (en) * | 2002-03-26 | 2003-10-02 | Masao Uratani | Fluid heating system |
| CN1399311A (en) * | 2002-08-29 | 2003-02-26 | 中国科学院上海技术物理研究所 | Etching equipment and method for deep mesa of dual-waveband mercury-cadmium-telluride IR detector |
| CN1545134A (en) * | 2003-11-12 | 2004-11-10 | 四川大学 | Surface etching apparatus for semiconductor film |
| CN1564310A (en) * | 2004-03-18 | 2005-01-12 | 中国科学院上海技术物理研究所 | Appts. for silicon anisotropic corrosion |
| CN101299405A (en) * | 2008-06-16 | 2008-11-05 | 吉林大学 | Method for constructing anti-reflection structure on substrate surface |
| CN102157352A (en) * | 2011-03-23 | 2011-08-17 | 北京大学 | Wet etching method and device for micro-nano structure |
| CN202297838U (en) * | 2011-10-21 | 2012-07-04 | 上海欧普泰科技创业有限公司 | Photo-assisted electrochemical etching device |
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