CN103745999B - Groove power field-effect transistor with insulating buried layer - Google Patents
Groove power field-effect transistor with insulating buried layer Download PDFInfo
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- CN103745999B CN103745999B CN201310745165.7A CN201310745165A CN103745999B CN 103745999 B CN103745999 B CN 103745999B CN 201310745165 A CN201310745165 A CN 201310745165A CN 103745999 B CN103745999 B CN 103745999B
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- 230000005669 field effect Effects 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Abstract
The invention provides a kind of groove power field-effect transistor with insulating buried layer, including: source layer and drain electrode layer, described source layer is arranged on the first surface of substrate, and described drain electrode layer is arranged on the second surface that substrate is relative with first surface；Doping well layer, described doping well layer is arranged between described source layer and drain electrode layer, and fits with described source layer and drain electrode layer, and described source layer and drain electrode layer have the first conduction type, and described doping well layer has the second conduction type；Grid, the first surface of described substrate has one first groove further, fills gate dielectric layer, have one second groove in described gate dielectric layer further in described first groove, and described grid is arranged in described groove；Farther including an assisted depletion layer, described assisted depletion layer is arranged on described gate dielectric layer and the drain electrode layer intersection in the first trench bottom surfaces, and does not overlaps with described grid on the direction be perpendicular to substrate surface, and described assisted depletion layer has the second conduction type.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of groove power field-effect transistor.
Background technology
Silicon-on-insulator (SOI) is as a kind of preferably medium isolated material, can effectively realize high and low power model, and the isolation between high-low voltage device, thoroughly eliminate electrical interference, simplify the structure design of device, and SOI isolation area area is little compared with junction isolation, is greatly saved die area, reduce parasitic capacitance, can the most integrated different circuit and device.Therefore, SOI technology is applied to high tension apparatus and power integrated circuit has obvious advantage and has wide practical use.
There is silicon Limits properties in conventional high-tension device, is i.e. directly proportional to breakdown voltage 2.5 power than conducting resistance.Superjunction (Super Junction, SJ) structure has broken " the silicon limit " so that device becomes conducting resistance than the relation between conducting resistance to breakdown voltage and is directly proportional to breakdown voltage 1.32 power.For high tension apparatus, the ratio conducting resistance of device, equal to the product of conducting resistance with device area, the therefore size of device area, has vital impact to the ratio conducting resistance of device.At lateral high-voltage device, its conducting resistance is mainly made up of contact resistance, source-drain area resistance, channel resistance, accumulation area resistance and drift zone resistance.Longer drift region and its relatively low doping content so that drift zone resistance proportion shared by lateral high-voltage device conducting resistance is bigger.Trench gate technology make the channel region of high tension apparatus and accumulation area from laterally becoming longitudinally, to reduce channel region and the increase of device area that accumulation area causes.If that the drift region of device can be made also to realize longitudinalization, the lateral high-voltage device realizing Ultra-low Specific conducting resistance had the most important Research Significance.
Summary of the invention
The technical problem to be solved is to provide a kind of high performance groove power field-effect transistor.
In order to solve the problems referred to above, the invention provides a kind of groove power field-effect transistor with insulating buried layer, including: source layer and drain electrode layer, described source layer is arranged on the first surface of substrate, and described drain electrode layer is arranged on the second surface that substrate is relative with first surface；Doping well layer, described doping well layer is arranged between described source layer and drain electrode layer, and fits with described source layer and drain electrode layer, and described source layer and drain electrode layer have the first conduction type, and described doping well layer has the second conduction type；Grid, the first surface of described substrate has one first groove further, fills gate dielectric layer, have one second groove in described gate dielectric layer further in described first groove, and described grid is arranged in described groove；Farther including an assisted depletion layer, described assisted depletion layer is arranged on described gate dielectric layer and the drain electrode layer intersection in the first trench bottom surfaces, and does not overlaps with described grid on the direction be perpendicular to substrate surface, and described assisted depletion layer has the second conduction type.
Optionally, described doping well layer includes by Si in the direction being perpendicular to substrate surface1-xGexThe hetero-junctions that/Si is constituted, wherein x is more than 0 and less than 1.
Optionally, described grid includes the first gate layer and the second gate layer being made up of different materials, and described first gate layer and the second gate layer stack setting on the direction be perpendicular to substrate surface；The material of described first gate layer is N-type polycrystalline silicon, and the material of the second gate layer is p-type polysilicon
Optionally, the material of described source layer is germanium.
Optionally, described first conduction type is N-type, and the second conduction type is p-type.
Optionally, described first conduction type is p-type, and the second conduction type is N-type.
It is an advantage of the current invention that, assisted depletion layer is introduced between drain electrode layer and gate dielectric layer, when being in high-voltage state between source layer and drain electrode layer, assisted depletion layer mutually can exhaust with the drift region of drain electrode layer, play the effect of Double RESURF, both can increase the breakdown voltage of device, it is also possible to use higher drift doping concentration, reduce the ratio conducting resistance of device.
Accompanying drawing explanation
It it is the structural representation of transistor described in the specific embodiment of the invention shown in accompanying drawing 1.
Accompanying drawing 2 is the structural representation of a kind of another kind of detailed description of the invention of the present invention.
Detailed description of the invention
A kind of detailed description of the invention with the groove power field-effect transistor of insulating buried layer provided the present invention below in conjunction with the accompanying drawings elaborates.
It is the structural representation of transistor described in the specific embodiment of the invention shown in accompanying drawing 1, including the source layer 20 in substrate 10, drain electrode layer 30, doping well layer 40 and grid 50.
With continued reference to accompanying drawing 1, described source layer 20 is arranged on the first surface of substrate 10, and described drain electrode layer 30 is arranged on the second surface that substrate 10 is relative with first surface.Described doping well layer 40 is arranged between described source layer 20 and drain electrode layer 30, and fits with described source layer 20 and drain electrode layer 30.In this detailed description of the invention, the conduction type of described source layer 20 and drain electrode layer 30 is N-type, and the conduction type of described doping well layer 40 is p-type.In other detailed description of the invention, above-mentioned conduction type can also exchange.
With continued reference to accompanying drawing 1, the first surface of described substrate 10 has one first groove 61 further, being filled with gate dielectric layer 53 in described first groove 61, have one second groove 62 in described gate dielectric layer 53 further, described grid 50 is arranged in described second groove 62.Described source layer 20 surface has source electrode 71, and described drain electrode layer 30 surface has drain electrode 72, and described grid 50 surface has gate electrode 73, can further include the ohmic contact layer 31 for improving Ohmic contact effect between drain electrode layer 30 and drain electrode 72.In this embodiment, the conduction type of drain electrode layer 30 is N-type, and ohmic contact layer 31 is N-type heavily doped layer.Above-mentioned electrode structure is used for input and the output of electrical signal.
Above-mentioned device is the transistor of a kind of vertical stratification.Grid 50 applies voltage, makes doping well layer 40, near the surface of gate dielectric layer 53, transoid occur, form conducting channel, source layer 20 and drain electrode layer 30 are turned on, thus realizes the switching characteristic of device.In this embodiment, farther include an assisted depletion layer 80, described assisted depletion layer 80 is arranged on described gate dielectric layer 53 and the drain electrode layer 30 intersection in the first groove 61 bottom surface, and does not overlaps with described grid 50 on the direction being perpendicular to substrate 10 surface.Described assisted depletion layer 80 has the second conduction type, i.e. different from the conduction type of drain electrode layer 30.The meaning that assisted depletion layer 80 does not overlaps with described grid 50 on the direction being perpendicular to substrate 10 surface is to prevent electrical signal on grid 50 from the spent condition of assisted depletion layer 80 is produced impact.When being in high-voltage state between source layer 20 and drain electrode layer 30, assisted depletion layer 80 can mutually consume layer to the greatest extent with the drift region of drain electrode layer 30, play the effect of Double RESURF, both the breakdown voltage of device can have been increased, higher drift doping concentration can also be used, reduce the ratio conducting resistance of device.
It is the structural representation of a kind of another kind of detailed description of the invention of the present invention with reference to accompanying drawing 2.As preferred embodiment, described doping well layer 40 includes by Si in the direction being perpendicular to substrate surface1-xGexThe hetero-junctions that layer 41 and Si layer 42 is constituted, wherein x is more than 0 and less than 1.Have an advantage in that, the band structure of hetero-junctions can be adjusted by adjusting the molar percentage of Ge, it is achieved the optimization of device.The material of described source layer 20 is preferably Ge, and doping content is preferably 1 × 1019To 9 × 1020cm-3.Ge can extract the doping well layer 40 hole in the conducting channel near the surface of gate dielectric layer 53, suppression appendage effect and BJT effect effectively.
With continued reference to accompanying drawing 2, as preferred embodiment, described grid 50 can include that the first gate layer 51 and the second gate layer 52 being made up of different materials, described first gate layer 51 and the second gate layer 52 stack setting on the direction being perpendicular to substrate 10 surface.As the optional embodiment of one, the material of described first gate layer 51 is N-type polycrystalline silicon, and the material of the second gate layer 52 is p-type polysilicon, and the doping content scope of the first gate layer 51 and the second gate layer 52 is all 1 × 1019To 5 × 1020cm-3.First gate layer 51 of different materials and the second gate layer 52 can introduce stepped surfaces Potential Distributing in doping well layer 40 in the conducting channel near the surface of gate dielectric layer 53, and then reduce the peak electric field near drain electrode layer 30, guarantee that the average electric field in raceway groove is improved, reduce ohmic leakage, strengthen the grid 50 control ability to channel conduction.
The above is only the preferred embodiment of the present invention; it should be pointed out that, for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (7)
1. a groove power field-effect transistor, it is characterised in that including:
Source layer and drain electrode layer, described source layer is arranged on the first surface of substrate, and described drain electrode layer is arranged on substrate and the first table
The second surface that face is relative；
Doping well layer, described doping well layer is arranged between described source layer and drain electrode layer, and with described source layer and drain laminating
Closing, described source layer and drain electrode layer have the first conduction type, and described doping well layer has the second conduction type；
Grid, the first surface of described substrate has one first groove further, fills gate dielectric layer, institute in described first groove
Stating and have one second groove in gate dielectric layer further, described grid is arranged in described groove；It is characterized in that；
Farther including an assisted depletion layer, described assisted depletion layer is arranged on described gate dielectric layer with drain electrode layer in the first trench bottom
The intersection in face, and do not overlap with described grid on the direction be perpendicular to substrate surface, described assisted depletion layer has second leads
Electricity type.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described doping well layer is being perpendicular to lining
The direction of basal surface includes by Sil-XGeXThe hetero-junctions that/Si is constituted, wherein x is more than 0 and less than 1.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described grid includes by different materials
The first gate layer constituted and the second gate layer, described first gate layer and the second gate layer stack setting on the direction be perpendicular to substrate surface.
Groove power field-effect transistor the most according to claim 3, it is characterised in that the material of described first gate layer is N-type
Polysilicon, the material of the second gate layer is p-type polysilicon.
Groove power field-effect transistor the most according to claim 1, it is characterised in that the material of described source layer is germanium.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described first conduction type is N-type,
Second conduction type is p-type.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described first conduction type is p-type,
Second conduction type is N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310745165.7A CN103745999B (en) | 2013-12-31 | 2013-12-31 | Groove power field-effect transistor with insulating buried layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310745165.7A CN103745999B (en) | 2013-12-31 | 2013-12-31 | Groove power field-effect transistor with insulating buried layer |
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| Publication Number | Publication Date |
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| CN103745999A CN103745999A (en) | 2014-04-23 |
| CN103745999B true CN103745999B (en) | 2016-08-17 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1264158A (en) * | 1998-12-28 | 2000-08-23 | 因芬尼昂技术北美公司 | Autoregistered channel injection |
| CN101897028A (en) * | 2007-12-13 | 2010-11-24 | 飞兆半导体公司 | Structure and method for forming field effect transistor with low resistance channel region |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8008144B2 (en) * | 2006-05-11 | 2011-08-30 | Micron Technology, Inc. | Dual work function recessed access device and methods of forming |
| JP2008108962A (en) * | 2006-10-26 | 2008-05-08 | Toshiba Corp | Semiconductor device |
| JP2011199000A (en) * | 2010-03-19 | 2011-10-06 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1264158A (en) * | 1998-12-28 | 2000-08-23 | 因芬尼昂技术北美公司 | Autoregistered channel injection |
| CN101897028A (en) * | 2007-12-13 | 2010-11-24 | 飞兆半导体公司 | Structure and method for forming field effect transistor with low resistance channel region |
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| CN103745999A (en) | 2014-04-23 |
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