CN103745998B - Groove power field-effect transistor - Google Patents
Groove power field-effect transistor Download PDFInfo
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- CN103745998B CN103745998B CN201310745065.4A CN201310745065A CN103745998B CN 103745998 B CN103745998 B CN 103745998B CN 201310745065 A CN201310745065 A CN 201310745065A CN 103745998 B CN103745998 B CN 103745998B
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- layer
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- effect transistor
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- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000005457 optimization Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
- 229910007020 Si1−xGex Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a kind of groove power field-effect transistor, including: source layer and drain electrode layer, described source layer is arranged on the first surface of substrate, and described drain electrode layer is arranged on the second surface that substrate is relative with first surface；Doping well layer, described doping well layer is arranged between described source layer and drain electrode layer, and fits with described source layer and drain electrode layer, and described source layer and drain electrode layer have the first conduction type, and described doping well layer has the second conduction type；Grid, the first surface of described substrate has a groove further, and described trench wall is coated with gate dielectric layer, and described grid is in the space that described gate dielectric layer is crowded around；Described doping well layer includes by Si in the direction being perpendicular to substrate surface1‑xGexThe hetero-junctions that/Si is constituted.It is an advantage of the current invention that the band structure that can adjust hetero-junctions by adjusting the molar percentage of Ge, it is achieved the optimization of device.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of groove power field-effect transistor.
Background technology
Trench gate structure is the most own through being applied in DMOS device and achieving commercialization as far back as the mid-90, referred to as UMOS device.UMOS device has higher groove density and relatively low leakage diffusion resistance, extremely low with its ON state featured resistance.Trench gate is commonly used on VDMOSFET device, is mainly due to trench gate and introduces internal consistent with the current direction of vertical structure by channel current from device surface.This structure can also improve breakdown voltage value, trench gate can well control channel length simultaneously, reduce hot carrier's effect, reduce the drift of threshold voltage, the most this device architecture can improve saturation region characteristic, improve the linearity of transfer characteristic curve, thus improve reliability and the life-span of device.
Summary of the invention
The technical problem to be solved is to provide a kind of high performance groove power field-effect transistor.
In order to solve the problems referred to above, the invention provides a kind of groove power field-effect transistor, including: source layer and drain electrode layer, described source layer is arranged on the first surface of substrate, and described drain electrode layer is arranged on the second surface that substrate is relative with first surface；Doping well layer, described doping well layer is arranged between described source layer and drain electrode layer, and fits with described source layer and drain electrode layer, and described source layer and drain electrode layer have the first conduction type, and described doping well layer has the second conduction type；Grid, the first surface of described substrate has a groove further, and described trench wall is coated with gate dielectric layer, and described grid is in the space that described gate dielectric layer is crowded around；Described doping well layer includes by Si in the direction being perpendicular to substrate surface1-xGexThe hetero-junctions that/Si is constituted, wherein x is more than 0 and less than 1.
Optionally, described grid includes the first gate layer and the second gate layer being made up of different materials, and described first gate layer and the second gate layer stack setting on the direction be perpendicular to substrate surface；The material of described first gate layer is N-type polycrystalline silicon, and the material of the second gate layer is p-type polysilicon.
Optionally, the material of described source layer is germanium.
Optionally, described first conduction type is N-type, and the second conduction type is p-type.
Optionally, described first conduction type is p-type, and the second conduction type is N-type.
It is an advantage of the current invention that described doping well layer includes by Si in the direction being perpendicular to substrate surface1-xGexThe hetero-junctions that layer and Si layer are constituted, can adjust the band structure of hetero-junctions, it is achieved the optimization of device by adjusting the molar percentage of Ge.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of transistor described in the specific embodiment of the invention.
Accompanying drawing 2 is the structural representation of a kind of another kind of detailed description of the invention of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of a kind of groove power field-effect transistor that the present invention provides is elaborated.
It is the structural representation of transistor described in the specific embodiment of the invention shown in accompanying drawing 1, including the source layer 20 in substrate 10, drain electrode layer 30, doping well layer 40 and grid 50.
With continued reference to accompanying drawing 1, described source layer 20 is arranged on the first surface of substrate 10, and described drain electrode layer 30 is arranged on the second surface that substrate 10 is relative with first surface.Described doping well layer 40 is arranged between described source layer 20 and drain electrode layer 30, and fits with described source layer 20 and drain electrode layer 30.In this detailed description of the invention, the conduction type of described source layer 20 and drain electrode layer 30 is N-type, and the conduction type of described doping well layer 40 is p-type.In other detailed description of the invention, above-mentioned conduction type can also exchange.
With continued reference to accompanying drawing 1, the first surface of described substrate 10 has a groove 60 further, and described groove 60 inwall is coated with gate dielectric layer 53, and described grid 50 is in the space that described gate dielectric layer 53 is crowded around.Described source layer 20 surface has source electrode 71, and described drain electrode layer 30 surface has drain electrode 72, and described grid 50 surface has gate electrode 73, can further include the ohmic contact layer 31 for improving Ohmic contact effect between drain electrode layer 30 and drain electrode 72.In this embodiment, the conduction type of drain electrode layer 30 is N-type, and ohmic contact layer 31 is N-type heavily doped layer.Above-mentioned electrode structure is used for input and the output of electrical signal.
Above-mentioned device is the transistor of a kind of vertical stratification.Grid 50 applies voltage, makes doping well layer 40, near the surface of gate dielectric layer 53, transoid occur, form conducting channel, source layer 20 and drain electrode layer 30 are turned on, thus realizes the switching characteristic of device.In this embodiment, described doping well layer 40 includes by Si in the direction being perpendicular to substrate surface1-xGexThe hetero-junctions that layer 41 and Si layer 42 is constituted, wherein x is more than 0 and less than 1.Have an advantage in that, the band structure of hetero-junctions can be adjusted by adjusting the molar percentage of Ge, by changing Si1-xGexLayer and Si layer conduction band and valence band difference, reduce electronics and by the potential barrier in source electrode to raceway groove and make source electrode be easier to extract the hole in raceway groove simultaneously, reduce parasitic bipolar transistor effect and the floater effect of device, it is achieved the optimization of device.
The material of described source layer 20 is preferably Ge, and doping content is preferably 1 × 1019~1×1020cm-3
.Ge can extract the doping well layer 40 hole in the conducting channel near the surface of gate dielectric layer 53, suppression appendage effect and BJT effect effectively.
It is the structural representation of a kind of another kind of detailed description of the invention of the present invention with reference to accompanying drawing 2.As preferred embodiment, described grid 50 can include that the first gate layer 51 and the second gate layer 52 being made up of different materials, described first gate layer 51 and the second gate layer 52 stack setting on the direction being perpendicular to substrate 10 surface.As the optional embodiment of one, the material of described first gate layer 51 is N-type polycrystalline silicon, and the material of the second gate layer 52 is p-type polysilicon, and p-type N-type polycrystalline silicon all uses the heavy doping, doping content scope to be: 1 × 1019~1×1021cm-3.First gate layer 51 of different materials and the second gate layer 52 can introduce stepped surfaces Potential Distributing in doping well layer 40 in the conducting channel near the surface of gate dielectric layer 53, and then reduce the peak electric field near drain electrode layer 30, guarantee that the average electric field in raceway groove is improved, reduce ohmic leakage, strengthen the grid 50 control ability to channel conduction.
The above is only the preferred embodiment of the present invention; it should be pointed out that, for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (6)
1. a groove power field-effect transistor, including:
Source layer and drain electrode layer, described source layer is arranged on the first surface of substrate, and described drain electrode layer is arranged on substrate and the first table
The second surface that face is relative；
Doping well layer, described doping well layer is arranged between described source layer and drain electrode layer, and with described source layer and drain laminating
Closing, described source layer and drain electrode layer have the first conduction type, and described doping well layer has the second conduction type；
Grid, the first surface of described substrate has a groove further, and described trench wall is coated with gate dielectric layer, described grid
Pole is in the space that described gate dielectric layer is crowded around；It is characterized in that:
Described doping well layer includes by Si in the direction being perpendicular to substrate surfaceL mono-XGeXThe hetero-junctions that/Si is constituted, wherein x is more than
0 and less than 1, described SiL mono-XGeXLayer directly with described source contact.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described grid includes by different materials
First gate layer of material composition and the second gate layer, described first gate layer and the second gate layer stack on the direction be perpendicular to substrate surface and set
Put.
Groove power field-effect transistor the most according to claim 2, it is characterised in that the material of described first gate layer is
N-type polycrystalline silicon, the material of the second gate layer is p-type polysilicon.
Groove power field-effect transistor the most according to claim 1, it is characterised in that the material of described source layer is germanium.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described first conduction type is N
Type, the second conduction type is p-type.
Groove power field-effect transistor the most according to claim 1, it is characterised in that described first conduction type is P
Type, the second conduction type is N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310745065.4A CN103745998B (en) | 2013-12-31 | 2013-12-31 | Groove power field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310745065.4A CN103745998B (en) | 2013-12-31 | 2013-12-31 | Groove power field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103745998A CN103745998A (en) | 2014-04-23 |
| CN103745998B true CN103745998B (en) | 2016-10-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310745065.4A Active CN103745998B (en) | 2013-12-31 | 2013-12-31 | Groove power field-effect transistor |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101897028A (en) * | 2007-12-13 | 2010-11-24 | 飞兆半导体公司 | Structure and method for forming field effect transistor with low resistance channel region |
| CN102165594A (en) * | 2008-09-29 | 2011-08-24 | 飞兆半导体公司 | Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6828628B2 (en) * | 2003-03-05 | 2004-12-07 | Agere Systems, Inc. | Diffused MOS devices with strained silicon portions and methods for forming same |
| US8008144B2 (en) * | 2006-05-11 | 2011-08-30 | Micron Technology, Inc. | Dual work function recessed access device and methods of forming |
-
2013
- 2013-12-31 CN CN201310745065.4A patent/CN103745998B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101897028A (en) * | 2007-12-13 | 2010-11-24 | 飞兆半导体公司 | Structure and method for forming field effect transistor with low resistance channel region |
| CN102165594A (en) * | 2008-09-29 | 2011-08-24 | 飞兆半导体公司 | Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate |
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| Publication number | Publication date |
|---|---|
| CN103745998A (en) | 2014-04-23 |
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