CN103745934B

CN103745934B - Wafer-level packaging method

Info

Publication number: CN103745934B
Application number: CN201310746188.XA
Authority: CN
Inventors: 蒋珂玮
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2016-08-24
Anticipated expiration: 2033-12-30
Also published as: CN103745934A

Abstract

The present invention relates to a kind of wafer-level packaging method, described method for packing includes: providing the multiple wafers being categorized as at least two classification, multiple wafers of each classification are respectively provided with the multiple samples comprising at least one wafer；Sample for each classification carries out chip probing test respectively, obtains the wafer figure of sample respectively；In conjunction with wafer figure, and the inefficacy that comparison is preset divides threshold value, distinctly displays effective chip unit and invalid chip unit；Combinations matches before being packaged different classes of sample, obtains the optimum matching method that effective chip unit combines；According to described optimum matching method, different classes of wafer is carried out wafer-level packaging.

Description

Wafer-level packaging method

Technical field

The present invention relates to wafer level packaging field, particularly to a kind of wafer-level packaging method.

Background technology

Wafer-level packaging (wafer level package, WLP) refers to complete encapsulation system on wafer Journey, its have significantly reduce encapsulating structure area, reduce manufacturing cost electrical property, excellent batch The advantages such as manufacture, can significantly reduce the demand of workload and equipment.The encapsulation side of prior art Method its be wafer is carried out wire weight cloth (redistribution) after, multiple wafer vertical stackings glue Close (wafer to wafer, W2W), then section forms the IC that 3D is integrated.

The method low cost of manufacture, has the biggest advantage, but can introduce a yield simultaneously and refer to The problem that number declines.Such as: if the yield of a piece of wafer is 90%, another sheet also 90%, So after two panels bonding, the yield of chip will be slightly over 90%*90%=81% (because wherein can Have the chip failing fail die that portion is overlapping), this will make originally by W2W technology The cost reduced has risen because of yield loss again.

In sum, it is provided that a kind of solve above-mentioned cause due to encapsulation yield reduce problem crystalline substance Circle level packaging methods, becomes those skilled in the art's problem demanding prompt solution.

Be disclosed in that the information of this background of invention technology segment is merely intended to deepen to the present invention is general The understanding of background technology, and be not construed as recognizing or implying this information structure in any form Prior art the most known to those skilled in the art.

Summary of the invention

For solving above-mentioned problems of the prior art, the purpose of the present invention is for providing a kind of excellent The wafer-level packaging method changed.

In order to achieve the above object, the present invention provides a kind of wafer-level packaging method, described encapsulation Method includes: A) provide and be categorized as multiple wafers of at least two classification, each classification multiple Wafer is respectively provided with the multiple samples comprising at least one wafer；B) for the sample difference of each classification Carry out chip probing test, obtain the wafer figure of sample respectively；C) combine wafer figure, and compare Default inefficacy is divided threshold value, distinctly displays effective chip unit and invalid chip unit；D) Combinations matches before being packaged different classes of sample, obtains what effective chip unit combined Optimum matching method；E) according to described optimum matching method, different classes of wafer is carried out crystalline substance Circle level encapsulation.

Preferably, described at least two classification is A, B ... Φ, the number of wherein said classification Amount is N, wherein N 2；Sample A1, A2 in described A classification ..., the nothing that An is corresponding Effect chip unit quantity is a1, a2 ..., an, wherein a1 to an is more than or equal to 0 Integer；Sample B1, B2 in described B classification ..., the invalid chip unit that Bn is corresponding Quantity is b1, b2 ..., bn, wherein b1 to bn is the integer more than or equal to 0.

Preferably, described step D) in, form multiple matched group, Mei Gepei after combinations matches The invalid chip unit quantity of group is respectively c1, c2 ..., cn, wherein, c1 to cn is Integer more than or equal to 0, the pairing encapsulation yield of described each matched group is respectively Y1, Y2 ..., Yn, the encapsulation yield Yn and overall package yield Ya of each matched group are by following Formula calculates: Yn=(Na-cn)/Na*100%；Ya=(Y1+Y2+ ...+Yn)/n*100%； Wherein, Na is the encapsulation number of chips in each matched group, and n is the quantity of matched group；Institute State step D) optimum matching method be: make described overall package yield Ya reach maximum Matching method.

Preferably, described step E) in, also include: by sample in described classification for another kind of After sample corresponding rotation in not 180 degree, by the front of the sample in a described classification and another In classification, sample front carries out bonding encapsulation.

Preferably, described step E) in, also include: directly by the sample in a described classification Sample reverse side in front and another category carries out bonding encapsulation.

Preferably, the sample in a described classification and the sample in another category are brilliant by least one Circle composition.

Preferably, described inefficacy divides threshold value and includes: described chip is divided into two grades: Chip failing and non-chip failing.

Preferably, the described division threshold value that lost efficacy can farther include: is drawn by described chip failing It is divided into two grades: the direct current failure level of the first order and the disabler grade of the second level.

Preferably, described step D) farther include: the first direct current inefficacy etc. to the first order Level carries out step D) in pairing process thus obtain first order optimum matching method, then to the The disabler grade of two grades carries out step D) pairing process thus obtain second level optimum and join To mode.

Preferably, according to described first order optimum matching method according to step E) carry out bonding encapsulation； According to described second level optimum matching method according to step E) carry out bonding encapsulation.

The invention has the beneficial effects as follows: the present invention increases by one after chip probing test and screened Journey, carries out permutation and combination by computer optimization mode and matches with the optimization reaching chip, and The position carrying out rearranged portions wafer accordingly is packaged, thus reaches to promote yield, reduce cost And improve the purpose of the market competitiveness.

Accompanying drawing explanation

By Figure of description and be used for subsequently illustrating together with Figure of description the present invention some The detailed description of the invention of principle, further feature that the present invention is had and advantage will be clear from or More specifically illustrated.

Fig. 1 is the sample A1 warp of the kind A wafer of the wafer-level packaging method according to the present invention Cross the wafer figure after chip probing test.

Figure 1A is the sample A2 warp of the kind A wafer of the wafer-level packaging method according to the present invention Cross the wafer figure after chip probing test.

Fig. 2 is that the sample B1 of the kind B wafer of the wafer-level packaging method according to the present invention passes through Wafer figure after chip probing test.

Fig. 2 A is the sample B2 warp of the kind B wafer of the wafer-level packaging method according to the present invention Cross the wafer figure after chip probing test.

Fig. 3 is the wafer frontside-front encapsulation signal of the wafer-level packaging method according to the present invention Figure.

Fig. 4 is the wafer reverse side-front encapsulation signal of the wafer-level packaging method according to the present invention Figure.

Fig. 5 is the wafer-level packaging method flow chart according to the present invention.

It is to be appreciated that Figure of description shows the concrete structure of the present invention with being not necessarily to scale, And for illustrating that the n-lustrative feature of some principle of the present invention also can be taked in Figure of description The technique of painting slightly simplified.The specific design feature of invention disclosed herein includes the most concrete Size, direction, position and profile will partly be come really by the environment specifically applied and to use Fixed.

In several accompanying drawings of Figure of description, identical reference represents that the present invention's is identical Or the part of equivalent.

Critical piece symbol description:

The sample A1 of a kind A wafer

The sample A2 of 2 kind A wafers

The sample B1 of 3 kind B wafers

The sample B2 of 4 kind B wafers

5 kind A wafer frontside

6 kind A wafer reverse side

7 kind B wafer frontside

8 kind B wafer reverse side.

Detailed description of the invention

Elaborate a lot of detail in the following description so that fully understanding the present invention.But It is that the present invention can implement to be much different from alternate manner described here, art technology Personnel can do similar popularization in the case of intension of the present invention, and therefore the present invention is not subject to The restriction of following public specific embodiment.

Below, in conjunction with accompanying drawing, the specific embodiment of the present invention is described.Refer to Fig. 5 institute Showing, the present invention provides a kind of wafer-level packaging method.

The method for packing of the present invention comprises the following steps:

A) offer is categorized as multiple wafers of at least two classification, and multiple wafers of each classification are equal There are the multiple samples comprising at least one wafer；

B) sample for each classification carries out chip probing test respectively, obtains sample respectively Wafer figure；

C) combine wafer figure, and the inefficacy that comparison is preset divides threshold value, distinctly displays effective chip Unit and invalid chip unit；

D) combinations matches before being packaged different classes of sample, obtains effective chip unit In conjunction with optimum matching method；

E) according to described optimum matching method, different classes of wafer is carried out wafer-level packaging.

In the wafer-level packaging method of the present invention, the classification of the wafer provided is at least two kinds, E.g. two classifications of A, B；Can also be multiple, appointing between e.g. 4 kinds to 10 kinds One numerical value, further, the e.g. wafer of tetra-classifications of A, B, C, D.It addition, it is every The wafer of one kind all comprises multiple sample, each sample comprises at least one wafer, Can also comprise multiple wafer, any value in e.g. 4 to 25, further, Classification A wafer e.g. comprises 4 samples A1, A2, A3, A4, classification A wafer Each sample all comprises 25 wafers；Classification B wafer also comprises 4 sample B1, B2, B3, B4, each sample of classification B wafer all comprises 25 wafers.No matter it is to provide multiple The wafer of classification or each classification comprise several samples or each sample comprise many Individual wafer, the principle of a combination thereof coupling and (two kinds in embodiment to be described in detail below Not, every kind comprises two samples, and each sample comprises 1 wafer) permutation and combination former Reason is just as, and is the most all to be obtained by the total encapsulation yield after calculating combinations matches To required combination.

In an embodiment of the present invention, according to step A), first two kinds of wafer classifications are provided, It is kind A (hereinafter referred to as kind A) and another kind of classification B (hereinafter referred to as kind B). As shown in Fig. 1, Figure 1A, Fig. 2 and Fig. 2 A, kind A comprises two samples, respectively For sample A1 and sample A2, the sample A1 and sample A2 of kind A respectively comprises 1 wafer, Chip count amount N on each wafer is 21；Similarly, kind B also comprises sample B1 and sample B2, respectively comprises 1 wafer, often in the sample B1 and sample B2 of kind B Chip count amount N on individual wafer is 21.

Then according to step B) and step C), in conjunction with obtain after above-mentioned chip probing test Sample wafer figure, and comparison preset inefficacy divide threshold value, distinctly display effective chip unit and Invalid chip unit.The present embodiment divides threshold value, the setting of this threshold value for default inefficacy It is that chip is divided into non-chip failing and chip failing, the most corresponding above-mentioned effective chip unit With invalid chip unit.

Specifically, as shown in Fig. 1, Figure 1A, Fig. 2 and Fig. 2 A, wherein Fig. 1 and Figure 1A The two panels sample A1 of kind A wafer and A2 warp for the wafer-level packaging method according to the present invention Cross the wafer figure after chip probing test, and Fig. 2 and Fig. 2 A is the wafer scale envelope according to the present invention Two panels sample B1 and B2 of the kind B wafer of dress method wafer after chip probing test Figure.The chip of the black shade mark in Fig. 1, Figure 1A, Fig. 2 and Fig. 2 A is for passing through Invalid invalid chip unit namely chip failing it is defined as after chip probing test, and remaining Chip without color lump mark is effective chip unit namely non-chip failing.

It can thus be seen that invalid chip unit quantity a1 of sample A1 and sample A2's is invalid Chip unit quantity a2 is 2, i.e. a1=a2=2, and the invalid chip unit quantity of sample B1 Invalid chip unit quantity b2 of b1 and sample B2 is also 2, i.e. b1=b2=2.Thus may be used With calculate the yield Ya1 of sample A1, the yield Ya2 of sample A2, sample B1 good The yield Yb2 of rate Yb1 and sample B2, it calculates by below equation:

Ya1=(N-a1)/N*100%；

Ya2=(N-a2)/N*100%；

Yb1=(N-b1)/N*100%；

Yb2=(N-b2)/N*100%；

Wherein N is the chip count amount on each wafer.

Then draw Ya1=Ya2=Yb1=Yb2=(21-2)/21*100%=90.5%,

Then according to step D), it is combined coupling between four wafers of these four samples, Specifically being obtained in that two kinds of combinations matches modes, each combinations matches mode can form 2 Individual matched group, combination is respectively as follows: sample A1 sample B1 (matched group 1) and sample A2 sample B2 (matched group 2) or sample A1 sample B2 (matched group 11) and sample Product A2 sample B1 (matched group 22).

In the present embodiment, what the encapsulation adhesion between two groups of wafers was taked is the bonding in front-front Mode, as it is shown on figure 3, i.e. the wafer in kind A and the wafer in kind B are with faced by just The mode in front mutually bonds, and therefore during actual adhesion, two wafer to kind A are carried out Upset, bonds with the wafer in kind B after corresponding rotation 180 degree.

Based on above-mentioned front-front adhesive mode, for the first combinations matches mode: sample A1 sample B1 (matched group 1) and sample A2 sample B2 (matched group 2), at sample When A1 bonds with sample B1 after turning over turnback again, the chip failing on the wafer of two samples Unit is misaligned, the most not on same position, bonds with sample B2 after sample A2 upset Also it is same situation, therefore invalid chip unit quantity c1 of matched group 1 after coupling and joining Invalid chip unit quantity c2 of group 2 is 4, i.e. c1=c2=4, matched group 1 and pairing The pairing encapsulation yield of group 2 is respectively Y1 and Y2, below equation calculate:

Y1=(Na-c1)/Na*100%；

Y2=(Na-c2)/Na*100%；

Overall package yield Ya is calculated by below equation:

Ya=(Y1+Y2)/n*100%；

Wherein, Na is the encapsulation number of chips in each matched group, its actually with encapsulation before Chip count amount N on each wafer is identical, and n is the quantity of matched group, is 2 herein.

Then draw Y1=Y2=(21-4)/21*100%=81%, overall package yield Ya= (81%+81%)/2*100%=81%.

For the second combinations matches mode: sample A1 sample B2 (matched group 11) and sample Product A2 sample B1 (matched group 22), sample A1 overturn after 180 degree again with sample B2 During bonding, the chip failing unit on the wafer of two samples is to overlap, i.e. at same position On, the situation as when bonding with sample B1 after sample A2 upset being also, therefore after coupling Invalid chip unit quantity c11 of matched group 11 and the invalid chip unit number of matched group 22 Amount c22 is 2, i.e. c11=c22=2, the pairing encapsulation yield of matched group 11 and matched group 22 It is respectively Y11 and Y22, below equation calculates:

Y11=(Na-c11)/Na*100%；

Y22=(Na-c22)/Na*100%；

Overall package yield Ya is calculated by below equation:

Ya=(Y11+Y22)/n*100%；

Wherein, N is the encapsulation number of chips in each matched group, its actually with encapsulation before Chip count amount N on each wafer is identical, and n is matched group quantity, is 2 herein.

Then draw Y11=Y22=(21-2)/21*100%=90.5%, overall package yield Ya= (90.5%+90.5%)/2*100%=90.5%.

Calculating based on above-mentioned yield, it can be seen that the second combinations of pairs mode is joined than the first Invalid chip unit after encapsulating combination generally is less, namely effective chip unit is more Many, thus the overall package yield Ya obtained is bigger, therefore the second combinations of pairs mode is more Alright, it is the optimum matching method that the effective chip unit described in the present embodiment combines, connects Get off according to step E), according to this optimum matching method to the wafer in kind A and kind B Carry out wafer-level packaging.

More than enumerate is to comprise two samples and every in the wafer of two kinds, every kind The situation of only one of which wafer in individual sample, relevant according to permutation and combination of the prior art is known Knowledge can also be easy to spread in the wafer of plurality of classes or each classification and comprises multiple sample Product or each sample comprise the various situations of multiple wafer, its computational methods and principle and Above-described embodiment is identical.

It addition, the encapsulation adhesion between two groups of wafers can also take the bonding mode in reverse side-front, As shown in Figure 4, i.e. the wafer in kind A and the wafer in kind B with reverse side to front Mode mutually bonds, then during actual adhesion, two wafer to kind A are made without turning over Then the wafer in direct kind B bonds.By combinations of the above mode and its yield meter The method calculated can easily draw, for the bonding mode in this reverse side-front, then the first is joined It it is optimum matching method to combination.Sum it up, be so that bonding is overall after encapsulating Invalid chip unit quantity minimize, overall Yield lmproved can be made.

And, in the case of in order to describe chip behavior more meticulously, chip failing also may be used To carry out grade separation further, e.g. direct current lost efficacy and disabler etc., the most above-mentioned nothing Effect chip unit can also be further divided into different grades of invalid chip unit, and e.g. the The direct current failure level of one-level and the disabler grade of the second level, in this case, then first First the direct current failure level of the first order is carried out step D) in pairing process thus obtain first The optimum matching method of level, then the disabler grade of the second level is carried out step D) pairing Journey thus obtain second level optimum matching method, and according to first order optimum matching method according to Step E) carry out bonding encapsulation or according to second level optimum matching method according to step E) carry out Bonding encapsulation.

The principle of being illustrative for property of above-described embodiment explanation present invention and effect thereof, but this Bright it is not limited to above-mentioned embodiment.Those skilled in the art all can be without prejudice to the present invention's Under spirit and the scope, in claims, above-described embodiment is modified.Cause This protection scope of the present invention, should cover such as claims of the present invention.

Claims

1. a wafer-level packaging method, described method for packing includes:

E) according to described optimum matching method, different classes of wafer is carried out wafer-level packaging；

Described step D) in, form multiple matched group, the nothing of each matched group after combinations matches Effect chip unit quantity be respectively c1, c2 ..., cn, wherein, c1 to cn be more than or Integer equal to 0, the pairing encapsulation yield of described each matched group is respectively Y1, Y2 ..., Yn, the encapsulation yield Yn and overall package yield Ya of each matched group are calculated by below equation Draw:

Yn=(Na-cn)/Na*100%；

Ya=(Y1+Y2+ ...+Yn)/n*100%；

Wherein, Na is the encapsulation number of chips in each matched group, and n is the quantity of matched group；

Described step D) optimum matching method be: described overall package yield Ya is reached Maximum matching method.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described At least two classification is A, B ... Φ, and the quantity of classification is N, wherein N 2；

Sample A1, A2 in described A classification ..., the invalid chip unit quantity that An is corresponding For a1, a2 ..., an, wherein a1 to an is the integer more than or equal to 0；Described B classification in sample B1, B2 ..., invalid chip unit quantity corresponding for Bn is b1, b2 ..., Bn, wherein b1 to bn is the integer more than or equal to 0.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described step Rapid E) in, also include: by sample in a classification for the sample corresponding rotation in another category After 180 degree, sample front in the front of the sample in a classification and another category is carried out bonding envelope Dress.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described step Rapid E) in, also include: the sample in the direct front by the sample in a classification and another category Reverse side carries out bonding encapsulation.

Wafer-level packaging method the most according to claim 1, it is characterised in that: a classification In sample and sample in another category be made up of at least one wafer respectively.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described mistake Effect divides threshold value and includes: described chip is divided into two grades: chip failing and not losing efficacy Chip.

Wafer-level packaging method the most according to claim 6, it is characterised in that: described mistake Effect divides threshold value and can farther include: described chip failing is divided into two grades: first The direct current failure level of level and the disabler grade of the second level.

Wafer-level packaging method the most according to claim 7, it is characterised in that: described step Rapid D) farther include: first the direct current failure level of the first order is carried out step D) in Pairing process thus obtain first order optimum matching method, then the disabler grade to the second level Carry out step D) pairing process thus obtain second level optimum matching method.

Wafer-level packaging method the most according to claim 8, it is characterised in that: according to institute State first order optimum matching method according to step E) carry out bonding encapsulation；According to the described second level Excellent matching method is according to step E) carry out bonding encapsulation.