CN102759697B - Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method - Google Patents
Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method Download PDFInfo
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- CN102759697B CN102759697B CN201210261950.0A CN201210261950A CN102759697B CN 102759697 B CN102759697 B CN 102759697B CN 201210261950 A CN201210261950 A CN 201210261950A CN 102759697 B CN102759697 B CN 102759697B
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Abstract
The invention provides a method for testing the package level of a metal oxide semiconductor (MOS) transistor and an MOS transistor manufacturing method. The method for testing the package level of the MOS transistor comprises the following steps of: firstly, inserting the MOS transistor into a package test slot; secondly, inputting test sample signals; thirdly, checking parasitic equivalent diodes among pins, and judging whether the MOS transistor corresponds to the pins of the package test slot; and finally, directly ending the flow under the condition that the MOS transistor does not correspond to the pins of the package test slot. According to the method, a MOS transistor device can be effectively prevented from being broken through and damaged due to errors of connection excitation by checking the parasitic equivalent diodes among the pins of the MOS transistor device and judging correct pin definitions according to check values of the parasitic equivalent diodes.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of test of MOS transistor package level
The MOS transistor manufacture method of method and the MOS transistor package level method of testing of having sampled.
Background technology
Semiconductor devices（Such as power MOS transistor）Constantly the direction towards high integration and high power capacity is developed.
In semiconductor device design, the yield rate of chip is generally improved using various error checking and correction repairing method.
Integrated circuit（IC）Measuring technology, according to the different phase that IC is manufactured, is divided into chip testing（Wafer Sort or
CIRCUIT Probe）With package level test（Final test, FT, also referred to as survey, finished product test or packaging and testing eventually）Two kinds.
The former is that the crystal grain carried out when product is still in the wafer fabrication stage with probe is tested.
Package level test is performed after IC package, and the function and specification for determining IC finished products meets the requirements, be divided into again
The content such as testing electrical property and mechanicalness test.And according to the species of IC products, test is divided into MEMTEST and the test of logic IC etc. again,
IC pin numbers are more, measuring technology also more high-order.
Typically, in the package level test of MOS transistor, need MOS transistor to be prevented in packaging and testing slot（FT
socket）In, test MOS transistor will pass through applying test signal.
But, for different device detection factories, the definition to each port in packaging and testing slot is different.Tool
Say, Fig. 1 schematically shows an example of the pin definition of packaging and testing slot body.As shown in figure 1, for certain device
Part tests factory, and its pin from left to right is respectively defined as grid G 1, drain D 1 and source S 1.Meanwhile, Fig. 2 is schematically
Show another example of the pin definition of packaging and testing slot.As shown in Fig. 2 coming possibly for another device detection factory
Say, its pin from left to right is respectively defined as drain D 2, source S 2, grid G 2.
Therefore, in the case where not knowing that concrete pin is defined, it is impossible to correct line excitation is carried out, consequently, it is possible to causing
Signal inputs port by mistake, so as to cause device failure.Such as punch through damage.
Accordingly, it is desirable to be able to provide it is a kind of can be effectively prevented from due to line excitation mistake and make MOS transistor device
The MOS transistor package level method of testing of the breakdown damage of part.
The content of the invention
The technical problem to be solved is to be directed in prior art to there is drawbacks described above, there is provided one kind can be effective
Avoid due to line excitation mistake and make the breakdown damage of MOS transistor device MOS transistor package level method of testing,
And the MOS transistor manufacture method of the MOS transistor package level method of testing of having sampled.
According to the first aspect of the invention, there is provided a kind of MOS transistor package level method of testing, it includes：First will
MOS transistor inserts packaging and testing slot；Hereafter input test sample signal；Subsequently check parasitic equivalent two between each pin
Pole pipe, and judge whether MOS transistor is corresponding with the pin of the packaging and testing slot for being inserted；And judging MOS transistor
In the case of not corresponding with the pin of the packaging and testing slot for being inserted, directly terminate flow process.
Preferably, in above-mentioned MOS transistor package level method of testing, wherein using plus stream pressure measurement come check each pin it
Between parasitic equivalent diode.
Preferably, it is parasitic equivalent between each pin of the inspection in above-mentioned MOS transistor package level method of testing
In the step of diode, grid leak test electric current is added between the grid of MOS transistor and drain electrode, and measure grid and drain electrode
Between voltage, with check MOS transistor device grid and drain electrode between parasitic equivalent diode；In MOS transistor
Test electric current in grid source is added between grid and source electrode, and measures the voltage between grid and source electrode, to check MOS transistor device
Parasitic equivalent diode between the grid and source electrode of part；Source and drain test electricity is added between source and drain in a mos transistor
Stream, and the voltage between source electrode and drain electrode is measured, it is parasitic equivalent between the source electrode of MOS transistor device and drain electrode to check
Diode.
Preferably, it is parasitic equivalent between each pin of the inspection in above-mentioned MOS transistor package level method of testing
In the step of diode, according to the voltage between the grid that measures and drain electrode, the voltage between grid and source electrode and source electrode and
Voltage between drain electrode is judging whether MOS transistor is corresponding with the pin of the packaging and testing slot for being inserted.
Preferably, in above-mentioned MOS transistor package level method of testing, in the encapsulation for judging MOS transistor Yu inserted
In the case of the pin of test socket is not corresponding, after flow process is terminated, the packaging and testing slot of MOS transistor insertion is changed
Mode, repeats afterwards the MOS transistor package level method of testing.
Preferably, in above-mentioned MOS transistor package level method of testing, the MOS transistor package level method of testing is used
Test in the package level of power MOS transistor.
According to the second aspect of the invention, there is provided a kind of MOS described according to the first aspect of the invention that sampled is brilliant
The MOS transistor manufacture method of body pipe package level method of testing.
According to the present invention it is possible to pass through to check the parasitic equivalent diode between each pin of MOS transistor device, according to
The test value of parasitic equivalent diode carrys out judicious pin definition, it is possible thereby to be effectively prevented from due to the mistake of line excitation
Make the breakdown damage of MOS transistor device by mistake.
Description of the drawings
With reference to accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows an example of the pin definition of packaging and testing slot.
Fig. 2 schematically shows another example of the pin definition of packaging and testing slot.
Fig. 3 schematically shows the flow chart of MOS transistor package level method of testing according to embodiments of the present invention.
Fig. 4 schematically shows the situation of the parasitic equivalent diode of NMOS.
It should be noted that accompanying drawing is used to illustrate the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Also, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 3 schematically shows the flow chart of MOS transistor package level method of testing according to embodiments of the present invention.
After MOS transistor to be inserted packaging and testing slot, input test sample signal first（Step ST1）.
Hereafter, the parasitic equivalent diode between each pin is checked, and judges whether by test, that is, to judge MOS crystal
Whether pipe is corresponding with the pin of the packaging and testing slot for being inserted（Step ST2）.
Specifically, in step ST2, such as available plus stream pressure measurement（Force current and measure
Voltage, writes a Chinese character in simplified form FIMV）To check the parasitic equivalent diode between each pin, i.e., introduce between the pin of each two pole
Electric current, and measure the voltage between the two poles.
More specifically, in step ST2, grid leak test electricity can be added between the grid of MOS transistor and drain electrode
Stream, and the voltage between grid and drain electrode is measured, it is parasitic equivalent between the grid of MOS transistor device and drain electrode to check
Diode；Test electric current in grid source is added between the grid and source electrode of MOS transistor, and measures the electricity between grid and source electrode
Pressure, to check the parasitic equivalent diode between the grid of MOS transistor device and source electrode；Source electrode and leakage in MOS transistor
Source and drain test electric current is added between pole, and measures the voltage between source electrode and drain electrode, to check the source electrode of MOS transistor device
Parasitic equivalent diode and drain electrode between.
Hereafter, in step ST2, according to the voltage between the grid that measures and drain electrode, the voltage between grid and source electrode,
And the voltage between source electrode and drain electrode is judging whether MOS transistor is corresponding with the pin of the packaging and testing slot for being inserted.
On the one hand, in step ST2, judging that MOS transistor is corresponding with the pin of the packaging and testing slot for being inserted
In the case of（That is, current MOS transistor is properly inserted into packaging and testing slot）, can after conventional package level test（Step
ST3）, and terminate flow process after package level test has been performed（Step ST4）.
On the other hand, in step ST2, judging that MOS transistor is not right with the pin of the packaging and testing slot for being inserted
In the case of answering（That is, current MOS transistor is not properly inserted into packaging and testing slot）, directly terminate flow process（Step
ST4）.
Thus, MOS transistor package level method of testing according to embodiments of the present invention is completed.
MOS transistor package level method of testing according to embodiments of the present invention, can pass through inspection MOS transistor device
Parasitic equivalent diode between each pin, defines according to the test value of parasitic equivalent diode come judicious pin, by
This can be effectively prevented from making the breakdown damage of MOS transistor device due to the mistake of line excitation.
Preferably, in step ST2, judging that MOS transistor is not corresponding with the pin of the packaging and testing slot for being inserted
（That is, current MOS transistor is not properly inserted into packaging and testing slot）In the case of, flow process can terminated（Step
ST4）Afterwards, repeat real according to the present invention shown in Fig. 3 after the mode of the packaging and testing slot of conversion MOS transistor insertion
The flow chart of the MOS transistor package level method of testing of example is applied, it is possible thereby to judge that the MOS transistor after changing is not correct
Ground insertion packaging and testing slot.
The rest may be inferred, can be in the way of constantly changing MOS transistor and insert packaging and testing slot until correctly that MOS is brilliant
Body pipe inserts packaging and testing slot.
More specifically, Fig. 4 schematically shows the situation of the parasitic equivalent diode of NMOS.In source S 1 to drain electrode
There is a parasitic equivalent diode A1 between D1, its conducting direction is from the source S 1 of NMOS to drain D 1.
Thus, for the situation of the NMOS shown in Fig. 4, each in three pins of packaged NMOS tube are not known
In the case of the corresponding relation of the source S 1, drain D 1 and grid G 1 of pin and NMOS, first to the two of packaged NMOS tube
Add electric current between individual pin, if there is electrical potential difference between the two pins, may determine that the high pin of potential for NMOS's
Source S 1, the drain D 1 of the low pin NMOS of potential.So remain grid G 1 of the next one pin for NMOS.
In another case, the situation of the same NMOS for shown in Fig. 4, if the first step is in packaged NMOS tube
The first pin（It is assumed to be grid G 1）To second pin（It is assumed to be source S 1）Direction between plus electric current, then do not have electricity
Potential difference（Electric current is not turned on）；Hereafter, if second step is in the first pin in packaged NMOS tube（It is assumed to be grid G 1）Extremely
3rd pin（It is assumed to be drain D 1）Direction between plus electric current, then there will not be electrical potential difference（Electric current is not turned on）；Thus may be used
To judge that the first pin is grid G 1 or drain D 1.
Hereafter, in the third step on the direction of second pin to the 3rd pin between plus electric current, then will have electrical potential difference
Occur, it is possible thereby to judge that second pin is the source S 1 of NMOS, the 3rd pin is the drain D 1 of NMOS, and the first pin is grid
G1.On the other hand, if adding electric current on the 3rd pin to the direction of second pin in the 3rd step, electrical potential difference is not still had
（Electric current is not turned on）, so still may determine that second pin is the source S 1 of NMOS.Hereafter, respectively in second pin and
Between one pin and second pin and the 3rd pin plus electric current, so as to according to whether having the situation of electrical potential difference to judge the 3rd
Pin is the drain D 1 of NMOS, and the first pin is grid G 1.
As PMOS, from unlike NMOS, the direction of parasitic equivalent diode is from drain electrode to source electrode, except this
Outside, test process is identical with the situation of above-mentioned MOS, will not be described here.
MOS transistor package level method of testing according to embodiments of the present invention, correctly can seal MOS transistor insertion
Dress test socket, it is possible thereby to be effectively prevented from making the breakdown damage of MOS transistor device due to the mistake of line excitation.
Preferably, in a particular application, to be advantageously used for power MOS brilliant for the MOS transistor package level method of testing
The package level test of body pipe.
According to another preferred embodiment of the invention, present invention also offers a kind of sampled described in above-described embodiment
The MOS transistor manufacture method of MOS transistor package level method of testing.
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to
Limit the present invention.For any those of ordinary skill in the art, under without departing from technical solution of the present invention ambit,
All many possible variations and modification are made to technical solution of the present invention using the technology contents of the disclosure above, or be revised as
With the Equivalent embodiments of change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, still fall within the scope of technical solution of the present invention protection
It is interior.
Claims (6)
1. a kind of MOS transistor package level method of testing, it is characterised in that include：
First MOS transistor is inserted into packaging and testing slot；
Hereafter input test sample signal；
The parasitic equivalent diode between each pin is subsequently checked, and judges MOS transistor and the packaging and testing slot for being inserted
Pin whether correspond to, the step of parasitic equivalent diode between each pin of the inspection in, in the grid of MOS transistor
Grid leak test electric current is added and drain electrode between, and measures the voltage between grid and drain electrode, to check MOS transistor device
Parasitic equivalent diode between grid and drain electrode；Test electric current in grid source is added between the grid and source electrode of MOS transistor, and
And the voltage between grid and source electrode is measured, to check parasitic equivalent two pole between the grid of MOS transistor device and source electrode
Pipe；Source and drain test electric current is added between source and drain in a mos transistor, and measures the voltage between source electrode and drain electrode,
To check the parasitic equivalent diode between the source electrode of MOS transistor device and drain electrode；And
In the case of judging that MOS transistor is not corresponding with the pin of the packaging and testing slot for being inserted, directly terminate flow process.
2. MOS transistor package level method of testing according to claim 1, it is characterised in that wherein using plus stream pressure measurement
To check the parasitic equivalent diode between each pin.
3. MOS transistor package level method of testing according to claim 2, it is characterised in that in each pin of the inspection
Between parasitic equivalent diode the step of in, according to the voltage between the grid that measures and drain electrode, between grid and source electrode
Voltage between voltage and source electrode and drain electrode is judging whether are MOS transistor and the pin of packaging and testing slot for being inserted
Correspondence.
4. MOS transistor package level method of testing according to claim 1, it is characterised in that judge MOS transistor with
In the case of the pin of the packaging and testing slot for being inserted is not corresponding, after flow process is terminated, the envelope of MOS transistor insertion is changed
The mode of dress test socket, repeats afterwards the MOS transistor package level method of testing.
5. MOS transistor package level method of testing according to claim 1, it is characterised in that the MOS transistor encapsulation
Level method of testing is used for the package level of power MOS transistor and tests.
6. a kind of MOS transistor of the MOS transistor package level method of testing sampled according to one of claim 1 to 5
Manufacture method.
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| CN201210261950.0A CN102759697B (en) | 2012-07-26 | 2012-07-26 | Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method |
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| CN201210261950.0A CN102759697B (en) | 2012-07-26 | 2012-07-26 | Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method |
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| CN102759697B true CN102759697B (en) | 2017-05-03 |
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| CN103969544B (en) * | 2014-03-04 | 2018-02-16 | 深圳博用科技有限公司 | A kind of integrated circuit high pressure pin continuity testing method |
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