TW201337280A - Avalanche testing apparatus and method thereof - Google Patents

Abstract

A testing apparatus for performing an avalanche test includes a wafer chuck configured to retain a wafer having at least one transistor, an inductor with a first end connected to a drain terminal of the transistor, a power source configured to provide a current to a second end of the inductor through a switch, a meter connected to a source terminal of the transistor through the wafer chuck, and a driver configured to synchronously control the operation of the switch and the operation of the transistor.

Description

Crash test device and test method thereof

The present disclosure relates to a crash test apparatus and test method, and more particularly to an apparatus and method for performing a crash characteristic test of a transistor at a wafer level.

In general, integrated circuit components on a wafer must first be tested for electrical characteristics to determine if the integrated circuit components are good. A good integrated circuit will be selected for subsequent packaging processes, and defective products will be discarded to avoid additional packaging costs. The completed integrated circuit component must be subjected to another electrical test to screen out the defective package, thereby improving the final product yield. In other words, the integrated circuit component must be tested for electrical characteristics several times during the manufacturing process.

The crash test of the transistor can be performed at the wafer level, rather than after the packaging process is completed, so that the transistor that does not conform to the crash specification can be screened and discarded before the packaging process, thereby avoiding an increase in packaging cost. U.S. Patent No. 7,368,934 discloses a crash test for applying a crash test signal to a packaged circuit component to be tested that completes the package.

The present disclosure provides an apparatus and method for conducting a crash characteristic test of a transistor at a wafer level.

The crash test apparatus provided by the present disclosure includes a wafer stage configured To receive a wafer having at least one transistor; an inductor having a first end connected to one of the drains of the transistor; a power source configured to provide a current to the inductor via a switch a second end point; a meter configured to be coupled to a source of the transistor via the wafer stage; and a driver configured to synchronously control operation of the switch and operation of the transistor.

The crash test method provided by the present disclosure includes the steps of: flowing a current from a wafer stage configured to receive a wafer having at least one transistor; charging an inductor, the inductor having a a first terminal connected to one of the drains of the transistor; synchronously conducting the transistor and stopping charging the inductor; and measuring a current through a source of the transistor.

The technical features and advantages of the present disclosure have been broadly described above, and the detailed description of the present disclosure will be better understood. Other technical features and advantages of the subject matter of the claims of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present invention may be practiced with the same or equivalents. It is also to be understood by those of ordinary skill in the art that this invention is not limited to the spirit and scope of the disclosure as defined by the appended claims.

The crash test of the transistor can be performed at the wafer level, rather than after the packaging process is completed, so that the transistor that does not conform to the crash specification can be screened and discarded before the packaging process, thereby avoiding an increase in packaging cost. However, wafer crash testing at the wafer level faces a major drawback: since the components (transistors) of the wafer have a common source and the wafer is placed on the wafer stage, the wafer stage can be considered a large The capacitor prevents the current passing through the component under test from flowing to the meter of the test machine, resulting in an incorrect measurement result.

1 and 2 illustrate a transistor collapse test apparatus 10 in accordance with an embodiment of the present invention. In one embodiment of the present disclosure, the crash test apparatus 10 includes a wafer stage 11 configured to receive a wafer 21 having a plurality of transistors 23; an inductor 31 having a first end point 33, connected to one of the transistor 23 of the transistor 23; a power source 41 (such as a high voltage source or a high current source), configured to provide a current through a switch 43 to a second terminal 35 of the inductor 31; A meter 49 is configured to be coupled to one of the sources 25 of the transistor 23 via a contact 13 of the wafer stage 11; and a driver 45 (eg, a slew rate voltage driver) configured for synchronous control The operation of the switch 43 and the operation of the transistor 23. In one embodiment of the present disclosure, the crash test apparatus 10 further includes a pulse detector 47 and a blocking component 51. The pulse detector 47 is connected to the drain 27 of the transistor 23, and the blocking component 51 ( For example, a diode is connected to the second terminal 35 of the inductor 31.

3 is a flow chart showing a method of testing a cell crash according to an embodiment of the present invention. In an embodiment of the disclosure, the crash test method includes the following Step: discharging a current from a wafer stage configured to receive a wafer having at least one transistor; charging an inductor, the inductor having a first end connected to the One of the crystals is drained; the transistor is turned on synchronously and the charging of the inductor is stopped; and the current through one of the sources of the transistor is measured. In one embodiment of the present disclosure, flowing a current from a wafer stage includes connecting the wafer stage to a ground potential, that is, flowing current from a common source of the wafer via the wafer stage.

4 is a waveform diagram showing an embodiment of the present invention, showing a gate voltage waveform applied to a transistor and a current waveform of an inductor. Fig. 5 is a view showing a waveform diagram of an embodiment of the present invention, showing a drain current waveform and a source current waveform of the transistor. As shown in FIG. 5 and FIG. 6, even when the transistor collapse test is performed at the wafer level, the collapse test device and the collapse of the present disclosure are performed when the transistor 23 is turned on synchronously and the switch 43 is turned off (the charging of the inductor 31 is stopped). The test method can accurately measure the current peak on the source 25 of the transistor 23.

Under the conventional crash test architecture, the wafer stage 11 serves as a large capacitor, so that the current passing through the common source 29 of the transistor 23 to be tested is dispersed on the wafer stage 11 and cannot flow to the test machine. The meter 49 causes the current peak to be lost (as shown in Figure 6). In contrast, the embodiment of the present disclosure flows current from the common source 25 of the wafer 21 via the wafer stage 11 , and simultaneously turns on the transistor 23 and turns off the switch 43 (stops charging the inductor 31 ). The crash test device and the crash test method can accurately measure the current peak on the source 25 of the transistor 23.

The technical content and technical features of the disclosure have been disclosed above, however, this disclosure It is to be understood by those of ordinary skill in the art that the present invention may be modified and modified without departing from the spirit and scope of the disclosure. For example, many of the processes disclosed above may be implemented in different ways or in other processes, or a combination of the two.

Moreover, the scope of the present invention is not limited to the particular process, machine, manufacture, composition, means, method or method of the particular embodiments disclosed. It should be understood by those of ordinary skill in the art that, based on the teachings of the present disclosure, the process, the machine, the manufacture, the composition of the material, the device, the method, or the steps, whether present or future developers, The revealer performs substantially the same function in substantially the same manner, and achieves substantially the same result, and can also be used in the present disclosure. Accordingly, the scope of the following claims is intended to cover such <RTIgt; </ RTI> processes, machines, manufactures, compositions, devices, methods or steps.

10‧‧‧Crash test device

11‧‧‧ Wafer stage

13‧‧‧Contacts

21‧‧‧ wafer

23‧‧‧Optoelectronics

25‧‧‧ source

27‧‧‧汲polar

29‧‧‧ gate

31‧‧‧Inductance

33‧‧‧First endpoint

35‧‧‧second endpoint

41‧‧‧Power supply

43‧‧‧Switch

45‧‧‧ drive

47‧‧‧Pulse Detector

49‧‧‧meter

51‧‧‧Barrier components

The technical features and advantages of the present disclosure are fully understood by reference to the foregoing description and the accompanying drawings.

1 and 2 illustrate a transistor collapse test apparatus according to an embodiment of the present invention; FIG. 3 is a flow chart showing a transistor crash test method according to an embodiment of the present invention; and FIG. 4 is a waveform diagram showing an application according to an embodiment of the present invention. In the transistor The gate voltage waveform and the current waveform of the inductor; FIG. 5 illustrates a waveform diagram of an embodiment of the present invention, showing a drain current waveform and a source current waveform of the transistor; and FIG. 6 illustrates a conventional crash test architecture, the transistor The drain current waveform and the source current waveform.

10‧‧‧Crash test device

13‧‧‧Contacts

23‧‧‧Optoelectronics

25‧‧‧ source

27‧‧‧汲polar

29‧‧‧ gate

31‧‧‧Inductance

33‧‧‧First endpoint

35‧‧‧second endpoint

41‧‧‧Power supply

43‧‧‧Switch

45‧‧‧ drive

47‧‧‧Pulse Detector

49‧‧‧meter

51‧‧‧Barrier components

Claims (10)

A crash test apparatus comprising: a wafer stage configured to receive a wafer having at least one transistor; an inductor having a first end connected to one of the gates of the transistor; a power supply configured to provide a current to a second end of the inductor via a switch; a meter configured to connect to a source of the transistor via the wafer stage; and a driver configured to The operation of the switch and the operation of the transistor are synchronously controlled. The crash test device of claim 1, further comprising a pulse detector coupled to the drain of the transistor. The crash test apparatus of claim 1, wherein the gauge is coupled to a common source of the wafer. The crash test device of claim 1 further comprising a blocking element coupled to the second end of the inductor. The crash test device of claim 4, wherein the barrier element comprises a diode. The crash test apparatus of claim 1, wherein the gauge is an ammeter. A crash test method comprising the steps of: flowing a current from a wafer stage, the wafer stage configured to receive a wafer having at least one transistor; Charging an inductor having a first terminal connected to one of the drains of the transistor; synchronously conducting the transistor and stopping charging the inductor; and measuring a current through a source of the transistor. The crash test apparatus of claim 7, wherein a power source charges the inductor via a switch. The crash test apparatus of claim 8, wherein the turning on the transistor and turning off the open relationship are performed synchronously. The crash test apparatus of claim 7, wherein flowing a current from a wafer stage comprises connecting the wafer stage to a ground potential.