CN103731014B - A kind of TDC circuit for power tube drive part by part - Google Patents
A kind of TDC circuit for power tube drive part by part Download PDFInfo
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- CN103731014B CN103731014B CN201410024149.3A CN201410024149A CN103731014B CN 103731014 B CN103731014 B CN 103731014B CN 201410024149 A CN201410024149 A CN 201410024149A CN 103731014 B CN103731014 B CN 103731014B
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Abstract
The present invention relates to integrated circuit technique, relate to a kind of time-to-digital conversion circuit for DC-DC converter DCM mode power pipe drive part by part specifically.A kind of TDC circuit for power tube drive part by part of the present invention, comprise time to digital converter unit and logic control element, described time to digital converter unit comprises Postponement module and latch module, and described logic control element comprises frequency division module, work schedule generation module, summation module and segmentation determination module; Wherein, Postponement module is connected with latch module, and summation module is connected with latch module, work schedule generation module and segmentation determination module respectively, and work schedule generation module is connected with frequency division module and segmentation determination module respectively.Beneficial effect of the present invention is, by the TDC circuit realiration current detecting of DC-DC converter under DCM of band logic control, and realizes the stable segmentation of power tube.The present invention is particularly useful for the power tube drive part by part under DC-DC converter DCM pattern.
Description
Technical field
The present invention relates to integrated circuit technique, relate to a kind of time figure for DC-DC converter DCM mode power pipe drive part by part conversion (TimeDigitalConverter, TDC) circuit specifically.
Background technology
DC-DC converter becomes the voltage changer that on-fixed direct voltage is fixing direct voltage, is widely used in the middle of the various electronic portable device such as mobile phone, flat board.Common DC-DC converter is divided three classes: Buck buck convertor, Boost boost converter, Buck-Boost buck-boost code converter.The conversion efficiency of DC-DC converter affects electronic portable device some performance received much concern, such as cruising time etc.For this reason, conversion efficiency Chang Zuowei weighs one of important indicator of DC-DC converter performance quality.
Power tube drive part by part technology is a kind of important means that effectively can improve DC-DC converter efficiency especially light-load efficiency.In the art, how detecting load current is a crucial problem.The current sample of conventional SenseFET mirror image pipe mode, has good sampling precision under large load current, but at little load current down-sampling precision meeting degradation, carries out current detecting under being not suitable for being used in DCM.Therefore, how under DCM, easily and effectively to detect load current and complete power tube and stablize segmentation and become a problem highly significant.
Summary of the invention
To be solved by this invention, be exactly for above-mentioned conventional power pipe drive part by part technology Problems existing, propose a kind of TDC circuit for power tube drive part by part.
The present invention solves the problems of the technologies described above adopted technical scheme: as shown in Figure 1, a kind of TDC circuit for power tube drive part by part, comprise time to digital converter unit and logic control element, described time to digital converter unit comprises Postponement module and latch module, and described logic control element comprises frequency division module, work schedule generation module, summation module and segmentation determination module; Wherein, Postponement module is connected with latch module, and summation module is connected with latch module, work schedule generation module and segmentation determination module respectively, and work schedule generation module is connected with frequency division module and segmentation determination module respectively;
Described Postponement module is connected power tube control signal with latch module, the output signal input and latch module of multiple test point as Postponement module is provided with in Postponement module, when power tube control signal is by high level step-down level, transmit backward through oppositely producing rising edge, the test point that rising edge passes to can uprise level by low level, the node do not passed to still keeps low level, when external control signal uprises level by low level, the multibit signal that Postponement module inputs latches by latch module under control of the control signal, produce n position quantization code and output to summation module, wherein n position quantization code is the ON time of power tube control signal,
The n position quantization code that described summation module inputs according to latch module produces corresponding m position control signal and outputs to segmentation determination module, and segmentation determination module produces n position Discrete control code according to m position control signal;
Described work schedule generation module is used for for control summation module and segmentation determination module provide enable control signal;
Described frequency division module is used for carrying out frequency division to external timing signal and being supplied to work schedule generation module.
The technical scheme that the present invention is total, the effect of time to digital converter unit is that the ON time in each clock cycle to power tube once quantizes, produce n position quantization code, the effect of collecting control unit is the summation that the quantization code produced time to digital converter unit carries out some cycles, and judge that final which to be in value interval, then the relation of hop count is opened with power tube in foundation and value interval, produces final Discrete control code.Here adopt some periodic quantization codes with value as segmentation foundation, avoid the fluctuation of Discrete control code, ensure that the stability of segmentation.
Concrete, described Postponement module is made up of multiple delay cell cascade, and the d type flip flop that described latch module is triggered by multiple trailing edge is formed, and described d type flip flop is equal with the quantity detecting node in Postponement module and be corresponding in turn to connection.
Beneficial effect of the present invention is, by the TDC circuit realiration current detecting of DC-DC converter under DCM of band logic control, and realizes the stable segmentation of power tube.
Accompanying drawing explanation
Fig. 1 is the structural representation of the TDC circuit for power tube drive part by part of the present invention;
Fig. 2 is the structural representation of time to digital converter unit;
Fig. 3 is logic control element work period schematic diagram;
Fig. 4 is the structural representation applying drive part by part Buck converter of the present invention.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
As shown in Figure 1, be the TDC circuit with logic control that the present invention proposes, generally speaking, it comprises time to digital converter unit and logic control element two large divisions.Time to digital converter unit comprises: Postponement module and latch module; Logic control element comprises: frequency division module, work schedule generation module, summation module and segmentation determination module.
The effect of time to digital converter unit is that the ON time in each clock cycle to power tube once quantizes, and produces n position quantization code.The effect of logic control element is the summation that the quantization code produced time to digital converter unit carries out some cycles, and judges that final which to be in value interval.Then the relation of hop count is opened with power tube in foundation and value interval, produces final Discrete control code.Here adopt some periodic quantization codes with value as segmentation foundation, avoid the fluctuation of Discrete control code, ensure that the stability of segmentation.
Annexation between each module is described in detail as follows:
En is overall enable signal, connects an input of latch module and NAND gate.
Drivep is the drive singal of power P pipe (all supposing in following explanation that P pipe is power switch pipe), connects another input of above-mentioned NAND gate.The output of NAND gate connects Postponement module and latch module respectively.Postponement module arranges n test point as output in internal latency chain: d1 ..., dn, d1 ..., dn connects latch module.At the rising edge of drivep, namely power P pipe is by when being opened to shutoff, latch module to d1 ..., the state of dn latches, and produces n position quantization code: a1 ..., an.A1 ..., an is the quantization code of the power tube ON time that each clock cycle produces, and it connects the summation module in Logical processing unit.
Clk is converter switches frequency clock signal, connects frequency division module, summation module, segmentation determination module respectively.The output of frequency division module connects work schedule generation module, and work schedule generation module produces 3 road signals: en1, rst1, en2.Wherein en1, rst1 connect summation module, are respectively its enable signal and reset signal.En2 connects segmentation determination module, is its enable signal.Summation module produces m position (value of m is determined according to Discrete control code bit number n) and exports: q1 ..., qm, q1 ..., qm connects segmentation determination module.Segmentation determination module produces n digit numeric code: seg1 ..., segn, seg1 ..., segn is as final Discrete control code.
As shown in Figure 2, be the concrete structure of time to digital converter unit:
Wherein, Postponement module is made up of a series of basic delay cell cascade.N is had to detect node in Postponement module.Choosing of they is the relation according to load current and power tube ON time, determines corresponding conduction period point by the current intervals point of segmentation, then on delay chain, find corresponding node time of delay, is set to detect node.Described Postponement module has such characteristic: suppose that Postponement module is input as low level, then each detects node is all initially low level.When input is by low high jump, can produces a rising edge and transmit backward in delay chain, the node that rising edge arrives will become high level, and the node do not arrived still keeps low level.The state that each detects node if at a time detect, then each node presents the different state of height.Detect the moment different, then can obtain different error detecting code combinations.
The d type flip flop that latch module is triggered by a series of trailing edge is formed.From power P pipe drive singal by high step-down, have rising edge and start to transmit backward in delay chain, the node that rising edge passes to can be uprised by low, and the node do not passed to still keeps low level.When power P pipe drive singal is by low uprising, the trailing edge through anti-phase generation can triggered latch module, and the state that Postponement module respectively detects node this moment will be saved.Now, the time that aforementioned rising edge transmits in delay chain is just the low level time of power P pipe drive singal, i.e. the ON time of power P pipe.So the ON time of power P pipe has just been quantized into set of number code.
Visible above, described time to digital converter unit has completed the quantification of power tube ON time to digital code.But this quantization code can not directly as final Discrete control code.Reason is that above quantization code produces once in each clock cycle, if the internal power P pipe ON time appearance fluctuation of certain clock cycle (or due to ectocine, or be in critical current due to load current), then quantization code also there will be fluctuation, thus segmentation can be caused unstable.
The effect of logic control element is exactly avoid above problem, ensures to stablize segmentation.In order to make segmentation stablize, it (is referred to as the work period) within N number of clock cycle, by the logical process to quantization code, upgrades once final Discrete control code.Wherein, work schedule generation module produces 3 crucial clock signals, and they will be divided into 4 Main Stage the work period: summation, judgement, reset, maintenance.
Composition graphs 3, is described the operating state of each phase logic control unit.
Summation stage: en1 is high level, continues N
1(N
1<N) the individual clock cycle, during this period, summation module carries out N to the quantized value of time to digital converter unit
1secondary sampling summation.After en1 step-down, summation module stops summation, keeps final summing value constant;
Judgement stage: en2 is high level, continues N
2(N
2<N) the individual clock cycle, during this period, segmentation determination module is enabled, and residing for its summing value kept summation module, interval makes a determination, and produces corresponding Discrete control code, and upgrades Discrete control code;
Reseting stage: rst1 is high level, continues N
3(N
3<N) the individual clock cycle, during this period, summation module is resetted (namely summation module exports and is set to 0) by clock signal, for the next work period prepares;
The maintenance stage: within the remaining clock cycle, fragment code remains unchanged.Until the arrival of next work period, then carry out once new judgement.
Embodiment:
This example mainly comprises the power tube of drive part by part, LC filter circuit, feedback control unit and TDC circuit of the present invention.Feedback control unit connects the output of Buck converter, produces the drive singal of power tube, gives the buffer circuit of TDC module and power tube.The ON time of TDC to power P pipe quantizes, and infers present load current size, produces Discrete control code.Discrete control code connects buffer circuit, carries out drive part by part to power tube.
In this example, some the parameter occurrences in preceding solution are as follows:
n=5，m=9，N=32，N
1=10，N
2=2，N
3=2
Namely 5 Discrete control codes (the power tube hop count controlled under DCM is 5) are had; Summation module exports with 9 binary representations (5 quantization code 10 cycle summations at least could represent with 9 bits); A work period comprises 32 clock cycle; Clock signal en1 high level continues 10 clock cycle, and clock signal rst1 high level continues 2 clock cycle, and clock signal en2 high level continues 2 clock cycle.
In the summation stage, in described logic control element, summation module carries out 10 sampling summations to the quantization code of ON time, and then segmentation determination module judges which interval this and value are in, and upgrades fragment code.Then, summation module is reset (summation module exports and is cleared).In the time of work period remainder, fragment code remains unchanged, until the arrival of next work period, then carries out once new judgement.
In this example, logic control element carries out segmentation and judges that the look-up table of institute foundation is as shown in table 1:
Table 1 logic control element carries out segmentation and judges look-up table
Claims (2)
1. the TDC circuit for power tube drive part by part, described TDC circuit is time-to-digital conversion circuit, comprise time to digital converter unit and logic control element, described time to digital converter unit comprises Postponement module and latch module, and described logic control element comprises frequency division module, work schedule generation module, summation module and segmentation determination module; Wherein, Postponement module is connected with latch module, and summation module is connected with latch module, work schedule generation module and segmentation determination module respectively, and work schedule generation module is connected with frequency division module and segmentation determination module respectively;
Described Postponement module is connected power tube control signal with latch module, the output signal input and latch module of multiple test point as Postponement module is provided with in Postponement module, when power tube control signal is by high level step-down level, transmit backward through oppositely producing rising edge, the test point that rising edge passes to can uprise level by low level, the test point do not passed to still keeps low level, when external control signal uprises level by low level, the multibit signal that Postponement module inputs latches by latch module under control of the control signal, produce n position quantization code and output to summation module, wherein n position quantization code is the ON time of power tube control signal,
The n position quantization code that described summation module inputs according to latch module produces corresponding m position control signal and outputs to segmentation determination module, and segmentation determination module produces n position Discrete control code according to m position control signal;
Described work schedule generation module is used for for control summation module and segmentation determination module provide enable control signal;
Described frequency division module is used for carrying out frequency division to external timing signal and being supplied to work schedule generation module.
2. a kind of TDC circuit for power tube drive part by part according to claim 1, it is characterized in that, described Postponement module is made up of multiple delay cell cascade, the d type flip flop that described latch module is triggered by multiple trailing edge is formed, and described d type flip flop is equal with the quantity of test point in Postponement module and be corresponding in turn to connection.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410024149.3A CN103731014B (en) | 2014-01-20 | 2014-01-20 | A kind of TDC circuit for power tube drive part by part |
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| CN201410024149.3A CN103731014B (en) | 2014-01-20 | 2014-01-20 | A kind of TDC circuit for power tube drive part by part |
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| CN103731014A CN103731014A (en) | 2014-04-16 |
| CN103731014B true CN103731014B (en) | 2016-04-06 |
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| CN109149912B (en) * | 2018-09-15 | 2020-12-25 | 福州大学 | Switching tube power loss and automatic adjusting circuit in switching power supply and working method |
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| CN102801317A (en) * | 2012-08-16 | 2012-11-28 | 电子科技大学 | Adaptive sectional driving DC-DC converter |
Family Cites Families (2)
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| JP3394013B2 (en) * | 1999-12-24 | 2003-04-07 | 松下電器産業株式会社 | Data extraction circuit and data extraction system |
| US7205924B2 (en) * | 2004-11-18 | 2007-04-17 | Texas Instruments Incorporated | Circuit for high-resolution phase detection in a digital RF processor |
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Patent Citations (3)
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|---|---|---|---|---|
| CN1532792A (en) * | 2003-03-26 | 2004-09-29 | 三洋电机株式会社 | Driving circuit of vacuum fluorescent display |
| CN101373973A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科微电子（上海）有限公司 | Time-to-digital conversion circuit and method |
| CN102801317A (en) * | 2012-08-16 | 2012-11-28 | 电子科技大学 | Adaptive sectional driving DC-DC converter |
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| 基于FPGA的高精度时间数字转换电路设计;许春香等;《微计算机信息》;20090131;第25卷(第1-2期);第208-210页 * |
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