CN1036864A - Cmos/nmos集成电路 - Google Patents

Cmos/nmos集成电路 Download PDF

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Publication number
CN1036864A
CN1036864A CN89101825.5A CN89101825A CN1036864A CN 1036864 A CN1036864 A CN 1036864A CN 89101825 A CN89101825 A CN 89101825A CN 1036864 A CN1036864 A CN 1036864A
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cmos
basic circuit
nmos
inverter
function
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汉斯·尤根·加里
阿荷德·尤兰霍夫
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TDK Micronas GmbH
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Deutsche ITT Industries GmbH
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

集成电路的每个功能由一基本电路实现，如加法 器(SM)，乘法器(m)，除法器(d)，比较器(K)、存贮 器(SP)、移位寄存器(Sr)、模/数转换器(ad)、数/ 模转换器(da)或采样保持器(ah)、翻转触发器(f)、反 相器(ic，id)或门(g)，其特征为将各功能所需的基本 电路中子数(p)个制成CMOS基本电路(c)，其余子 数q个制成增强型NMOS具有电流源的基本电路 (N)，最好是以耗尽型晶体管为负载器件，并选择子 数p，使CMOS基本电路(c)中传输延迟对供电电压 的依赖性被NMOS基本电路(N)中传输延迟对供电 电压的依赖性所补偿。

Description

本发明涉及CMOS/NMOS集成电路。这种电路在《微电子学杂志》（Mieroelectronics    Joarnal）1982上第29至32页，特别是在第32页上有所叙述，根据这篇文章，为实现任何特别的数字功能而对CMOS或NMOS技术的选择，将取决于集成电路的速度和封装密度的要求，以便使CMOS和NMOS在同一片集成电路片上结合起来，去实现那些仅用CMOS技术或仅用NMOS技术的特别功能。
本发明所需解决的问题是在简单的CMOS器件中，特别是在CMOS反相器中，决定着集成电路开关速度和截止频率的传输延迟依赖于供电电压，如“NEREM    Record”杂志1967年号第168至169页所谈及的CMOS反相器。这种对电压的依赖性是很不利的。例如由CMOS技术所实现的功能主要是利用上述那种传输延迟，如同延迟元件，特别是在数字滤波器中或环路振荡器中，下面将谈到这些器件。
因此，本发明的目的是补偿由CMOS技术所实现的CMOS/NMOS集成电路功能中传输延迟对电压的这种依赖。这种所说的“功能”是指集成电路中的小单元，它由单一的尤其是数字的基本类型电路来实现。这类数字基本类型电路如：加法器、乘法器、除法器、比较器、存贮器、移位寄存器、模/数转换器、数/模转换器或采样保持器，以及翻转触发器，反相器，或各类门等。加法器、乘法器等被认为是包含保持器的。
“门”在这里指任何逻辑电路，其唯一输出端提供一个基于其输入端信号组合的信号。对本发明来说，仅相器被看作是最简单的门。
本发明的基本思想是在CMOS/NMOS电路的一个功能中将子数p个必要的基本电路做成CMOS基本电路，将其余子数q个作成带电流源的增强型NMOS基本电路，特别是耗尽型晶体管作为负载器件，即最好用耗尽型负载NMOS基本电路，这样就脱离了所有功能全由上述一种技术来实现的现有技术。
根据本发明，例如环振荡器的振荡频率可以无需电压调节电路而独立于供电电压决定，因此，在本发明方案中芯片上无需因电压调节电路而增设额外的区域。
下面参考附图详细叙述本发明，其中，图1为应用了本发明的集成电路示意结构图。图2，为应用了本发明的环振荡器示意电路图。
图1示意图表示做在一个芯片上的集成电路的结构。由于集成电路有许多种类，所以本发明不限于所述的结构。在许多独立自合功能的基本电路中，图1表示了模/数转换器ad，采样保持器ah、加法器Sm、乘法器m、存贮器Sp、数/模转换器d    移位寄存器Sr、门g和翻转触发器f。集成电路S还可以包括  拟电路如放大器等。
集成电路S左边的外部连线代表输入线，右边的代表输出线。在集成电路S内，由上述基本类型电路实现的功能具有输出线，通向集成电路S内其它子功能或别的输出线。各功能还有来自集成电路S内其它功能的输入线。各功能的具体连接是依据集成电路S的特定结构及电路设计的整个功能而定的。具体的内部连线对于本发明是不重要要，也就是说本发明是可以应用于所有集成电路的。
在图1所示实施例中，一些上所示功能是根据本发明实现的，即，实现这些功能所需的基本电路中的子数p个用CMOS技术作成，而其余子数q个作成增强型NMOS，即各基本电路C、N。在图1中，它们是模/数转换器ad、加法器Sm、乘法器m，存贮器Sp和翻转触发器f。
根据本发明，实现一个功能的基本电路总数p+q以这种方式被分成p和q，即CMOS基本电路C的传输延迟对供电电压的依赖由NMOS基本电路N的传输延迟对供电电压的依赖来补偿。
图2表示了将本发明原理应用于环振荡器的实施例，环振荡器经常用在数字集成电路中，例如产生时钟信号或测量门转输延迟。众所周知，环振荡器包括许多次E角的起振相位串联的反相器，最后一个反相器的输出与第一个反相器的输入相耦合，形成一个“环”。为了满足振荡条件，通常将奇数个反相器连成环。如果要中断振荡，反相器之一要用NOR或NAND门做成，例如用一个信号通过这个门可消除“正确”的相位条件。
图2表示了由七个反相器连成环的环振荡器。根据本发明，子数p个制成CMOS反相器ic，子数q个制成耗尽负载型反相器id。在图2的实施例中，四个CMOS反相器ic和三个带有耗尽型晶体管di负载的耗尽负载型反相器连成环振荡器。
对供电电源的依赖性可通过各设计参数和工艺参数而精确地调整。在图2实施例中，p＝4、q＝3，CMOS反相器ic中P和N型场效应晶体管各有1.5毫微米长隧道，P场效应管道宽为30毫微米，门限电压为-0.75V;N场效应管道宽为15毫微米，门限电压为+0.75V。
图2中的耗尽负载反相器id被分为两“组”，在两组耗尽负载反相器中，耗尽型晶体管隧道长2毫微米，道宽14毫微米，增强型晶体管隧道长1.5毫微米，道宽15毫微米。在第三个耗尽负载反相器中，耗尽型晶体管隧道长2毫微米，道宽20毫微米，而增强型晶体管隧道长1.5毫微米，道宽15毫微米。所有耗尽型晶体管具有门源限电压-2V，所有增强型晶体管具有门限电压+0.75V。
对于p、q其它的数值，本领域一般技术人员可容易地基于设计原则和生产规则通过实验取适当的计设数据。

Claims (2)

1、CMOS/NMOS集成电路(S)，具有，最好数字的，功能，每个功能由一基本电路实现，如加法器(SM)，乘法器(m)，除法器(d)，比较器(k)、存贮器(sp)、移位寄存器(sr)、模/数转换器(ad)、数/模转换器(da)或采样保持器(ah)、翻转触发器(f)、反相器(ic，id)或门(g)，其特征为将各功能所需的基本电路中子数(p)个制成CMOS基本电路(c)，其余子数q个制成增强型NMOS具有电流源的基本电路(N)，最好是以耗尽型晶体管为负载器件，并选择子数p，使CMOS基本电路(c)中传输延迟对供电电压的依赖性被NMOS基本电路(N)中传输延迟对供电电压的依赖性所补偿。
2、如权利要求1所述的CMOS/NMOS集成电路，其特征为包括环振荡器，其中有p个串联的CMOS反相器（ic），及后面的q个串联的NMOS耗尽负载型反相器（id），最后一个NMOS反相器的输出与第一个CMOS反相器的输入相耦合，且p+q为奇数。
CN89101825.5A 1988-03-31 1989-03-30 Cmos/nmos集成电路 Pending CN1036864A (zh)

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Application Number Priority Date Filing Date Title
EP88105243A EP0334983A1 (de) 1988-03-31 1988-03-31 Integrierte CMOS/NMOS-Schaltung
EP88105243.5 1988-03-31

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EP (1) EP0334983A1 (zh)
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US4922140A (en) 1990-05-01
EP0334983A1 (de) 1989-10-04

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