CN103683883A - Single-power-supply circuit capable of restraining IGBT miller capacitance effect - Google Patents
Single-power-supply circuit capable of restraining IGBT miller capacitance effect Download PDFInfo
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Abstract
The invention discloses a single-power-supply circuit capable of restraining the IGBT miller capacitance effect. The single-power-supply circuit comprises a single power supply system (1) of the IGBT driving portion, and an MOSFET clamping circuit topological structure (2) for restraining the IGBT miller capacitance effect. The MOSFET clamping circuit topological structure (2) comprises a first N channel MOSFET pipe (Q1), a second N channel MOSFET pipe (Q2), a grid resistor (R6) of the first N channel MOSFET pipe (Q1), a grid resistor (R7) of the second N channel MOSFET pipe (Q2), a first resistor (R5), a second resistor (R8), a drive signal capacitor (C52) and a pull-down resistor (R8). The single-power-supply circuit can effectively restrain the IGBT wrong connection phenomenon caused by the miller capacitance effect, losses of the IGBT are greatly reduced, the service life of the IGBT is prolonged, and guarantees are provided for reliable running of a low-voltage and low-power frequency converter.
Description
Technical field
The present invention is applied to several kilowatts of following small-power industry or civil electrical transmission field, relates to because the intrinsic Miller capacitance effect of IGBT may cause circuit topological structure and the implementation method that IGBT misleads and invents.
Background technology
The simplicity to the sensitiveness of product cost and design due to small-power industry or civil electrical transmission field, the harshness of volume, in Small-power Inverter or servo controller IGBT driving, conventionally adopt single power supply technology (the general single power supply that adopts in small-power, if employing dual power supply, Miller capacitance effect still exists, but can not cause straight-through phenomenon in short-term), existence due to IGBT Miller capacitance effect, if do not take any measure, inevitably there will be the in short-term straight-through phenomenon of inverter upper and lower bridge arm tens to hundreds of nanosecond, although can not bring fatal impact in the short time, but this phenomenon can cause IGBT switching loss significantly to increase, cause larger thermal cycling stresses, have a strong impact on the useful life of IGBT, when reducing the efficiency of inverter, heat radiation is had higher requirement.For addressing this problem, prior art has two kinds: the method that the first conventionally adopts, drives between resistance and grid, emitter the straightforward procedures such as shunt capacitance to improve the risk that misleads of bringing due to Miller capacitance effect by strengthening IGBT grid; It two is the methods that adopt PNP or NPN triode.
The technological merit of existing method one is: simple in structure, and low price.Shortcoming is: can only reduce the risk that misleads causing because of Miller capacitance effect, can not eliminate the of short duration phenomenon that misleads, referring to accompanying drawing 5, CH1 is upper brachium pontis driving voltage waveform, when this waveform slowly changes to low (approximately 1.5 μ s) by height, upper brachium pontis turn-offs, the grid that can find out thus IGBT in Fig. 5 has adopted method one to strengthen resistance and electric capacity, when but the IGBT of brachium pontis opens instantly, between the CE of upper brachium pontis, produce very large du/dt, this du/dt signal is coupled between the grid and emitter of brachium pontis through Miller capacitance effect, owing to having adopted method one at grid, electric capacity in parallel between emitter, the du/dt signal being coupled by Miller capacitance effect will charge to this shunt capacitance, thereby because the existence of this shunt capacitance has reduced Miller capacitance effect voltage, this shunt capacitance has absorbed part Miller capacitance effect energy in other words, therefore reduced the risk that misleads that Miller capacitance effect causes.But the finite energy that this shunt capacitance absorbs, still can not eliminate the of short duration phenomenon that misleads, CH4 in Fig. 5 can see the electric current that misleads clearly, the about 2A of peak value, in fact can not ad infinitum increase the capacitance of this electric capacity, because this will cause larger driving time delay (approximately 1.5 μ s time delays in figure will become longer), strengthen switching loss, thereby affect the control performance of motor, this is also that we do not wish to see.
Existing method two is mentioned in some papers, but do not see in practical application, by reality, test, method two is owing to adopting PNP or NPN triode, its response speed cannot meet the disturbing pulse of tens to the hundreds of nanosecond that Miller capacitance effect brings, through reality test, Miller capacitance effect is not had to any inhibition.Therefore there is no actual application value.
Summary of the invention
Goal of the invention: a kind of simple, quick and cheap topological circuit structure is provided, the IGBT phenomenon that misleads in the inverter single power supply drive circuit that effectively suppresses to cause due to Miller capacitance effect, reduce the loss of IGBT, in the useful life that extends IGBT, the reliability service of low pressure Small-power Inverter is provided safeguard.
Technical scheme: a kind of single power supply suppresses the circuit of IGBT Miller capacitance effect, comprises the single power supply system 1 of IGBT drive part, the MOSFET clamp circuit topological structure 2 of inhibition IGBT Miller capacitance effect,
Each brachium pontis driving power that described single power supply system 1 can be inverter independently provides by Switching Power Supply, such as: for three-phase inverter, Switching Power Supply provides an independently positive 15V common driver power supply to brachium pontis under three-phase inverter, to brachium pontis on three-phase inverter, respectively provide a positive 15V driving power in road, this mode switch power supply provides the 4 tunnels unipolarity driving power of isolation mutually altogether to three-phase inverter, referring to Fig. 1;
Described single power supply system 1 can also be Switching Power Supply only provides a road unipolarity power supply to the driving of inverter, this power supply provides driving directly to the lower brachium pontis IGBT of inverter, each IGBT driving power of upper brachium pontis all obtains by Boost mode, referring to Fig. 2;
Described MOSFET(Chinese full name is mos field effect transistor, be called for short metal half field effect transistor or MOSFET) clamp circuit topological structure, comprise the first N-channel MOS FET pipe Q1, the resistance R6 of the second N-channel MOS FET pipe Q2, the first N-channel MOS FET pipe Q1, the resistance R7 of the second N-channel MOS FET pipe Q2, the first resistance R 5, the second resistance R 8, driving signal capacitor C 52, pull down resistor R8, is characterized in that:
The upper brachium pontis of IGBT in inverter drives the driving signal of optocoupler U1 to pass through the first resistance R 5 direct effects to the grid of IGBT, the grid of the first N-channel MOS FET pipe Q1 is connected with the output of optocoupler U1 by the second resistance R 6, the gate pole of the second N-channel MOS FET pipe Q2 is connected with the positive pole of IGBT driving power by its resistance R7, the drain electrode of the first N-channel MOS FET pipe Q1 is directly connected with the grid of the second N-channel MOS FET pipe Q2, the source electrode of the source electrode of the first N-channel MOS FET pipe Q1 and the second N-channel MOS FET pipe Q2 is directly connected on the ground U-network of single power supply,
Described pull down resistor R8 is in parallel with driving signal capacitor C 52, and the first filter capacitor C1 of single power supply system 1, the second filtering C2 are in parallel, are one end and are connected with the anodal U+ of single power supply system 1, and the other end is connected with the ground U-of single power supply system 1; Described pull down resistor R8 prevents the electrostatic breakdown of IGBT grid, and described driving signal capacitor C 52 prevents that other interference of IGBT from misleading.
Structure is referring to accompanying drawing 3, and principle is summarized as follows:
The upper brachium pontis Q3 of U phase IGBT of take in inverter is example, when upper brachium pontis IGBT drives optocoupler U1 to send the high level signal of conducting IGBT, the first N-channel MOS FET pipe Q1 conducting, thereby the gate clamped of the second N-channel MOS FET pipe Q2 makes the second N-channel MOS FET pipe Q2 turn-off cut-off to low level, high level drives signal to pass through the first resistance R 5 direct effects to the grid of IGBT, thus correct this IGBT of conducting; Subsequently when upper brachium pontis IGBT drives optocoupler U1 to send the low level signal that turn-offs IGBT, the first N-channel MOS FET pipe Q1 cut-off, the grid of managing Q2 due to the second N-channel MOS FET is connected with the positive pole of IGBT driving power by its resistance R7, now the second N-channel MOS FET pipe Q2 enters conducting state immediately, in this process, current potential and the DC bus positive potential at the parasitic capacitance C3 two ends between the collector electrode of upper brachium pontis IGBT and grid CG are basic identical, during the IGBT conducting of brachium pontis instantly, between the IGBT collector and emitter of upper brachium pontis, produce very high du
cE/ dt(is the voltage change ratio between the collector and emitter of IGBT), due to the existence of upper brachium pontis IGBT miller capacitance, this du
cE/ dt will produce by miller capacitance the disturbing pulse of tens to hundreds of nanosecond at the grid of upper brachium pontis, but because the second N-channel MOS FET pipe Q2 is in advance in conducting state, a Low ESR leakage path is provided to this disturbing pulse, thereby the amplitude that has suppressed this disturbing pulse, through reality, test, now go up brachium pontis grid voltage and be suppressed in 3V with interior (referring to accompanying drawing 4, CH1 is the upper brachium pontis grid voltage of representative), lower than threshold voltage of the grid V
gEth(IGBT that the model that German Infinion company produces of take is FP10R12W1T4 is example, V
gEthrepresentative value is 5.8V, and minimum value is 5.2V, and maximum is 6.4V), thus misleading of IGBT effectively suppressed;
The clamped circuit topological structure of MOSFET that suppresses Miller capacitance effect, except suppressing Miller capacitance effect effect, when inverter is short-circuited or the large overcurrent protection such as electric leakage and while turn-offing IGBT fast, existence due to major loop stray inductance in IGBT module, will produce very high-Ldi/dt(L is major loop stray inductance, di/dt is that the current changing rate that IGBT causes is turn-offed in representative fast, negative sign represents that the induced voltage symbol of stray inductance generation is contrary with current changing rate), the grid that this signal also can be coupled to IGBT may cause this to protect the IGBT of shutoff by conducting again, but the existence due to the clamped circuit of MOSFET of this inhibition Miller capacitance effect, this signal also can equally with Miller capacitance effect signal be effectively suppressed.
Advantage of the present invention and beneficial effect: the present invention is by the clamped circuit topological structure of MOSFET, effectively suppress the phenomenon that misleads due to IGBT that Miller capacitance effect causes, greatly reduce the loss of IGBT, extend the useful life of IGBT, and the control performance of motor can not be affected because having increased the clamped circuit of MOSFET of inhibition Miller capacitance effect, and the reliability service of low pressure Small-power Inverter is provided safeguard.
Accompanying drawing explanation
Fig. 1 is that Switching Power Supply provides the four tunnels single power supply system of isolation mutually;
Fig. 2 is that Switching Power Supply provides a road single power supply system;
Fig. 3 is MOSFET clamp circuit topological structure in the present invention;
Fig. 4 is MOSFET clamp circuit inhibition waveform of the present invention;
Fig. 5 adopts the conventional IGBT of increasing grid to drive the inhibition waveform of shunt capacitance between resistance and grid, emitter.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the drawings and specific embodiments, describe the present invention.
Single power supply suppresses a circuit for IGBT Miller capacitance effect, comprises the single power supply system 1 of IGBT drive part, the MOSFET clamp circuit topological structure 2 of inhibition IGBT Miller capacitance effect.
Each brachium pontis driving power that described single power supply system 1 can be inverter independently provides by Switching Power Supply, such as: for three-phase inverter, Switching Power Supply provides an independently positive 15V common driver power supply to brachium pontis under three-phase inverter, to brachium pontis on three-phase inverter, respectively provide a positive 15V driving power in road, this mode switch power supply provides the four tunnels unipolarity driving power of isolation mutually altogether to three-phase inverter, referring to accompanying drawing 1, wherein+U and OU are U phase upper arm unipolarity driving power, + V and OV are V phase upper arm unipolarity driving power, + W and OW are W phase upper arm unipolarity driving power, + L and OL are three-phase underarm unipolarity driving power,
Described single power supply system 1 can also be Switching Power Supply only provides a road unipolarity power supply to the driving of inverter, this power supply provides driving directly to the lower brachium pontis IGBT of inverter, each IGBT driving power of upper brachium pontis all obtains by Boost mode, referring to accompanying drawing 2;
Described MOSFET(Chinese full name is mos field effect transistor, be called for short metal half field effect transistor or MOSFET) clamp circuit topological structure, comprise the first N-channel MOS FET pipe Q1, the resistance R6 of the second N-channel MOS FET pipe Q2, the first N-channel MOS FET pipe Q1, the resistance R7 of the second N-channel MOS FET pipe Q2, the first resistance R 5, the second resistance R 8, driving signal capacitor C 52, pull down resistor R8, is characterized in that:
The upper brachium pontis of IGBT in inverter drives the driving signal of optocoupler U1 to pass through the first resistance R 5 direct effects to the grid of IGBT, the grid of the first N-channel MOS FET pipe Q1 is connected with the output of optocoupler U1 by the second resistance R 6, the gate pole of the second N-channel MOS FET pipe Q2 is connected with the positive pole of IGBT driving power by its resistance R7, the drain electrode of the first N-channel MOS FET pipe Q1 is directly connected with the grid of the second N-channel MOS FET pipe Q2, the source electrode of the source electrode of the first N-channel MOS FET pipe Q1 and the second N-channel MOS FET pipe Q2 is directly connected on the ground U-network of single power supply,
Described pull down resistor R8 is in parallel with driving signal capacitor C 52, and the first filter capacitor C1 of single power supply system 1, the second filtering C2 are in parallel, are one end and are connected with the anodal U+ of single power supply system 1, and the other end is connected with the ground U-of single power supply system 1; Described pull down resistor R8 prevents the electrostatic breakdown of IGBT grid, and described driving signal capacitor C 52 prevents that other interference of IGBT from misleading.
Structure is referring to accompanying drawing 3, and principle is summarized as follows:
The upper brachium pontis Q3 of U phase IGBT of take in inverter is example, when upper brachium pontis IGBT drives optocoupler U1 to send the high level signal of conducting IGBT, the first N-channel MOS FET pipe Q1 conducting, thereby the gate clamped of the second N-channel MOS FET pipe Q2 makes the second N-channel MOS FET pipe Q2 turn-off cut-off to low level, high level drives signal to pass through the first resistance R 5 direct effects to the grid of IGBT, thus correct this IGBT of conducting; Subsequently when upper brachium pontis IGBT drives optocoupler U1 to send the low level signal that turn-offs IGBT, the first N-channel MOS FET pipe Q1 cut-off, the grid of managing Q2 due to the second N-channel MOS FET is connected with the positive pole of IGBT driving power by its resistance R7, now the second N-channel MOS FET pipe Q2 enters conducting state immediately, in this process, current potential and the DC bus positive potential at the parasitic capacitance C3 two ends between the collector electrode of upper brachium pontis IGBT and grid CG are basic identical, during the IGBT conducting of brachium pontis instantly, between the IGBT collector and emitter of upper brachium pontis, produce very high du
cE/ dt(is the voltage change ratio between the collector and emitter of IGBT), due to the existence of upper brachium pontis IGBT miller capacitance, this du
cE/ dt will produce by miller capacitance the disturbing pulse of tens to hundreds of nanosecond at the grid of upper brachium pontis, but because the second N-channel MOS FET pipe Q2 is in advance in conducting state, a Low ESR leakage path is provided to this disturbing pulse, thereby has suppressed the amplitude of this disturbing pulse;
In a specific embodiment, employing be two N-channel MOS FET pipes, its drain-source voltage V
dSSbe greater than 60V, gate source voltage V
gSbe not less than 20V, for do not affect as far as possible, from optocoupler output, do not open signal to the gate delay time of IGBT, the resistance R6 resistance of the first N-channel MOS FET pipe Q1 is got 100 ohm, the resistance R7 of the second N-channel MOS FET pipe Q2 is unsuitable too small, otherwise when the first N-channel MOS FET pipe Q1 conducting, R7 is upper by consuming excessive driving power power, while especially adopting the second single power supply system, does not allow especially, in addition, owing to being avoid IGBT upper and lower bridge arm straight-through, the driving signal of upper and lower bridge arm is all provided with the Dead Time of Microsecond grade, even the resistance resistance of the second N-channel MOS FET pipe Q2 is larger in this Dead Time, also conducting in time, therefore, the resistance of the second N-channel MOS FET pipe Q2 can be got larger resistance, avoid driving power that excessive power is provided on the one hand, on the other hand due to the existence of Dead Time, the second N-channel MOS FET pipe Q2 timely conducting that is able to do in time completely, in the present embodiment, the second N-channel MOS FET pipe Q2 resistance is got 1k Ω.In this topological structure, although the resistance resistance of the second N-channel MOS FET pipe Q2 is larger, but when the first N-channel MOS FET pipe Q1 conducting, to the basis gate charge of the MOSFET pipe of conducting, provide an anti-leakage path of Quick-speed low-resistance, the second N-channel MOS FET pipe Q2 is turn-offed with the fastest speed cut-off, like this with regard to guaranteed to drive the output of optocoupler U1 open signal almost without time delay be transferred to the grid of IGBT, the control performance that makes motor can not suppress the MOSFET clamped circuit of Miller capacitance effect and not be affected because having increased.Through reality test, now go up brachium pontis grid voltage and be suppressed in 3V with interior (referring to accompanying drawing 4, CH1 is the upper brachium pontis grid voltage of representative), lower than threshold voltage of the grid V
gEth(IGBT that the model that German Infinion company produces of take is FP10R12W1T4 is example, V
gEthrepresentative value is 5.8V, and minimum value is 5.2V, and maximum is 6.4V), thus misleading of IGBT effectively suppressed;
This suppresses the clamped circuit topological structure of MOSFET of Miller capacitance effect; except suppressing Miller capacitance effect effect; when inverter is short-circuited or the large overcurrent protection such as electric leakage and while turn-offing IGBT fast; due in IGBT module and the existence of major loop stray inductance; will produce very high-Ldi/dt; the grid that this signal also can be coupled to IGBT may cause this to protect the IGBT of shutoff by conducting again; but due to the existence of the clamped circuit of MOSFET of this inhibition Miller capacitance effect, this signal also can equally with Miller capacitance effect signal be effectively suppressed.
Fig. 4 is MOSFET clamp circuit inhibition waveform of the present invention, wherein, CH1-upper arm IGBT grid drive waveforms, the former limit of CH2-upper arm optocoupler drive waveforms (low conducting), the former limit of CH3-underarm optocoupler drive waveforms (low conducting), CH4-upper and lower bridge arm is through current waveform in short-term, CH1 is IGBT driving voltage waveform, can see and adopt the circuit inhibition grid voltage peak value that misleads that Miller capacitance effect causes afterwards of the present invention less than 3V, CH4 is through current waveform in short-term, can find out the about 0.5A of this current peak;
Fig. 5 adopts the conventional IGBT of increasing grid to drive resistance and grid, the inhibition waveform of shunt capacitance between emitter, wherein, CH5---IGBT grid drive waveforms, CH6---the former limit of upper arm optocoupler drive waveforms (low conducting), CH7---the former limit of underarm optocoupler drive waveforms (low conducting), CH8---upper and lower bridge arm is through current waveform in short-term, CH1 is IGBT driving voltage waveform, can see that the grid voltage peak value that misleads that after adopting conventional method to suppress, Miller capacitance effect causes reaches 8V, CH4 is through current waveform in short-term, can find out, this current peak reaches about 2A.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, as long as within the spirit and principles in the present invention, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (4)
1. single power supply suppresses a circuit for IGBT Miller capacitance effect, comprises the single power supply system (1) of IGBT drive part, the MOSFET clamp circuit topological structure (2) of inhibition IGBT Miller capacitance effect, it is characterized in that,
Described MOSFET clamp circuit topological structure (2), comprise the first N-channel MOS FET pipe (Q1), the second N-channel MOS FET pipe (Q2), the resistance (R6) of the first N-channel MOS FET pipe (Q1), the resistance (R7) of the second N-channel MOS FET pipe (Q2), the first resistance (R5), the second resistance (R8), drive signal electric capacity (C52), pull down resistor (R8), the upper brachium pontis of IGBT in inverter drives the driving signal of optocoupler (U1) to pass through the first resistance (R5) direct effect to the grid of IGBT, the grid of the first N-channel MOS FET pipe (Q1) is connected with the output of optocoupler (U1) by the second resistance (R6), the gate pole of the second N-channel MOS FET pipe (Q2) is connected with the positive pole of IGBT driving power by its resistance (R7), the drain electrode of the first N-channel MOS FET pipe (Q1) is directly connected with the grid that the second N-channel MOS FET manages (Q2), the source electrode of the source electrode of the first N-channel MOS FET pipe (Q1) and the second N-channel MOS FET pipe (Q2) is directly connected on the ground U-network of single power supply, described pull down resistor (R8) is in parallel with driving signal electric capacity (C52), first filter capacitor (C1) of single power supply system (1), the second filtering (C2) parallel connection, be one end and be connected with the anodal U+ of single power supply system (1), the other end is connected with the ground U-of single power supply system (1), described pull down resistor (R8) prevents the electrostatic breakdown of IGBT grid, and described driving signal electric capacity (C52) prevents that other interference of IGBT from misleading.
2. single power supply according to claim 1 suppresses the circuit of IGBT Miller capacitance effect, it is characterized in that,
Described single power supply system (1) is that each brachium pontis driving power of inverter independently provides by Switching Power Supply.
3. single power supply according to claim 1 suppresses the circuit of IGBT Miller capacitance effect, it is characterized in that,
Described single power supply system (1) is Switching Power Supply only provides a road unipolarity power supply to the driving of inverter, and this power supply provides driving directly to the lower brachium pontis IGBT of inverter, and each IGBT driving power of upper brachium pontis all obtains by Boost mode.
4. single power supply according to claim 1 suppresses the circuit of IGBT Miller capacitance effect, it is characterized in that,
For avoiding the straight-through of IGBT upper and lower bridge arm, the driving signal of upper and lower bridge arm is all provided with the Dead Time of Microsecond grade, the drain-source voltage V of the first N-channel MOS FET pipe (Q1) and the second N-channel MOS FET pipe (Q2)
dSSbe greater than 60V, gate source voltage V
gSbe not less than 20V; Resistance (R6) resistance of the first N-channel MOS FET pipe (Q1) is got 100 ohm, 1000 ohm of resistance (R7) values of the second N-channel MOS FET pipe (Q2), second N-channel MOS FET pipe (Q2) conducting in time in this Dead Time.
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| CN112564461A (en) * | 2019-09-26 | 2021-03-26 | 珠海格力电器股份有限公司 | Power switch circuit system |
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| CN103683883B (en) | 2015-12-09 |
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