CN103682005A - LED epitaxial growth process - Google Patents

LED epitaxial growth process Download PDF

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Publication number
CN103682005A
CN103682005A CN201210334114.0A CN201210334114A CN103682005A CN 103682005 A CN103682005 A CN 103682005A CN 201210334114 A CN201210334114 A CN 201210334114A CN 103682005 A CN103682005 A CN 103682005A
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Prior art keywords
epitaxial layer
layer
led
processing procedure
heap
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CN103682005B (en
Inventor
林雅雯
黄世晟
凃博闵
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Guangdong Xuan Ze Yitai Culture Communication Co ltd
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Rongchuang Energy Technology Co ltd
Zhanjing Technology Shenzhen Co Ltd
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Priority to CN201210334114.0A priority Critical patent/CN103682005B/en
Priority to TW101133911A priority patent/TW201411696A/en
Priority to US13/958,612 priority patent/US20140073077A1/en
Publication of CN103682005A publication Critical patent/CN103682005A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Abstract

An LED epitaxial growth process comprises the following steps: growing a buffer layer on the surface of a substrate; growing an epitaxial layer on the surface of the buffer layer at a first temperature; growing a second epitaxial layer on the surface of the first epitaxial layer at a second temperature which is lower than the first temperature so as to roughen the surface of the second epitaxial layer; etching the second epitaxial layer and the first epitaxial layer until the rough surface of the second epitaxial layer is duplicated on the first epitaxial layer; depositing a silicon dioxide layer on the rough surface of the first epitaxial layer; etching the top surface of the silicon dioxide layer until exposing the first epitaxial layer so as to form a plurality of bumps; sequentially growing an N-type epitaxial layer, a light emitting layer and a P-type epitaxial layer on the first epitaxial layer. The rough surface of the first epitaxial layer and the bumps on the silicon dioxide layer can effectively reflect and block light emitted by the light emitting layer so as to improve luminous efficiency of an LED grain.

Description

LED builds brilliant processing procedure
Technical field
The present invention relates to a kind of LED brilliant processing procedure of heap of stone, relate in particular to a kind of LED brilliant processing procedure of heap of stone with better light extraction efficiency.
Background technology
Light-emitting diode (Light Emitting Diode, LED) is a kind ofly current conversion can be become to the optoelectronic semiconductor component of particular range of wavelengths.The advantages such as light-emitting diode is high with its brightness, operating voltage is low, power consumption is little, it is simple easily to mate with integrated circuit, drive, the life-span is long, thus can be used as light source and be widely used in lighting field.
In the growth course of LED crystal grain, because the structure of LED is to build crystal type to be grown on sapphire substrate, of heap of stone brilliant very big with lattice constant and the thermal expansion coefficient difference of sapphire substrate, so can produce the poor row of high-density lines (Thread Dislocation), this kind of poor row of high-density lines can limit the luminous efficiency of LED.In addition, in the structure of LED, except luminescent layer (Active Layer) and other epitaxial layer can absorb light, the light that its semi-conductive high index of refraction also can make LED produce is limited to, and often produce total internal reflection and make most of light sending from luminescent layer, be limited in semiconductor inside, this light being limited to is likely absorbed by thicker substrate.So how from semi-conductive luminescent layer extraction light source, and then increase light extraction efficiency, it is the problem that current LED industry is made great efforts.
Summary of the invention
In view of this, be necessary to provide a kind of LED brilliant processing procedure of heap of stone with better light extraction efficiency.
LED builds a brilliant processing procedure, comprises the following steps:
Provide a substrate, the resilient coating of growing on the surface of described substrate;
At the first temperature, at first epitaxial layer of superficial growth of resilient coating;
At the second temperature lower than the first temperature, at superficial growth second epitaxial layer of the first epitaxial layer, thereby make the surface roughening of the second epitaxial layer;
Etching the second epitaxial layer and the first epitaxial layer, until carve again the rough surface of the second epitaxial layer to the first epitaxial layer;
Rough surface deposition layer of silicon dioxide layer at the first epitaxial layer;
The end face of silicon dioxide layer described in etching until expose the first epitaxial layer, forms a plurality of projections with the end face at silicon dioxide layer; And
At the first epitaxial layer grow up successively a N-type epitaxial layer, a luminescent layer and a P type epitaxial layer.
In above-mentioned LED brilliant processing procedure of heap of stone, because the surface of the second epitaxial layer is matsurface, and the end face of described silicon dioxide layer forms a plurality of projections with etching mode, by described matsurface and described projection to reflection of light, barrier effect, the rising angle of described LED epitaxial structure will be comparatively narrow, the narrow effect with concentrated light of rising angle, effectively improves the luminous intensity of described LED crystal grain.
Accompanying drawing explanation
Fig. 1 is first step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 2 is the second step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 3 is the 3rd step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 4 is the 4th step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 5 is the five steps of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 6 is the 6th step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 7 is the 7th step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Fig. 8 is the schematic top plan view of the silicon dioxide layer in Fig. 7.
Fig. 9 is the schematic top plan view of another embodiment of the silicon dioxide layer in Fig. 7.
Figure 10 is the 8th step of the LED that provides of first embodiment of the invention brilliant processing procedure of heap of stone.
Figure 11 is the schematic cross-section of the LED that provides of second embodiment of the invention brilliant processing procedure of heap of stone.
Figure 12 is the schematic cross-section of the LED that provides of third embodiment of the invention brilliant processing procedure of heap of stone.
Main element symbol description
Substrate 110
Projection 111
Resilient coating 120
The first epitaxial layer 130
Rough surface 131
The second epitaxial layer 140
Rough surface 141
Silicon dioxide layer 150
Projection 151
Gap 152
N-type epitaxial layer 160
Luminescent layer 170
P type epitaxial layer 180
Cover layer 190
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Referring to diagram, LED of the present invention brilliant processing procedure of heap of stone is further detailed.
Refer to Fig. 1, first a substrate 110 is provided.In the present embodiment, described substrate 110 is sapphire substrate, and described sapphire substrate has a smooth surface.
Refer to Fig. 2, the resilient coating 120 of growing up on substrate 110.
Refer to Fig. 3, first epitaxial layer 130 of growing up on resilient coating 120.Described the first epitaxial layer 130 is grown at the first temperature.In the present embodiment, the temperature range of described the first temperature is 1100 ℃ to 1300 ℃.Described the first epitaxial layer 130 can be the GaN layer of unadulterated GaN layer or N-type doping.
Refer to Fig. 4, second epitaxial layer 140 of growing up on the first epitaxial layer 130.The growth course of described the second epitaxial layer 140 is carried out at the second temperature lower than the first temperature, thereby forms a rough surface 141 at the end face of the second epitaxial layer 140.In the present embodiment, the temperature range of described the second temperature is 500 ℃ to 600 ℃.Similarly, described the second epitaxial layer 140 can be the GaN layer of unadulterated GaN layer or N-type doping.
Refer to Fig. 5, adopt inductively coupled plasma etching method etching the second epitaxial layer 140 and the first epitaxial layer 130, until the rough surface of the second epitaxial layer 140 141 is carved to the first epitaxial layer 130 again.In above-mentioned etching process, due to the etched etched thickness of inductively coupled plasma and etching period proportional, after the etched removal in the less region of the thickness of the second epitaxial layer 140, the region of the first epitaxial layer 130 exposing will be continued etched.After the second epitaxial layer 140 is completely removed, the shape on the second epitaxial layer 140 surfaces will be copied to the surface of the first epitaxial layer 130, thereby forms rough surface 131 on the first epitaxial layer 130.As required, can also pass through reaction ionic etching method (RIE, Reactive Ion Etching) etching the second epitaxial layer 140 and the first epitaxial layer 130, until the rough surface of the second epitaxial layer 140 141 is carved to the first epitaxial layer 130 again.
Refer to Fig. 6, on the rough surface 131 of the first epitaxial layer 130, deposit layer of silicon dioxide layer 150.
Refer to Fig. 7, the end face of silicon dioxide layer 150 described in etching until expose the first epitaxial layer 130, forms a plurality of protruding 151 with the end face at silicon dioxide layer 150.Described protruding 151 shape is restriction not, and it can be circle, rectangle or polygon.Refer to Fig. 8, described protruding 151 is hexagonal shape, and it is arranged in honeycomb shape.Refer to Fig. 9, described protruding 151 is circular.Described protruding 151 diameter is between 2 microns to 3 microns.Between projection 151 and projection 151, be formed with gap 152, the size in described gap 152 is between 1 micron to 2 microns.In the present embodiment, described protruding 151 diameter is 3 microns, and the gap 152 between projection 151 and projection 151 is 2 microns.As required, described protruding 151 diameter can be also 2 microns, and the gap 152 between corresponding projection 151 and projection 151 is 1 micron.
Refer to Figure 10, the N-type epitaxial layer 160 of growing up successively, luminescent layer 170 and a P type epitaxial layer 180 on the first epitaxial layer 130.In the present embodiment, the making material of described N-type epitaxial layer 160, luminescent layer 170 and P type epitaxial layer 180 be selected from GaN, AlGaN, InGaN and AlInGaN one of them.
In the course of work of above-mentioned LED crystal grain, between P type epitaxial layer 180 and N-type epitaxial layer 160, apply a forward voltage, in hole in P type epitaxial layer 180 and N-type epitaxial layer 160, electronics will be compound in luminescent layer 170, and energy discharges with the form of light.Because the end face of silicon dioxide layer 150 is formed with a plurality of protruding 151, and be formed with rough surface 131 on the first epitaxial layer 130, the light that described rough surface 131 and described protruding 151 will send luminescent layer 170 produces and stops and reflex, thereby the light that luminescent layer 170 sends is upwards concentrated, effectively to improve the luminous intensity of described LED crystal grain.
As required, described LED brilliant processing procedure of heap of stone is not limited to above-mentioned execution mode.Refer to Figure 11, end face at silicon dioxide layer 150 forms after a plurality of protruding 151, can be further on the surface of the first epitaxial layer 130 and silicon dioxide layer 150, form a cover layer 190, and then the N-type epitaxial layer 160 of growing up successively on cover layer 190, luminescent layer 170 and a P type epitaxial layer 180.Described cover layer 190 can be aluminium nitride (AlN) thin layer, and it grows at the first temperature.Described aluminum nitride thin rete contributes to the deposition of follow-up N-type epitaxial layer 160, luminescent layer 170 and P type epitaxial layer 180.
As required, described substrate 110 is also not limited to above-mentioned execution mode.Refer to Figure 12, the sapphire substrate that described substrate 110 is patterning, the surface of described sapphire substrate is formed with a plurality of protruding 111.Substrate 110 in alternative first embodiment of sapphire substrate of above-mentioned patterning, and then the epitaxial structure layer of growing follow-up on the sapphire substrate of patterning.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change and distortion all should belong to the protection range of the claims in the present invention.

Claims (10)

1. a LED brilliant processing procedure of heap of stone, comprises the following steps:
Provide substrate, grown buffer layer on the surface of described substrate;
At the first temperature, at superficial growth first epitaxial layer of resilient coating;
At the second temperature lower than the first temperature, at superficial growth second epitaxial layer of the first epitaxial layer, thereby make the surface roughening of the second epitaxial layer;
Etching the second epitaxial layer and the first epitaxial layer, until carve again the rough surface of the second epitaxial layer to the first epitaxial layer;
Rough surface deposition of silica layer at the first epitaxial layer;
The end face of etch silicon dioxide layer is until expose the first epitaxial layer, to form a plurality of projections; And
On the first epitaxial layer, grow up successively N-type epitaxial layer, luminescent layer and P type epitaxial layer.
2. LED as claimed in claim 1 brilliant processing procedure of heap of stone, is characterized in that, the temperature range of described the first temperature is 1100 ℃-1300 ℃.
3. LED as claimed in claim 2 brilliant processing procedure of heap of stone, is characterized in that, the temperature range of described the second temperature is 500 ℃-600 ℃.
4. LED as claimed in claim 1 builds brilliant processing procedure, it is characterized in that, after forming a plurality of projections, further on the surface of the first epitaxial layer and silicon dioxide layer, form cover layer, and then the described N-type epitaxial layer of growing up successively on cover layer, described luminescent layer and described P type epitaxial layer, described cover layer is grown at the first temperature.
5. LED as claimed in claim 4 brilliant processing procedure of heap of stone, is characterized in that, described cover layer is aluminum nitride thin rete.
6. LED as claimed in claim 1 brilliant processing procedure of heap of stone, is characterized in that, the diameter of described projection is 2 microns to 3 microns.
7. LED as claimed in claim 1 brilliant processing procedure of heap of stone, is characterized in that, between described projection and projection, be formed with gap, the size in described gap is between 1 micron to 2 microns.
8. LED as claimed in claim 1 brilliant processing procedure of heap of stone, is characterized in that, described substrate is sapphire substrate, and the end face of institute's sapphire substrate is formed with a plurality of projections.
9. LED as claimed in claim 1 brilliant processing procedure of heap of stone, is characterized in that, described substrate is sapphire substrate, and the end face of described sapphire substrate is smooth surface.
10. LED as claimed in claim 1 brilliant processing procedure of heap of stone, is characterized in that, the making material of described N-type epitaxial layer, luminescent layer and P type epitaxial layer be selected from GaN, AlGaN, InGaN and AlInGaN one of them.
CN201210334114.0A 2012-09-12 2012-09-12 LED epitaxial growth processing procedure Expired - Fee Related CN103682005B (en)

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CN201210334114.0A CN103682005B (en) 2012-09-12 2012-09-12 LED epitaxial growth processing procedure
TW101133911A TW201411696A (en) 2012-09-12 2012-09-17 Epitaxial method for making LED chip
US13/958,612 US20140073077A1 (en) 2012-09-12 2013-08-05 Method for epitaxial growth of light emitting diode

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CN111129238A (en) * 2014-11-06 2020-05-08 上海芯元基半导体科技有限公司 III-V group nitride semiconductor epitaxial wafer, device comprising epitaxial wafer and preparation method of device

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CN1423842A (en) * 1999-12-03 2003-06-11 美商克立光学公司 Enhanced light extration in LEDS through the use of internal and external optical elements
US20050202581A1 (en) * 2002-12-19 2005-09-15 Kabushiki Kaisha Toshiba Method of manufacturing nitride based semiconductor light-emitting device
US20080169482A1 (en) * 2007-01-11 2008-07-17 Dae Sung Kang Semiconductor light emitting device and a method for manufacturing the same
CN101636849A (en) * 2006-12-22 2010-01-27 皇家飞利浦电子股份有限公司 Be grown on the template to reduce the III group-III nitride luminescent device of strain
US20100019263A1 (en) * 2008-07-24 2010-01-28 Advanced Optoelectronic Technology Inc. Rough structure of optoelectronic device and fabrication thereof

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EP3699963A1 (en) * 2003-08-19 2020-08-26 Nichia Corporation Semiconductor light emitting diode and method of manufacturing its substrate
US20070272930A1 (en) * 2006-05-26 2007-11-29 Huan-Che Tseng Light-emitting diode package
KR101081062B1 (en) * 2010-03-09 2011-11-07 엘지이노텍 주식회사 Light emitting device, method for fabricating the light emitting device and light emitting device package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1423842A (en) * 1999-12-03 2003-06-11 美商克立光学公司 Enhanced light extration in LEDS through the use of internal and external optical elements
US20050202581A1 (en) * 2002-12-19 2005-09-15 Kabushiki Kaisha Toshiba Method of manufacturing nitride based semiconductor light-emitting device
CN101636849A (en) * 2006-12-22 2010-01-27 皇家飞利浦电子股份有限公司 Be grown on the template to reduce the III group-III nitride luminescent device of strain
US20080169482A1 (en) * 2007-01-11 2008-07-17 Dae Sung Kang Semiconductor light emitting device and a method for manufacturing the same
US20100019263A1 (en) * 2008-07-24 2010-01-28 Advanced Optoelectronic Technology Inc. Rough structure of optoelectronic device and fabrication thereof

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TW201411696A (en) 2014-03-16
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