CN111129238A - III-V group nitride semiconductor epitaxial wafer, device comprising epitaxial wafer and preparation method of device - Google Patents
III-V group nitride semiconductor epitaxial wafer, device comprising epitaxial wafer and preparation method of device Download PDFInfo
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Abstract
The present invention provides a group iii-v nitride semiconductor epitaxial wafer, including: 1) a substrate (101); 2) an epitaxial buffer layer (102); 3) a plurality of semiconductor medium bumps (107); 4) an epitaxial transition layer (108); and 5) an epitaxial effective layer, wherein the epitaxial effective layer contains an n-type epitaxial layer (109), a light-emitting layer (110) and a p-type epitaxial layer (111) from bottom to top. The invention also provides a manufacturing method of the epitaxial wafer, a device containing the epitaxial wafer and a preparation method of the device. The epitaxial wafer structure can effectively improve the quality of the epitaxial wafer, such as dislocation density, and can improve various performance indexes of a semiconductor device, particularly luminous efficiency, leakage current, antistatic breakdown property and the like. The preparation method has simple process, is beneficial to reducing the manufacturing cost, and is suitable for industrial production.
Description
The present application is a divisional application of invention patent application No. 201480009733.X entitled "a iii-v group nitride semiconductor epitaxial wafer, a device including the same, and a method for manufacturing the same" filed 11/6/2014.
Technical Field
The invention relates to the field of semiconductor illumination, in particular to a III-V group nitride semiconductor epitaxial wafer, a device comprising the epitaxial wafer and a manufacturing method of the device.
Background
Semiconductor lighting is used as a novel high-efficiency solid light source, has the advantages of long service life, energy conservation, environmental protection, safety and the like, and the application field of the semiconductor lighting is rapidly expanding. The heart of semiconductor lighting is a Light Emitting Diode (LED), which is structurally a PN junction formed by semiconductors of III-V compounds, such as GaAs (gallium arsenide), GaP (gallium phosphide), GaAsP (gallium arsenide phosphide), GaN (gallium nitride), and the like. Therefore, the semiconductor device has the I-V characteristics of a general PN junction, namely forward conduction, reverse cut-off and breakdown characteristics. In addition, it has a luminescent property under certain conditions. Under forward voltage, electrons are injected from the N region to the P region, and holes are injected from the P region to the N region. A part of the minority carrier (minority carrier) entering the opposite region is recombined with the majority carrier (majority carrier) to emit light.
In order to increase the light emitting efficiency of the LED, a light emitting layer including an active region of a quantum well is generally added between an N-type layer and a P-type layer of a PN junction, and the specific structure of the LED is mostly grown on a substrate in sequence according to the order of the N-type layer, the active region, and the P-type layer by using an epitaxial growth method. Since there is no inexpensive GaN homogeneous substrate, GaN-based LEDs are generally grown on a heterogeneous substrate such as Si, SiC, or sapphire, which is the most widely used substrate. The material with the n-type layer, the light-emitting layer and the p-type layer is made on the substrate by an epitaxial growth method and is called an LED epitaxial wafer. The LED device can be manufactured on the LED epitaxial wafer through conventional semiconductor processes of preparing an n electrode, a p electrode, an isolation protection layer and the like.
The epitaxial growth of GaN transition layers on sapphire and other heterogeneous substrates generally adopts a two-step growth method. The so-called two-step growth method is: firstly, a GaN or AlGaN buffer layer (buffer layer) with the thickness of about 30 nanometers grows on the surface of a sapphire substrate at the growth temperature of about 500 ℃, and then the growth temperature is increased to more than 1000 ℃ so as to grow a high-quality GaN epitaxial layer. The device structure manufactured by the method has a large amount of dislocation, and the higher the dislocation density is, the lower the luminous efficiency of the device is.
The most widely used technique called sapphire pattern substrate (PSS) is now applied, which can reduce the dislocation density in the epitaxial layer and improve the internal quantum efficiency of the LED, and can also improve the light-emitting efficiency of the LED by the diffuse scattering of the PSS pattern. The conventional PSS technique is to form a microscopic pattern on the sapphire surface using a photolithography process and an etching process. For example, conical protrusions with a certain periodic structure still made of sapphire material are formed on the sapphire surface with the (0001) crystal orientation, and a certain area of the (0001) crystal plane is reserved between the conical protrusions. Since a certain selective growth mechanism exists between the surface of the tapered protrusions and the (0001) crystal plane between the tapered protrusions, that is, when epitaxial growth is performed, the probability of nucleation on the (0001) crystal plane between the tapered protrusions is greater than that on the surface of the tapered protrusions, and the epitaxial layer on the tapered protrusions is generally formed by lateral growth, the epitaxial growth performed on the PSS substrate has the effect of lateral growth, which can reduce the dislocation density in the epitaxial layer and improve the internal quantum efficiency of the LED using the PSS substrate. On the other hand, the microstructure on the surface of the PSS substrate has a certain diffuse scattering effect on light emitted by the LED and can destroy the total reflection effect, so that the light emitting efficiency of the LED can be improved by the PSS substrate. The two-step method described above is also used to grow LED epitaxial structures on conventional PSS substrates.
Conventional PSS techniques also have a number of drawbacks. Firstly, the processing difficulty of sapphire is very high regardless of a wet method or a dry method, which not only affects the product yield of the conventional PSS, but also increases the manufacturing cost; secondly, since the growth selectivity between the surface of the sapphire pyramidal protrusions and the (0001) crystal plane between the pyramidal protrusions is not very significant, if the area of the (0001) crystal plane between the pyramidal protrusions is too small, nucleation occurs on the surface of the pyramidal protrusions, and the crystal orientation of crystal nuclei formed on the surface of the pyramidal protrusions is different from the crystal orientation of crystal nuclei formed on the (0001) crystal plane between the pyramidal protrusions, which easily results in the generation of polycrystals; thirdly, since the refractive index of the sapphire substrate is high, about 1.8, even if a convex structure is formed on the surface of the sapphire substrate, the diffuse scattering effect of light emitted by the LED is not optimal, and the improvement of the light extraction efficiency is also greatly limited.
The LED epitaxial wafer is the core of the LED device. The quality of each layer of crystal in the epitaxial wafer directly influences the parameters of the LED device such as luminous efficiency, leakage current, electrostatic breakdown voltage and the like. Therefore, it is necessary to provide a novel semiconductor epitaxial wafer, a device and a related manufacturing method, which can effectively improve the crystal quality, such as dislocation density, and can improve various performance indexes of the LED, especially the light emitting efficiency, leakage current, antistatic breakdown property and the like of the LED.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, it is an object of the present invention to provide a group iii-v nitride semiconductor epitaxial wafer, a device including the same, and a method of manufacturing the same.
In one aspect, the present invention provides a group iii-v nitride semiconductor epitaxial wafer, comprising:
1) a substrate (101);
2) an epitaxial buffer layer (102) having an upper surface and a lower surface in contact with the substrate;
3) a plurality of semiconductor medium bulges (107) which are arranged at intervals on the upper surface of the epitaxial buffer layer and are contacted with the upper surface of the epitaxial buffer layer, and the epitaxial buffer layer is exposed among the bulges;
4) an epitaxial transition layer (108) covering the semiconductor dielectric bumps and the exposed epitaxial buffer layer therebetween, the epitaxial transition layer being in contact with the exposed epitaxial buffer layer and the semiconductor dielectric bumps, the epitaxial transition layer completely covering the semiconductor dielectric bumps and completely filling the spaces between the semiconductor dielectric bumps;
5) and the epitaxial effective layer is positioned on the upper surface of the epitaxial transition layer and contains an n-type epitaxial layer (109), a light emitting layer (110) and a p-type epitaxial layer (111) from bottom to top.
In a second aspect, the invention provides a iii-v nitride semiconductor device comprising the epitaxial wafer and an n-electrode (113) and a p-electrode (114) in electrical communication with the n-epitaxial layer and the p-epitaxial layer, respectively.
In another aspect, the present invention also provides a method for manufacturing a group iii-v nitride semiconductor epitaxial wafer, comprising the steps of:
1) providing a substrate (101);
2) depositing an epitaxial buffer layer (102) on the substrate;
3) depositing a layer of semiconductor medium (103) on the epitaxial buffer layer, and patterning the semiconductor medium layer to form a plurality of semiconductor medium bulges (107) arranged at intervals, wherein the epitaxial buffer layer is exposed among the bulges;
4) depositing an epitaxial transition layer (108) on the exposed part of the epitaxial buffer layer until the thickness of the epitaxial transition layer is higher than the height of the semiconductor medium bump;
5) and growing an epitaxial effective layer on the upper surface of the epitaxial transition layer, wherein the epitaxial effective layer comprises an n-type epitaxial layer (109), a light emitting layer (110) and a p-type epitaxial layer (111) from bottom to top.
Finally, the present invention also provides a method of fabricating a group iii-v nitride semiconductor device, the method comprising fabricating on the epitaxial wafer an n-electrode and a p-electrode in electrical communication with the n-type epitaxial layer and the p-type epitaxial layer, respectively.
The invention can effectively improve the crystal quality of the epitaxial wafer, such as dislocation density, and can improve various performance indexes of the semiconductor device, especially luminous efficiency, leakage current, antistatic breakdown property and the like. Particularly, compared with the conventional PSS, the method has the advantages that the patterned semiconductor dielectric layer is used for replacing the sapphire patterned layer, so that the growth selectivity and the light scattering effect are improved. The preparation method has simple process, is beneficial to reducing the manufacturing cost, and is suitable for industrial production.
Drawings
Fig. 1to 2 are schematic structural views of steps 1) and 2) in the method for manufacturing a iii-v nitride semiconductor epitaxial wafer according to the present invention.
Fig. 3 to 7 are schematic structural views of step 3) in the method for manufacturing a iii-v nitride semiconductor epitaxial wafer according to the present invention.
Fig. 8 is a schematic structural view of step 4) in the method for manufacturing a iii-v nitride semiconductor epitaxial wafer according to the present invention.
Fig. 9 is a schematic structural view of step 5) in the method for manufacturing a iii-v nitride semiconductor epitaxial wafer according to the present invention.
Fig. 10A is a schematic cross-sectional view of a structure presented in a method of manufacturing a group iii-v nitride semiconductor device according to the present invention.
Fig. 10B shows a top view of the structure presented in fig. 10A.
Description of the element reference numerals
101 substrate
102 epitaxial buffer layer
103 semiconductor dielectric layer
104 photoresist layer
105 photoresist block
106-bag-shaped photoresist block
107 semiconductor dielectric bump
108 epitaxial transition layer
109 n type epitaxial layer
110 light emitting layer
111 p type epitaxial layer
112 transparent current spreading layer
113 n electrode
114 p electrode
Detailed Description
In the present invention, the group III-V nitride semiconductor means a nitride semiconductor of group III element of the periodic table such as GaN, GaAlN, InGaN, InAlGaN.
As a preferable mode of the III-V nitride semiconductor epitaxial wafer of the present invention, the substrate is made of a material selected from Al2O3SiC, Si, ZnO and GaN.
In a preferred embodiment of the group iii-v nitride semiconductor epitaxial wafer of the present invention, the epitaxial buffer layer has a thickness of 50 to 600 angstroms, preferably 100 to 500 angstroms, and more preferably 200to 400 angstroms. The excessively thin buffer layer cannot meet the nucleation requirement required by the subsequent epitaxial growth, so that the growth quality of the epitaxial layer is reduced; the excessively thick buffer layer can cause insufficient recrystallization of the buffer layer in the subsequent annealing process, and the quality of the epitaxial layer is influenced; an excessively thick buffer layer also affects the light extraction efficiency of the semiconductor device (e.g., LED device) being fabricated.
As a preferable mode of the III-V nitride semiconductor epitaxial wafer of the invention, the epitaxial buffer layer is selected from AlxGa1-xN layer, X is more than or equal to 0 and less than or equal to 0.5, preferably X is more than or equal to 0 and less than or equal to 0.2; and an AlN layer whose crystal orientation is (0001).
In a preferred embodiment of the III-V nitride semiconductor epitaxial wafer of the invention, the height of the semiconductor medium bump is 0.2-3 μm, preferably 0.5-2 μm.
As a preferable mode of the III-V nitride semiconductor epitaxial wafer of the invention, the semiconductor medium bump is made of SiO2SiON and SiN, and SiO is more preferable2。
As a preferable scheme of the III-V nitride semiconductor epitaxial wafer, the width of the bottom of the semiconductor medium bulge is 0.3-4 μm, and the distance between the semiconductor medium bulges is 0.1-2 μm.
As a preferable mode of the iii-v nitride semiconductor epitaxial wafer of the present invention, the semiconductor dielectric bump has a bottom surface and at least one side surface, the bottom surface being in contact with the epitaxial buffer layer; the side face is in contact with the epitaxial transition layer; the side surface and the bottom surface form an included angle smaller than or equal to 90 degrees.
The group iii-v nitride semiconductor epitaxial wafer of claim 1, wherein: the semiconductor medium bump is provided with a top surface parallel to the bottom surface, and the top surface is in contact with the epitaxial transition layer and forms an included angle larger than or equal to 90 degrees with the side surface.
As one preferable mode of the iii-v nitride semiconductor epitaxial wafer of the present invention, the semiconductor dielectric bump has a shape selected from the group consisting of a polygonal cube, a bag shape, a cone shape, and a pyramid shape. The bag-shaped protrusion with a smoother surface can effectively improve the growth quality of a subsequent light-emitting epitaxial structure (especially a GaN-based light-emitting epitaxial structure), and is therefore preferable.
In a preferred embodiment of the iii-v nitride semiconductor epitaxial wafer according to the present invention, the semiconductor dielectric protrusions are periodically arranged on the epitaxial buffer layer at intervals.
In a preferred embodiment of the iii-v nitride semiconductor epitaxial wafer of the present invention, the thickness of the epitaxial transition layer is greater than the height of the semiconductor medium bump, and the thickness of the epitaxial transition layer is 0.5 to 10 μm, preferably 1to 8.5 μm, and more preferably 1.5 to 4.5 μm.
As a preferable mode of the iii-v nitride semiconductor epitaxial wafer of the present invention, the epitaxial transition layer is composed of a material selected from the group consisting of: GaN, AlGaN, AlN, InGaN, InAlGaN, and their n-type or p-type dopants.
As a preferable mode of the group iii-v nitride semiconductor epitaxial wafer of the present invention, the epitaxial wafer includes an n-type GaN layer, an InGaN multi-quantum-hydrazine (MQW) light-emitting layer, and a p-type GaN layer.
As a preferred embodiment of the method for manufacturing a group iii-v nitride semiconductor epitaxial wafer according to the present invention, the substrate, the epitaxial buffer layer, the semiconductor dielectric bump, the epitaxial transition layer, and the epitaxial effective layer have the features as described in the above preferred embodiment for the semiconductor epitaxial wafer, and will not be repeated here. These broad, preferred and more preferred features may be combined with each other.
As a preferable embodiment of the method for manufacturing a group iii-v nitride semiconductor epitaxial wafer of the present invention, the step 2) of depositing an epitaxial buffer layer is performed by: formation of Al using metalorganic chemical vapor deposition (MOCVD) processxGa1-xN, 0 ≤ X ≤ 0.5, preferably 0 ≤ X ≤ 0.2, and is prepared at 450-700 deg.C, preferably 500-600 deg.C, or formed by Halide Vapor Phase Epitaxy (HVPE)xGa1-xN layers; the AlN is prepared by adopting an MOCVD method at the temperature of 700-1000 ℃, or is prepared by an HVPE method, a Physical Vapor Deposition (PVD) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or a sputtering method.
As a preferable mode of the method for manufacturing the iii-v nitride semiconductor epitaxial wafer of the present invention, the step 3) of patterning the semiconductor medium layer to form a plurality of semiconductor medium protrusions arranged at intervals comprises the following steps:
a) forming a photoresist layer on the surface of the semiconductor medium layer, and manufacturing the photoresist layer into a plurality of photoresist blocks which are arranged at intervals through an exposure process or a nano-imprinting process;
b) transferring the shape of the photoresist block to the semiconductor medium layer by adopting an inductively coupled plasma etching method to form a plurality of semiconductor medium bulges, and exposing the epitaxial buffer layer among the bulges;
c) and removing the photoresist blocks.
More preferably, a') reflowing the plurality of photoresist blocks into a plurality of bale-shaped photoresist blocks by a thermal reflow process is further included between the above steps a) and b).
As a preferable mode of the method for manufacturing the iii-v nitride semiconductor epitaxial wafer of the present invention, the method further comprises 3') annealing the substrate obtained in step 3) between steps 3) and 4) to nucleate the exposed portion of the epitaxial buffer layer. The annealing conditions depend on the epitaxial bufferThe material of the strike layer. For example, when the epitaxial buffer layer is AlxGa1-xN layer, when X is more than or equal to 0 and less than or equal to 0.5, the annealing temperature is 800-1400 ℃, and preferably 950-1250 ℃; when the epitaxial buffer layer is an AlN layer with the crystal orientation of (0001), the annealing temperature is 500-800 ℃.
As a preferable embodiment of the method for manufacturing a group iii-v nitride semiconductor epitaxial wafer of the present invention, the deposition of the epitaxial transition layer in step 4) is performed by an MOCVD method. More preferably, the MOCVD process is carried out directly at the above annealing temperature by passing the desired metalorganic. The epitaxial transition layer is deposited on the epitaxial buffer layer exposed between the semiconductor medium bulges firstly due to growth selectivity, and then gradually covers the bulges until the epitaxial transition layer completely covers the semiconductor medium bulges and completely fills the space between the semiconductor medium bulges, and the thickness of the epitaxial transition layer is preferably larger than the height of the bulges.
In a preferable embodiment of the method for manufacturing a group iii-v nitride semiconductor epitaxial wafer of the present invention, the deposition of each element of the epitaxial effective layer in step 5) may be performed by an MOCVD method. These methods are known to the person skilled in the art and are therefore not described in further detail.
As a preferable mode of the method for manufacturing a group iii-v nitride semiconductor epitaxial wafer of the present invention, the epitaxial wafer includes an n-type GaN layer, an InGaN multi-quantum-hydrazine (MQW) light-emitting layer, and a p-type GaN layer.
Examples
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1to 7. It should be noted that the drawings provided in the present embodiment are only schematic illustrations of the basic concept of the present invention, and only show the components related to the present invention, rather than limiting the number, shape, size, manufacturing method and process window of the components in actual implementation, the type, number and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated. The process conditions involved in the examples can be varied reasonably within the effective window and achieve the effects disclosed by the present invention.
Example 1
As shown in fig. 1to 10, the present embodiment provides a III-V nitride semiconductor LED device, the manufacturing method of which includes the steps of:
1. as shown in FIG. 1, in this embodiment, the growth substrate 101 is commercially available flat-sheet Al2O3And the surface crystal orientation (0001) of the substrate has flatness at an atomic level. In this embodiment, a substrate without cleaning is used, and is used without additional cleaning. Placing the substrate on a graphite tray with a SiC protective layer and feeding the substrate into an MOCVD (metal organic chemical vapor deposition) reaction chamber; heating the substrate to 1100 ℃ under a hydrogen atmosphere and holding at that temperature for 10 minutes; then the temperature of the substrate is reduced to 550 ℃, ammonia gas, trimethylaluminum (TMAl) and trimethylgallium (TMGa) are simultaneously introduced into the reaction chamber, wherein the standard flow rate of the ammonia gas is 56 liters/minute, and the molar flow rates of the TMAl and the TMGa are respectively 3.25 multiplied by 10-5And 2.47X 10-4Mol/min, the pressure in the reaction chamber was 500torr, and the time of passage was 215 seconds. As shown in fig. 2, Al is formed on the growth substrate 101 under the above-described conditionsxGa1-xThe N buffer layer has a thickness of 300 angstroms, where x is 0.2.
2. As shown in fig. 3, after the growth of the buffer layer 102 is completed, a PECVD (plasma enhanced chemical vapor deposition) process is used to form SiO on the surface of the buffer layer 1022 Layer 103, 1 μm thick. The temperature in the PECVD reaction chamber is 350 ℃, the pressure is 1torr (760 torr in one standard atmosphere), and SiH is added4And N2The flow rates of O are 10sccm (standard milliliters per minute) and 300sccm, respectively, the RF power of the plasma is 30W,
3. and forming a dielectric layer pattern. As shown in fig. 4 to 7, the patterns formed are arranged at periodic intervalsSiO2The protrusions are arranged in a hexagonal close packing manner with a period of 3 mu m and SiO2The width of the bottom of the bumps was 2 μm and the pitch was 1 μm.
Specifically, the step 3) includes the steps of:
as shown in FIGS. 4 to 5, step 3-a) is first performed on the SiO2The surface of the layer 103 is coated with a 1 μm photoresist layer 104, and the photoresist layer 104 is fabricated into photoresist cylinders 105 arranged in a hexagonal close-packed manner by an exposure process, wherein the period of hexagonal close-packing is 3 μm, the diameter of the photoresist cylinders is 2 μm, and the pitch is 1 μm.
As shown in fig. 6, step 3-b) is then performed to reflow the plurality of photoresist cylinders into a hemispherical shape through a thermal reflow process, wherein the reflow temperature is 130 degrees celsius and the reflow time is 120 seconds.
As shown in fig. 7, followed by step 3-c): transferring each hemispherical photoresist pattern to the SiO by inductively coupled plasma etching (ICP)2 Layer 103 of SiO2A bag-shaped protrusion exposing SiO2And the buffer layer 102 between the bag-shaped bulges is used for the subsequent epitaxial growth of the GaN epitaxial material. The technological conditions of the ICP etching are as follows: the etching gas is CHF3(trifluoromethane) at a standard flow rate of 50 ml/min; the upper electrode power of ICP was 1000W and the lower electrode power was 50W. And then carrying out the step 3-d) to remove the photoresist blocks. The cleaning process conditions are as follows: washing off the above SiO with acetone2Cleaning the residual photoresist on the surface with dilute hydrochloric acid to remove the SiO2And other pollutants on the surface of the bulge and the exposed surface of the buffer layer can be directly used for the epitaxial growth of the GaN.
4. And forming an epitaxial transition layer. And as shown in fig. 8, an epitaxial transition layer is epitaxially grown on the surface of the exposed buffer layer by using the MOCVD equipment, and the epitaxial transition layer completely covers the semiconductor medium bulges and completely fills the space between the semiconductor medium bulges.
Specifically, the substrate prepared in the above step is placed on a graphite tray with a SiC protective layer and sent into an MOCVD reaction chamber, and NH is added3Under the protection of (2), the temperature of the reaction chamber is directly adjustedHeating to 1100 deg.C, exposing to SiO in the substrate2The buffer layer between the protrusions becomes a single crystal nuclear island in the temperature rising process, and then a GaN non-doped layer transition layer with the thickness of 2 mu m, NH, is directly epitaxially grown at 1100 DEG C3The flow rate was 25 standard liters/min and the TMGa flow rate was 4X 10-5Mol/min, growth pressure 400 Torr.
5. And forming an epitaxial effective layer. As shown in fig. 9, after the growth of the epitaxial transition layer is completed, the n-type epitaxial layer, the light-emitting layer, and the p-type epitaxial layer are sequentially grown on the surface of the epitaxial transition layer directly using MOCVD without interrupting the growth.
The main growth conditions for each layer are as follows:
a. growing a Si-doped n-type GaN layer with a NH3 flow rate of 25 standard liters per minute and a TMGa flow rate of 4 x 10-3Mol/min, SiH doping4The flow rate is from 2 to 10-7The mol/min, the temperature of the reaction chamber is 1100 ℃, the pressure is 400Torr, and the thickness of the n-type GaN layer is 3 μm;
b. growing a Si-doped n-type AlGaN insertion layer at 1050 ℃, for 10min, under the pressure of 400Torr and with the thickness of 0.1 μm;
c. and (3) growing a multi-quantum well layer light-emitting layer: the multiple quantum well layer comprises 10 sequentially overlapped quantum well structures consisting of InxGa1-xN (x is 0.2) potential well layer and GaN barrier layer are overlapped and grown in sequence. Said InxGa1-xThe growth temperature of the N potential well layer is 780 ℃, the pressure is 300Torr, and the thickness is 2.5 nm; the growth temperature of the GaN barrier layer is 950 ℃, the pressure is 400Torr, and the thickness is 12 nm;
d. growing a Mg-doped p-type AlGaN layer at the growth temperature of 1000 ℃ and NH3The flow rate was 41 standard liters/min, and the TMGa flow rate was 1.1X 10-4Mol/min, TMAl flow rate 6.2X 10-5Mol/min, Cp2Mg (magnesium Dicyclopentate) flow 7.5X 10-7The mol/min, the pressure of the reaction chamber is 500Torr, and the growth thickness is 50 nm;
e. growing a Mg-doped p-type GaN layer: the temperature is reduced to 950 ℃, and the TMGa flow is 1 multiplied by 10-4Mole/clock, Cp2Mg streamThe amount is 4.5X 10-6The mol/min, the pressure of the reaction chamber is 500Torr, and the growth thickness is 600 nm;
f. growing Mg doped InGaN layer, cooling to 650 deg.C, NH3The flow rate was 40 standard liters/min, and the TEGa (triethylgallium) flow rate was 1.5X 10-5Mol/min, TMIn (trimethyl indium) flow 3X 10-5Mol/min, Cp2Mg flow 3.2X 10-6The mol/min, the pressure of the reaction chamber is 500Torr, and the growth thickness is 5 nm;
g. annealing treatment, finally reducing the temperature to 800 ℃, and N2The total flow rate was 80 standard liters/minute, the pressure in the reaction chamber was 200Torr, and the activation time was 10 minutes.
6. Finally, the n-type and p-type electrodes (wherein the p-type electrode includes an Indium Tin Oxide (ITO) transparent current spreading layer in addition to the p-type electrode metal layer) as shown in fig. 10 were formed in the epitaxial layer structure of the LED device formed in the above steps using a conventional semiconductor process, completing the fabrication of an LED chip having a size of 14mil × 28 mil.
Processing a conventional sapphire patterned substrate (PSS) for 10 minutes at a high temperature of 1200 ℃ in a hydrogen atmosphere by using the same MOCVD equipment, reducing the temperature to 500 ℃, and growing an AlGaN buffer layer of 30nm on the conventional PSS; then, under the same conditions as the step 4), epitaxially growing a GaN epitaxial transition layer with the same thickness; then, under the same conditions as the step 5), epitaxially growing the same light emitting diode epitaxial structure; and finally, manufacturing the LED chip with the same structure by using the semiconductor process conditions completely same as those in the step 6).
The two LED chips are packaged by adopting the same packaging process, and tests show that: compared with the conventional PSS substrate, the luminous efficiency of the LED chip prepared by the method is greatly improved. The luminous flux after 14mil x 28mil led chip packaging on conventional PSS substrate averaged 18.30 lm; the 14mil and 28mil LED chips prepared by the method have the average luminous flux of 19.23lm, and the luminous efficiency is improved by more than 5%. The ESD (electrostatic protection) aspect is also greatly improved, and under the condition that the leakage value is less than 0.5 microampere as the qualified leakage current, the passing rate of the ESD human body pattern 4000V of the 14mil and 28mil LED chip on the conventional PSS substrate is 80%, while the passing rate of the ESD human body pattern 4000V of the 14mil and 28mil LED chip prepared by the invention is average 94%.
Example 2
As shown in fig. 1to 10, this example provides a group iii-v nitride semiconductor LED device manufactured by the method of example 1, except for the step 2: the semiconductor dielectric layer 103 is a SiN layer prepared by a PECVD method, and the raw material for growing the SiN layer is NH3(Ammonia gas) and SiH4(silane) growth temperature 400 ℃ SiH4Flow rate 20sccm, NH3Is 17sccm, N2At 980sccm and a pressure of 0.8 torr.
The luminous flux of the 14mil by 28mil LED chip prepared in the embodiment after packaging is 19.1lm, and the average passing rate of the ESD human body mode 4000V is 95%.
Example 3
As shown in fig. 1to 10, this example provides a group iii-v nitride semiconductor LED device fabricated by the method of example 1, wherein the buffer layer 102 is an AlN layer with a thickness of 200 angstroms prepared by Physical Vapor Deposition (PVD), the target material is an Al target, and the sputtering gas is N2Substrate temperature 600 degrees centigrade, sputtering power 600W. The obtained AlN was columnar polycrystal with the main crystal orientation being (0001) arrangement.
The luminous flux of the 14mil by 28mil LED chip prepared in the embodiment after packaging is 20.2lm, and the average passing rate of the ESD human body mode 4000V is 97%.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A method for manufacturing a group iii-v nitride semiconductor epitaxial wafer, characterized in that the method comprises:
1) providing a substrate (101);
2) depositing an epitaxial buffer layer (102) on the substrate, the epitaxial buffer layer (102) being selected from AlxGa1-xN, 0 is more than or equal to X and less than or equal to 0.5, and the thickness of the epitaxial buffer layer (102) is 300 angstroms;
3) depositing a layer of semiconductor medium (103) on the epitaxial buffer layer (102), and patterning the semiconductor medium layer (103) to form a plurality of semiconductor medium bulges (107) arranged at intervals, wherein the epitaxial buffer layer (102) is exposed among the bulges (107), and the semiconductor medium bulges (103) are made of SiO (silicon dioxide)2SiON and SiN;
4) depositing an epitaxial transition layer (108) on the exposed part of the epitaxial buffer layer (102) until the thickness of the epitaxial transition layer (108) is higher than the height of the semiconductor medium bumps (107), wherein the epitaxial transition layer (108) covers the semiconductor medium bumps (107) and the exposed epitaxial buffer layer (102) between the semiconductor medium bumps, the epitaxial transition layer (108) is in contact with the exposed epitaxial buffer layer (102) and is in contact with the semiconductor medium bumps (107), and the epitaxial transition layer (108) completely covers the semiconductor medium bumps (107) and completely fills the space between the semiconductor medium bumps (107);
5) an epitaxial effective layer is grown on the upper surface of the epitaxial transition layer (108), the epitaxial effective layer comprises an n-type epitaxial layer (109), a light-emitting layer (110) and a p-type epitaxial layer (111) from bottom to top, and
the method is characterized in that the step of patterning the semiconductor medium layer (103) to form a plurality of semiconductor medium bulges (107) arranged at intervals comprises the following steps:
a) forming a photoresist layer on the surface of the semiconductor medium layer (103), and manufacturing the photoresist layer into a plurality of photoresist blocks which are arranged at intervals through an exposure process or a nanoimprint process;
b) transferring the shape of the photoresist block to the semiconductor medium layer (103) by adopting an inductively coupled plasma etching method to form a plurality of semiconductor medium bulges (107), and exposing the epitaxial buffer layer (102) among the bulges (107);
c) removing the photoresist block, and
characterized in that the method further comprises, between steps 3) and 4), 3') annealing the substrate obtained in step 3) to nucleate the exposed portion of the epitaxial buffer layer (102), when the epitaxial buffer layer (102) is AlxGa1-xN layer, when X is more than or equal to 0 and less than or equal to 0.5, the annealing temperature is 800-1400 ℃.
2. The method of claim 1, wherein: the substrate (101) is made of Al2O3SiC, Si, ZnO and GaN.
3. The method of claim 1, wherein: the height of the semiconductor medium bump (107) is 0.2-3 μm.
4. The method of claim 1, wherein: the thickness of the epitaxial transition layer (108) is 0.5-10 mu m, and the epitaxial transition layer is made of a material selected from the following materials: GaN, AlGaN, AlN, InGaN, InAlGaN, and their n-type or p-type dopants.
5. The method of claim 1, wherein: between steps a) and b) further comprising a') reflowing the plurality of photoresist blocks into a plurality of bale-shaped photoresist blocks by a thermal reflow process.
6. The method of claim 1, wherein: the epitaxial wafer comprises an n-type GaN layer, an InGaN multi-quantum hydrazine (MQW) light-emitting layer and a p-type GaN layer.
7. A method for manufacturing a group iii-v nitride semiconductor device, the method comprising preparing a group iii-v nitride semiconductor epitaxial wafer according to the method of any one of claims 1to 6, and preparing an n-electrode and a p-electrode on the epitaxial wafer in electrical communication with the n-type epitaxial layer and the p-type epitaxial layer, respectively.
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| CN113725331A (en) * | 2021-08-11 | 2021-11-30 | 广州市众拓光电科技有限公司 | Silicon-based LED epitaxial structure and growth method thereof |
| CN115498081A (en) * | 2022-09-30 | 2022-12-20 | 江西兆驰半导体有限公司 | Light emitting diode epitaxial structure, preparation method thereof and light emitting diode |
| CN113725331B (en) * | 2021-08-11 | 2024-04-26 | 广州市众拓光电科技有限公司 | Silicon-based LED epitaxial structure and growth method thereof |
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