JP2006156802A - Group iii nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor device having good performance and excellent reliability. <P>SOLUTION: A first group III nitride semiconductor layer and a second group III nitride semiconductor layer are laminated in this sequence on a substrate. The second semiconductor layer includes an active layer. The first semiconductor layer has a pattern in which a low dislocation density region and a high dislocation density region alternately exist in the planar direction. The second layer has a pattern structure similar to that of the first layer. The group III nitride semiconductor device has no second semiconductor layer on at least part of the high dislocation density region of the first semiconductor layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a group III nitride semiconductor device used for a light emitting device, a light receiving device, an electronic device, and the like. In particular, the present invention relates to a group III nitride semiconductor light-emitting device that has excellent light emission efficiency, a threshold voltage at which a current flows in the reverse direction, that is, a large reverse breakdown voltage and excellent reliability.

  The group III nitride semiconductor has a direct transition type band gap structure, and the gap energy corresponds to the visible light to ultraviolet light region. Utilizing this property, it is currently put into practical use in light emitting elements such as blue / blue-green LEDs, ultraviolet LEDs, and white LEDs combined with fluorescent materials.

  Group III nitride single crystals themselves are difficult to grow independently. The reason is that the dissociation pressure of the constituent nitrogen is high and nitrogen cannot be fixed by the pulling growth method or the like.

  For this reason, the metal organic vapor phase method (MOCVD method) is generally employed for the production of the group III nitride semiconductor. In this method, a single crystal substrate is set on a heatable jig in the reaction space, a source gas is supplied to the substrate surface, and a group III nitride semiconductor single crystal epitaxial film is grown on the substrate. is there. As the single crystal substrate at this time, sapphire, silicon carbide (SiC), or the like is used. However, even when a group III nitride semiconductor single crystal is directly grown on these single crystal substrates, there is a crystal lattice mismatch between the substrate crystal and the nitride single crystal. A large number of them are generated, and an epitaxial film with good crystallinity cannot be obtained. Therefore, in order to obtain a good epitaxial film, several methods for growing a buffer layer having a function of suppressing the occurrence of crystal dislocation between the substrate and the epitaxial film have been proposed.

  As a typical example, an organic metal raw material and a nitrogen source are simultaneously supplied onto a substrate at a temperature of 400 to 600 ° C. to deposit a layer called a low-temperature buffer layer, and then the temperature is increased to crystallize the low-temperature buffer layer. There is a method of performing a so-called heat treatment and then epitaxially growing a target group III nitride semiconductor single crystal (see Patent Document 1). Further, a first step of forming a group III nitride semiconductor by supplying a group III material with a ratio of group V material to group III material (V / III ratio) of 1000 or less on the substrate surface, and then a group III material and nitrogen A method comprising a second step in which a group III nitride semiconductor single crystal is vapor-grown using a raw material is also known (see Patent Document 2).

  With the advent of these methods, a group III nitride semiconductor single crystal having crystal dislocations suppressed to some extent that can be used as a semiconductor element material has been obtained. However, the electronic industry demands further improvement in performance of semiconductor elements.

  For example, for a semiconductor light emitting device, the emission wavelength, the forward voltage under the rated current, the light emission intensity, and the reliability as the device are important. One indicator of reliability is whether the current flows when the current is applied in the reverse direction rather than when the current is applied in the forward direction, that is, the threshold voltage at which the current flows in the reverse direction is high. This is important. The voltage at this threshold is called reverse breakdown voltage. In recent years, an element having a higher reverse breakdown voltage has been desired.

  On the other hand, a so-called selective growth technique has been proposed as a technique for reducing crystal dislocations. A method using a selective mask (ELO), a method using a concavo-convex substrate, and the surface of a nitride semiconductor layer are subjected to concavo-convex processing. Then, a method of further growing a nitride semiconductor layer is known. However, in selective growth, although the dislocation density decreases in most of the growth surface, there is a problem that crystal dislocations concentrate in the growth coalescence portion on the growth surface.

  In order to suppress the concentration of crystal dislocations on the surface of the growth coalescence part, a method of performing selective growth again by changing the position of selective growth has been reported (for example, Patent Documents 3 and 4). However, since the selective growth is performed a plurality of times, the growth time is extended, the yield is reduced, and the cost is increased. In addition, it has been proposed to provide a current barrier layer above a portion having a high dislocation density so as to concentrate the current in a portion having a low dislocation density (for example, Patent Document 5). However, even if a current barrier layer is provided above the high dislocation density region, current leakage from the low dislocation density region to the high dislocation density region because the low dislocation density region and the high dislocation density region are physically coupled. Inevitably, the effect of the current barrier layer must be limited.

JP-A-2-229476 JP 2003-243302 A JP 2002-33282 A JP 2001-111174 A JP 2002-33512 A

  An object of the present invention is to provide a group III nitride semiconductor device having good performance and excellent reliability. Another object of the present invention is to provide a group III nitride semiconductor device having a large threshold voltage at which a current flows in the reverse direction, that is, a reverse breakdown voltage, and excellent in reliability.

The present invention provides the following inventions.
(1) A first group III nitride semiconductor layer and a second group III nitride semiconductor layer are stacked in this order on a substrate, and the second semiconductor layer includes an active layer, One semiconductor layer has a pattern in which low dislocation density regions and high dislocation density regions exist alternately in a plane direction, and the second semiconductor layer has a pattern structure similar to that of the first semiconductor layer. And the Group III nitride semiconductor device, wherein the second semiconductor layer does not exist in at least a part of the high dislocation density region of the first semiconductor layer.

(2) The group III nitride semiconductor device according to the above item 1, wherein the pattern of the low dislocation density region and the high dislocation density region is a periodic pattern.

(3) The group III nitride semiconductor device according to the above item 1 or 2, wherein the low dislocation density region and the high dislocation density region exist in a stripe shape.

(4) The group III nitride semiconductor device according to the above item 1 or 2, wherein the low dislocation density region or the high dislocation density region exists in an island shape.

(5) The group III nitride semiconductor device according to the above item 1 or 2, wherein the low dislocation density region or the high dislocation density region exists in a lattice form.

(6) The group III nitride semiconductor device according to any one of the above items 1 to 5, further including a selection mask below (on the substrate side) the first group III nitride semiconductor layer.

(7) The group III nitride semiconductor device according to any one of the above items 1 to 5, further comprising a group III nitride semiconductor layer for selective growth below the first group III nitride semiconductor layer.

(8) The group III nitride semiconductor device according to any one of the above items 1 to 5, wherein the substrate has periodic recesses in a planar direction.

(9) The group III nitride semiconductor device according to any one of the above items 1 to 8, wherein the group III nitride semiconductor device is a light emitting device.

(10) In the above item 9, wherein the first group III nitride semiconductor layer forms at least a part of the n-type layer, and the second group III nitride semiconductor layer forms at least a light emitting layer and a p-type layer. The group III nitride semiconductor device described.

(11) The group III according to the above item 9 or 10, wherein the second group III nitride semiconductor layer is present on the high dislocation density region of the first group III nitride semiconductor layer in the periphery of the light emitting device. Nitride semiconductor device.

(12) The high dislocation density region of the first group III nitride semiconductor layer in which the second group III nitride semiconductor layer is present is 20% or less of the entire high dislocation density region, Group III nitride semiconductor device according to Item.

(13) An n-type layer, a light-emitting layer, and a p-type layer made of a group III nitride semiconductor layer having a pattern in which low dislocation density regions and high dislocation density regions are alternately present in the plane direction are stacked in this order on a substrate. A first step of forming, a second step of forming a negative electrode and a positive electrode in the n-type layer and the p-type layer, respectively, and a third step of removing at least a part of the high dislocation density regions of at least the light-emitting layer and the p-type layer A method for producing a group III nitride semiconductor light-emitting device comprising:

(14) The method for producing a group III nitride semiconductor light-emitting device according to the above item 13, wherein the first step, the second step, and the third step are performed in this order.

(15) A group III nitride semiconductor light-emitting device manufactured by the manufacturing method according to item 13 or 14 above.

(16) A lamp comprising the group III nitride semiconductor light-emitting device according to any one of items 9 to 12 and 15.

(17) Electronic equipment using the group III nitride semiconductor device according to any one of 1 to 12 and 15 above.
(18) A mechanical device in which the electronic device according to item 17 is incorporated.

  In the group III nitride semiconductor device of the present invention, since the dislocation density of the nitride semiconductor constituting the active layer is low, the characteristics and reliability are improved. In particular, when the group III nitride semiconductor device is a light emitting device, it has excellent luminous efficiency and a large reverse breakdown voltage.

In the present invention, the substrate includes a sapphire single crystal (Al ₂ O ₃ ; A plane, C plane, M plane, R plane), spinel single crystal (MgAl ₂ O ₄ ), ZnO single crystal, LiAlO ₂ single crystal, LiGaO. Known substrate materials such as ₂ single crystal, oxide single crystal such as MgO single crystal, Si single crystal, SiC single crystal, GaAs single crystal, and boride single crystal such as ZrB ₂ can be used without any limitation. A sapphire substrate and a SiC substrate are preferable. The plane orientation of the substrate is not particularly limited, but when a sapphire substrate is used, it is preferably the C plane ((0001) plane). Further, it is preferable that the vertical axis direction of the substrate surface is inclined in a specific direction from the <0001> direction of the sapphire substrate.

  A group III nitride semiconductor is usually laminated on the substrate via a buffer layer as disclosed in Patent Documents 1 and 2 described above. Depending on the substrate used and the growth conditions of the epitaxial layer, the buffer layer may be unnecessary.

Examples of the group III nitride semiconductor include, for example, the general formula Al _X Ga _Y In _Z N _1-A M _A (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, and X + Y + Z = 1. Symbol M Represents a group V element different from nitrogen (N), and 0 ≦ A <1). Many Group III nitride semiconductors represented by this group are known. Including nitride semiconductors, the general formula Al _X Ga _Y In _Z N _1-A M _A (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, and X + Y + Z = 1. Symbol M is nitrogen ( N) represents a Group V element different from 0), and a Group III nitride semiconductor represented by 0 ≦ A <1 can be used without any limitation.

  The group III nitride semiconductor can contain other group III elements in addition to Al, Ga, and In, and elements such as Ge, Si, Mg, Ca, Zn, Be, P, As, and B as required Can also be contained. Furthermore, it is not limited to elements that are intentionally added, but may include impurities that are inevitably included depending on film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

The growth method of the group III nitride semiconductor is not particularly limited, and the group III nitride semiconductor such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy) is grown. All methods known to be applied are applicable. A preferred growth method is the MOCVD method from the viewpoint of film thickness controllability and mass productivity. In the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) is used as a carrier gas, trimethyl gallium (TMGa) or triethyl gallium (TEGa) is used as a Ga source as a group III source, and trimethyl aluminum (TMAl) or triethyl aluminum is used as an Al source. (TEAl), trimethylindium (TMIn) or triethylindium (TEIn) as the In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as the N source which is a group V source. In addition, as a dopant, for n-type, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a Si raw material, germanium gas (GeH ₄ ) or tetramethyl germanium ((CH ₃ ) ₄ Ge) is used as a Ge raw material. And an organic germanium compound such as tetraethylgermanium ((C ₂ H ₅ ) ₄ Ge) can be used. In the MBE method, elemental germanium can also be used as a doping source. For the p-type, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) or bisethylcyclopentadienyl magnesium (EtCp ₂ Mg) is used as the Mg raw material.

  In the group III nitride semiconductor device of the present invention, a first group III nitride semiconductor layer and a second group III nitride semiconductor layer are stacked in this order on a substrate. In the first group III nitride semiconductor layer, low dislocation density regions with few crystal dislocations and high dislocation density regions with many crystal dislocations are alternately present in the plane direction. The second group III nitride semiconductor layer has the same structure as the first semiconductor layer, but at least a part of the high dislocation density region is removed. That is, the second semiconductor layer does not exist in at least part of the high dislocation density region of the first semiconductor layer. Therefore, the second semiconductor layer is composed of only the low dislocation density region or most of the low dislocation density region. The active layer in the semiconductor element of the present invention is included in this second semiconductor layer.

  In the present invention, the active layer refers to a layer that exhibits an element function, for example, a light emitting layer for a light emitting element, a light receiving layer for a light receiving element, and an electron transit layer for an electronic device.

In the present invention, a high dislocation density region means a region where crystal dislocations exist at a density of 1 to 100 × 10 ⁸ cm ⁻² . The low dislocation density region refers to a region having a crystal dislocation density that is 1/2 to 1/100 of the crystal dislocation density lower than that of the high dislocation density region.

  The density of crystal dislocations in the group III nitride semiconductor layer was determined by depositing a tungsten mask with a width of 1 μm on the surface of the chip, processing it with a focused ion beam (FIB), and then thinning the surface to 2000 mm width with an argon beam. The cross section of is observed and measured by TEM. The crystal dislocation part is observed as a linear contrast.

  The pattern in which the low dislocation density region and the high dislocation density region alternately appear in the plane direction may be any pattern, but a periodic pattern is preferable because it is easy to manufacture industrially. For example, a stripe shape having a repetition cycle in one-dimensional direction as shown in FIG. 1 or a lattice shape having a repetition cycle in two-dimensional direction as shown in FIG. In these figures, the shaded area is the low dislocation density region. Further, in FIG. 2, an island-like pattern in which the low dislocation density region and the high dislocation density region are reversed and the low dislocation density region exists in isolation may be used.

  The ratio of the geometric dimensions of the high dislocation density region and the low dislocation density region is preferably in the range of 1: 1 to 1:10 because the degree of freedom of the film forming conditions of the group III nitride semiconductor layer is increased. Further, the repeating pitch is preferably 0.1 to 10 times, more preferably 0.5 to 5 times the growth thickness of the group III nitride semiconductor layer per hour. By setting the pitch within this range, a good crystal group III nitride semiconductor layer with less distortion can be obtained.

  In the case of a stripe shape having a one-dimensional repetition period, the area ratio of the low dislocation density region and the high dislocation density region is the same as the area ratio, but the lattice ratio or island shape has a two-dimensional repetition period. In this case, the area ratio between the low dislocation density region and the high dislocation density region is the square of the dimensional ratio. Therefore, in order to enlarge the low dislocation density region, a lattice shape or an island shape having a two-dimensional repetitive period is preferable.

The semiconductor layer in which the low dislocation density region and the high dislocation density region described above alternately appear in the planar direction can be formed by a so-called selective growth technique. As the selective growth technique, for example, a method using a selective mask as disclosed in Japanese Patent Laid-Open No. 11-126948 is preferable. In this method, a base group III nitride semiconductor layer is stacked on a substrate, a selective mask having an opening having the desired pattern described above is formed thereon, and then a group III nitride semiconductor layer is further stacked. It is something to be made. In the semiconductor layer stacked on the selection mask, a high dislocation density region is formed on the opening portion of the selection mask and a low dislocation density region is formed on the non-opening portion. As the selective mask, for example, a film made of SiO ₂ , SiN, tungsten or the like and having a thickness of 10 to 10,000 mm is preferable.

  As a selective growth technique, for example, a group III nitride semiconductor layer for selective growth is formed on a substrate as disclosed in JP-A-11-263967, and a group III nitride semiconductor layer is further formed thereon. A method of growing the is also preferably used. In this method, a base group III nitride semiconductor layer is laminated on a substrate in advance, and the surface is etched into the desired pattern described above, and then a group III nitride semiconductor layer is further laminated thereon. is there. In the present invention, a group III nitride semiconductor layer whose surface is etched and has irregularities is referred to as a group III nitride semiconductor layer for selective growth. The group III nitride semiconductor layer laminated on the group III nitride semiconductor layer for selective growth has a low dislocation density region on the etching surface.

  Further, for example, as disclosed in Japanese Patent Application Laid-Open No. 11-274568, a method of growing the group III nitride semiconductor layer by providing the above-mentioned desired pattern-like recesses on the substrate surface can be preferably used. In this method, the portion laminated on the concave portion becomes a low dislocation density region.

  What is necessary is just to select suitably the composition and layer structure of the group III nitride semiconductor layer to laminate | stack according to the target semiconductor element.

  Thus, at least a part of the high dislocation density region of the group III nitride semiconductor layer in which the low dislocation density region and the high dislocation density region formed on the substrate alternately appear in the plane direction is removed from the surface to at least the active layer. The The layer from which the high dislocation density region is removed is the second group III nitride semiconductor layer in the present invention, and the layer in which the high dislocation density region is left is the first group III nitride semiconductor layer in the present invention.

  In the second group III nitride semiconductor layer, the remaining high dislocation density region is preferably 20% or less of the entire high dislocation density region. More preferably, it is 10% or less. If a large amount remains, improvement of characteristics and reliability of the semiconductor element will be insufficient.

  The method for removing the group III nitride semiconductor layer is not particularly limited. For example, the group III nitride semiconductor layer may be removed by applying a well-known etching method such as dry etching or wet etching after forming a protective mask on the portion where the semiconductor layer remains. it can. It can also be removed by irradiation with a laser or ion beam. In this case, it is not necessary to form a protective mask.

  The group III nitride semiconductor device having the structure of the present invention can be used as various semiconductor devices. For example, in addition to semiconductor light emitting devices such as light emitting diodes and laser diodes, it can be used as group III nitride semiconductor devices such as various high-speed transistors and light receiving devices. Among these various semiconductor elements, the group III nitride semiconductor light-emitting element having a structure in which an n-type layer and a p-type layer are provided on both sides of the light-emitting layer which is an active layer, depends on the degree of crystal dislocations in the light-emitting layer. Since the reverse withstand voltage that affects the voltage changes greatly, the structure of the present invention is a particularly preferable semiconductor element. Hereinafter, the present invention will be described in more detail by taking a semiconductor light emitting device as an example.

  In the group III nitride semiconductor light emitting device, for example, an n type layer, a light emitting layer, and a p type layer made of a group III nitride semiconductor are stacked in this order on a substrate made of sapphire, and a part of the p type layer and the light emitting layer are formed. A negative electrode is provided in contact with the removed n-type layer, and a positive electrode is provided in contact with the remaining p-type layer. FIG. 3 is a plan view schematically showing an example of a group III nitride semiconductor light-emitting device of the present invention produced in Example 1 described later, and FIG. 4 shows a cut section at XX ′. It is a schematic diagram. In these figures, 1 is a substrate, 5 is an n-type layer, 6 is a light-emitting layer, and 7 is a p-type layer. Reference numeral 8 denotes a negative electrode, which is provided in contact with the n-type layer exposed by removing up to half of the thickness of the p-type layer, the light emitting layer, and the n-type layer. Reference numeral 9 denotes a positive electrode, which is provided in a hatched portion in FIG. Reference numeral 10 denotes a positive electrode bonding pad, which is provided on and in contact with the positive electrode 9.

  In this example, the semiconductor layers in which the low dislocation density regions and the high dislocation density regions appear alternately in the plane direction are formed in stripes by the selective growth technique using the above-described selection mask. After forming the underlying group III nitride semiconductor layer 3 on the substrate 1 via the buffer layer 2, the selection mask 4 is formed thereon. A group III nitride semiconductor is again grown thereon to form the n-type layer 5, the light emitting layer 6, and the p-type layer 7. A high dislocation density region a is formed on the opening 4a of the selection mask, and a low dislocation density region b is formed on the non-opening 4b.

  The high dislocation density region b is removed from the upper surface of the p-type layer to the negative electrode forming surface of the n-type layer to form a recess c. However, the high dislocation density regions of the part d along the side where the negative electrode is provided and the part e along the side where the positive electrode bonding pad is provided are left without being removed. Further, a high dislocation density region of the positive electrode bonding pad portion is also left.

  Therefore, the group III nitride semiconductor layer A from the upper surface of the p-type layer to the negative electrode forming surface of the n-type layer is the second group III nitride semiconductor layer in the present invention, from the lower surface of the n-type layer to the negative electrode forming surface. The group III nitride semiconductor layer B is the first group III nitride semiconductor layer in the present invention.

  The step of removing the high dislocation density region and forming the recess c may be performed simultaneously with the step of exposing the negative electrode forming surface, but the formation of the positive electrode on the upper surface of the remaining p-type layer becomes complicated, so the negative electrode forming surface It is preferable to remove the high dislocation density region together with the positive electrode formed on the negative electrode and the positive electrode after the exposure step.

  In the group III nitride semiconductor light emitting device described above, the current supplied from the positive electrode bonding pad 10 spreads over the entire surface of the light emitting device by the positive electrode 9 and passes through the p-type layer 7, the light emitting layer 6 and the n-type layer 5. It flows to the negative electrode 8. Since most of the light emitting layer 6 is composed of a low dislocation density region, the light emitting layer 6 has high light emission efficiency and high reverse breakdown voltage.

  In the above example, the stripe shape is used as the pattern of the low dislocation density region and the high dislocation density region, but it may be a lattice shape or an island shape. In the case of stripes and islands, it is important that the entire positive electrode formed on the p-type layer is electrically connected, leaving a part of the high dislocation density region so as to connect the isolated low dislocation density regions. is there. In particular, it is preferable that the light emitting elements are connected at the four circumferences.

  The stripe shape is preferable because the degree of freedom of the film forming conditions of the group III nitride semiconductor layer is increased. In addition, the lattice shape reduces the degree of freedom of film formation conditions, but has excellent current distribution in the surface direction of the light emitting element, lowers the operating voltage, and increases the light emission intensity.

  The n-type layer, light-emitting layer, and p-type layer constituting the group III nitride semiconductor light-emitting device are well known in various compositions and structures. In the present invention, those having any composition and structure including those well known can be used. Also, negative electrodes and positive electrodes having various compositions and structures are well known. In the present invention, those having any composition and structure including those well known can be used.

  Since the group III nitride semiconductor device of the present invention has excellent characteristics and reliability, for example, a highly reliable device such as a high-intensity LED lamp can be manufactured from a light-emitting device using this technology. Therefore, the reliability of electronic devices such as mobile phones, displays and panels incorporating elements using this technology, and mechanical devices such as automobiles, computers and game machines incorporating such electronic devices is also improved. To do.

  EXAMPLES The present invention will be described in detail below with reference to examples, but the present invention is not limited only to these examples.

Example 1
In this example, a group III nitride semiconductor light emitting device was fabricated using a lateral growth method using a selection mask as a selective growth technique for reducing crystal dislocations. A striped mask was used as the selection mask.

  FIG. 3 is a plan view schematically showing the group III nitride semiconductor light emitting device manufactured in this example, and FIG. 4 is a schematic view showing a cross section taken along the line X-X ′. In these drawings, 1 is a substrate, 2 is a buffer layer, and 3 is an underlying group III nitride semiconductor layer. 4 is a selection mask, 4a is an opening, and 4b is a non-opening. 5 is an n-type layer, 6 is a light emitting layer, and 7 is a p-type layer. A negative electrode 8 is provided in contact with the n-type layer exposed by removing up to half of the thickness of the p-type layer, the light-emitting layer, and the n-type layer. Reference numeral 9 denotes a positive electrode, which is provided in contact with the p-type layer indicated by the hatched portion in FIG. Reference numeral 10 denotes a positive electrode bonding pad, which is provided on and in contact with the positive electrode 9. A is a second group III nitride semiconductor layer, and is composed of the p-type layer 7, the light emitting layer 6, and a part of the n-type layer 5. B is a first group III nitride semiconductor layer, and consists of the remaining portion of the n-type layer 5. a is a high dislocation density region and is located on the opening 4 a of the selection mask 4. b is a low dislocation density region and is located on the non-opening portion 4 b of the selection mask 4.

  The buffer layer 2 and the underlying group III nitride semiconductor layer 3 were laminated in the form of a substrate according to the method described in Example 1 of Patent Document 2 that disclosed the buffer layer forming technique. That is, sapphire was used as the substrate 1, introduced into a growth furnace after organic cleaning, and the oxide film on the surface was removed while being heated to 1170 ° C. in hydrogen.

Next, the substrate temperature is lowered to 1150 ° C., TMGa, TMAl, and NH ₃ are supplied to the growth furnace, the buffer layer 2 is laminated, and the underlying group III nitride semiconductor made of undoped GaN having the same temperature of 2 μm is then formed. Layer 3 was laminated. When the dislocation density of the undoped GaN layer 3 grown on the sapphire substrate was separately measured by the above-mentioned cross-sectional TEM evaluation, it had a dislocation density of about 8 × 10 ⁸ cm ⁻² .

The sapphire substrate 1 was taken out of the growth furnace, and a selective mask 4 made of SiO _{2 having a} thickness of 1000 mm was formed on the underlying group III nitride semiconductor layer 3 by sputtering. By a photolithography method, a striped pattern composed of repetition of an opening 4a of 2 μm and a non-opening 4b of 2 μm was formed.

The substrate 1 on which the selection mask was formed was returned to the growth furnace again, heated to 1170 ° C., TMGa as a group III material, NH ₃ as a group V material, and SiH ₄ as a dopant. The flow rates are 30 sccm, 3.5 slm, and 20 sccm, respectively. An n-type layer 5 made of a Si-doped GaN layer having a thickness of 2.2 μm was laminated. When the dislocation density of the stacked n-type layer 5 was measured separately, the dislocation density in the GaN layer on the mask opening was 8 × 10 ⁸ cm ⁻² , whereas the dislocation density was on the non-opening. in a 6 × 10 ⁷ cm ^-2, the dislocation density on the non-opening was reduced to 1/10.

Subsequently, the temperature of the growth furnace was lowered to 800 ° C., and a light emitting layer 6 having a multiple quantum well structure having a barrier layer made of GaN and a well layer made of InGaN was laminated using TMGa and TMIn as group III materials. The multi-quantum well structure is a five-layer structure in which both ends are barrier layers. Next, the temperature of the growth furnace is raised again to 1100 ° C., TMGa is used as a Group III material, Cp ₂ Mg is used as a Mg dopant material, a Cp ₂ Mg flow rate is 240 sccm, and a p-type layer 7 made of Mg-doped GaN is formed. Formed.

  The obtained group III nitride semiconductor multilayer structure is taken out of the growth furnace, a protective mask is formed with a resist leaving a position for forming a negative electrode on the p-type layer 7, and n-type is formed by dry etching using a chlorine-based gas. Layer 5 was exposed. By conventional means well known in the art, a negative electrode 8 made of Ti / Al is formed on the exposed n-type layer 5, a transparent positive electrode (TE) 9 made of Au / Ni is formed on the remaining p-type layer 7, and a positive electrode A positive electrode bonding pad 10 was formed on 9.

  A protective mask was formed with a resist on the laminated structure on which the electrodes were formed. This resist serves as a protective mask during etching for selective removal of a region having a high dislocation density. That is, a resist was applied to the entire surface of the laminated structure, and only the resist on the portion c in FIG. 3 corresponding to a part of the high dislocation density region was removed. Next, etching was performed by dry etching using a chlorine-based gas until it reached half the thickness of the n-type layer 5 to obtain a group III nitride semiconductor light emitting device of the present invention.

When the characteristics of the obtained group III nitride semiconductor light emitting device were evaluated, the reverse withstand voltage Vr was 20 V or more with respect to 10 μA, and the light emission output was 5 mW at 20 mA.
For comparison, the light emitting element in which the portion c in FIG. 3 was not removed was evaluated in the same manner. As a result, Vr was 12 V and the light emission output was 4 mW.

(Example 2)
In this example, a group III nitride semiconductor light-emitting device having a low dislocation density region having a lattice pattern was manufactured using the group III nitride semiconductor layer for selective growth described above as a selective growth technique for reducing crystal dislocations.

  The process up to the formation of the foundation layer group III nitride semiconductor layer 3 having a thickness of 2 μm is the same as that of the first embodiment. In this example, a resist film having a diameter of 2 μm was formed at a pitch of 4 μm vertically and horizontally on the entire surface of the underlying group III nitride semiconductor layer 3 by photolithography. Next, dry etching was performed using a chlorine-based gas, so that the base group III nitride semiconductor layer 3 was formed into a shape in which island-shaped protrusions having a diameter of 2 μm and a height of 1.8 μm were present at a pitch of 4 μm in length and width. The underlying group III nitride semiconductor layer 3 processed in this way becomes the group III nitride semiconductor layer for selective growth in this example.

After the group III nitride semiconductor layer for selective growth was formed, it was returned to the growth furnace again, and an n-type layer, a light emitting layer and a p-type layer were formed in the same manner as in Example 1. However, the thickness of the n-type layer was set to 4 μm so that the unevenness did not appear on the upper surface of the n-type layer. When the dislocation density was separately measured after the formation of the n-type layer, it was 6 × 10 ⁸ cm ⁻² above the island-shaped protrusions, whereas the other portion was 6 × 10 ⁷ cm ⁻² .

  A light emitting device was produced in the same manner as in Example 1 from the obtained group III nitride semiconductor multilayer structure. However, when removing the c portion corresponding to the high dislocation density region, the shape of the c portion is a square having a side of 2 μm arranged vertically and horizontally at a pitch of 4 μm in accordance with the protrusions of the group III nitride semiconductor layer for selective growth. The pattern was such that a low dislocation density region of a grid-like street having a width of 2 μm was left.

  When the obtained group III nitride semiconductor light-emitting device was evaluated in the same manner as in Example 1, the reverse withstand voltage Vr was 20 V or more with respect to 10 μA, and the light emission output was 5.2 mW at 20 mA.

(Example 3)
In this example, as a selective growth technique for reducing crystal dislocations, a group III nitride semiconductor light-emitting device having a low dislocation density region having a stripe pattern similar to that of Example 1 using a substrate having periodic recesses in the plane direction Was made.

  A 2 μm wide resist film was formed at a 4 μm pitch over the entire surface of the sapphire substrate. Next, the sapphire substrate was etched with a chlorine-based gas, and recesses having a depth of 2 μm and a width of 2 μm were provided at a pitch of 4 μm. The formed resist film was removed by organic cleaning.

A group III nitride semiconductor light-emitting device was produced in the same manner as in Example 1 using the sapphire substrate obtained by the above treatment. However, the thickness of the group III nitride semiconductor layer 3 of the underlayer was set to 4 μm so that a difference in height based on the unevenness of the substrate did not appear on the surface. Further, the selection mask 4 was not provided. When the dislocation density of the III-nitride semiconductor layer 3 as the underlayer was separately measured in the same manner as in Example 1, it was 8 × 10 ⁸ on the convex portion of the substrate as in the case of growing on a substrate that was not subjected to irregular processing. Although it was cm ⁻² , it was 2 × 10 ⁸ cm ⁻² on the concave portion, and a reduction in dislocation density of 1/3 to 1/4 was observed.

  When the obtained group III nitride semiconductor light-emitting device was evaluated in the same manner as in Example 1, the reverse withstand voltage Vr was 20 V or more with respect to 10 μA, and the light emission output was 5.2 mW at 20 mA.

  The group III nitride semiconductor device of the present invention can realize a highly reliable device when used for light emitting devices such as light emitting diodes and laser diodes, light receiving devices and various electronic devices. The utility value is very large.

It is a figure which shows an example of the pattern of a low dislocation density area | region and a high dislocation density area | region. It is a figure which shows another example of the pattern of a low dislocation density area | region and a high dislocation density area | region. 3 is a plan view schematically showing a group III nitride semiconductor light-emitting device manufactured in Example 1. FIG. It is the schematic diagram which showed the cut | disconnection cross section in X-X 'of FIG.

Explanation of symbols

1 substrate 2 buffer layer 5 n-type layer 6 light-emitting layer 7 p-type layer 8 negative electrode 9 positive electrode 10 positive electrode bonding pad

Claims (18)

  A first group III nitride semiconductor layer and a second group III nitride semiconductor layer are stacked in this order on a substrate, and the second semiconductor layer includes an active layer, and the first semiconductor The layer has a pattern in which low dislocation density regions and high dislocation density regions are alternately present in a plane direction, the second semiconductor layer has a pattern structure similar to that of the first semiconductor layer, and A group III nitride semiconductor device, wherein the second semiconductor layer does not exist in at least a part of the high dislocation density region of the first semiconductor layer.   The group III nitride semiconductor device according to claim 1, wherein the pattern of the low dislocation density region and the high dislocation density region is a periodic pattern.   The group III nitride semiconductor device according to claim 1, wherein the low dislocation density region and the high dislocation density region exist in a stripe shape.   The group III nitride semiconductor device according to claim 1 or 2, wherein the low dislocation density region or the high dislocation density region exists in an island shape.   The group III nitride semiconductor device according to claim 1 or 2, wherein the low dislocation density region or the high dislocation density region exists in a lattice form.   The group III nitride semiconductor device according to any one of claims 1 to 5, further comprising a selection mask below the first group III nitride semiconductor layer (substrate side).   The group III nitride semiconductor device according to any one of claims 1 to 5, further comprising a group III nitride semiconductor layer for selective growth below the first group III nitride semiconductor layer.   The group III nitride semiconductor device according to claim 1, wherein the substrate has periodic recesses in a planar direction.   The group III nitride semiconductor device according to any one of claims 1 to 8, wherein the group III nitride semiconductor device is a light emitting device.   The III-nitride semiconductor layer according to claim 9, wherein the first group III nitride semiconductor layer forms at least a part of the n-type layer, and the second group III nitride semiconductor layer forms at least a light emitting layer and a p-type layer. Group nitride semiconductor device.   The group III nitride semiconductor according to claim 9 or 10, wherein the second group III nitride semiconductor layer is present on the high dislocation density region of the first group III nitride semiconductor layer in the peripheral portion of the light emitting device. element.   12. The high dislocation density region of the first group III nitride semiconductor layer in which the second group III nitride semiconductor layer is present is 20% or less of the entire high dislocation density region. Group III nitride semiconductor device.   A first layer in which an n-type layer, a light-emitting layer, and a p-type layer, which are made of a group III nitride semiconductor layer having a pattern in which low dislocation density regions and high dislocation density regions exist alternately in a plane direction, are laminated in this order on a substrate. The second step of forming the negative electrode and the positive electrode on the n-type layer and the p-type layer, respectively, and the third step of removing at least a part of the high dislocation density region of the light-emitting layer and the p-type layer. A method for producing a Group III nitride semiconductor light-emitting device.   The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 13, wherein the first step, the second step, and the third step are performed in this order.   A group III nitride semiconductor light-emitting device manufactured by the manufacturing method according to claim 13 or 14.   The lamp | ramp which uses the group III nitride semiconductor light-emitting device as described in any one of Claims 9-12 and 15.   An electronic device using the group III nitride semiconductor device according to any one of claims 1 to 12 and 15.   A mechanical device in which the electronic device according to claim 17 is incorporated.

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