CN103681564A - 电子装置和制造电子装置的方法 - Google Patents

电子装置和制造电子装置的方法 Download PDF

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CN103681564A
CN103681564A CN201310347355.3A CN201310347355A CN103681564A CN 103681564 A CN103681564 A CN 103681564A CN 201310347355 A CN201310347355 A CN 201310347355A CN 103681564 A CN103681564 A CN 103681564A
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solder paste
paste layer
particle
metal ingredient
semiconductor
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CN103681564B (zh
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哈利勒·哈希尼
戈特弗里德·比尔
约阿希姆·马勒
伊万·尼基廷
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及电子装置和制造电子装置的方法，一种半导体装置包括导电载体和设置在所述载体上的半导体芯片。所述半导体装置还包括设置在所述载体和所述半导体芯片之间的多孔扩散焊料层。

Description

电子装置和制造电子装置的方法
技术领域
本发明涉及将半导体芯片接合（bond）在载体上的技术，更具体地，涉及扩散焊接的技术。
背景技术
半导体装置制造商不断努力以改进他们的产品的性能，同时降低他们的制造成本。在半导体装置的制造中的成本密集的区域是对半导体芯片进行封装。如本领域的技术人员已知的，在晶圆上制作集成电路，随后这些晶圆被单个化（singulate）以生产半导体芯片。随后，可以在导电载体上安装半导体芯片。希望在导电载体上安装的半导体芯片从而以高产量和低成本提供低应力、机械稳定以及高导热性和高导电性的接合。
发明内容
本文提供了一种半导体装置，该半导体装置包括：导电载体；半导体芯片，设置在载体上；以及多孔扩散焊料层，设置在载体和半导体芯片之间。
优选地，多孔扩散焊料层包括具有金属间相的颗粒。
优选地，颗粒包括从由银、铜、金和铟构成的组中选择的第一金属成分，以及从由锡和锌构成的组中选择的第二金属成分。
优选地，多孔扩散焊料层包括第一金属成分的重量百分比是50%至75%并且第二金属成分的重量百分比是25%至50%的化学组合物。
优选地，多孔扩散焊料层的颗粒被烧结或相互扩散。
优选地，半导体装置进一步包括设置在载体和多孔扩散焊料层之间的第一中间层，其中，第一中间层包括锡或锌。
优选地，第一中间层包括由防锈层形成的表面。
优选地，多孔扩散焊料层包括在从1μm到50μm的范围内的厚度。
优选地，载体是引线框。
优选地，半导体装置进一步包括设置在多孔扩散焊料层和半导体芯片之间的第二中间层，其中，第二中间层包括烧结的或相互扩散的金属层。
本文还提供了一种半导体布置，该半导体布置包括：半导体本体；以及焊料膏层，设置在半导体本体的至少一个主表面的上方，焊料膏层包括从由银、铜、金和铟构成的组中选择的第一金属成分的第一颗粒；从由锡和锌构成的组中选择的第二金属成分的第二颗粒；以及埋设有第一颗粒和第二颗粒的聚合物材料。
优选地，聚合物材料包括B阶段聚合物材料。
优选地，B阶段聚合物材料被预固化。
优选地，聚合物材料是溶剂或液体。
优选地，溶剂或液体在预固化期间可蒸发。
优选地，焊料膏层的总金属贡献包括第一金属成分的重量百分比是50%至75%并且第二金属成分的重量百分比是25%至50%的化学组合物。
本文还提供了一种在导电载体上接合半导体芯片的方法，该方法包括：在导电载体上形成焊料膏层，焊料膏层包括第一金属成分的第一颗粒和第二金属成分的第二颗粒；将半导体芯片放置在焊料膏层上；以及加热焊料膏层，从而将焊料膏层转换成多孔扩散焊料层中。
优选地，在加热期间对焊料膏层施加的最高温度小于220℃。
优选地，方法进一步包括在加热期间对焊料膏层施加外部压力。
优选地，外部压力在从3MPa到40MPa的范围内。
优选地，焊料膏层进一步包括埋设有第一颗粒和第二颗粒的聚合物材料。
优选地，第一颗粒包括从由银、铜、金和铟构成的组中选择的第一金属成分，以及从由锡和锌构成的组中选择的第二金属成分。
本文还提供了一种提供具有焊料膏的半导体芯片的方法，该方法包括：将包括第一金属成分的第一颗粒、第二金属成分的第二颗粒以及B阶段聚合物材料的焊料膏层涂覆在晶圆表面上；加热焊料膏层以预固化B阶段聚合物材料；以及将晶圆单个化为多个半导体芯片。
优选地，涂覆焊料膏层包括印刷、箔剥离、分配、旋涂或溅射。
优选地，焊料膏层的总金属贡献包括第一金属成分的重量百分比是50%至75%并且第二金属成分的重量百分比是25%至50%的化学组合物。
本文还提供了一种半导体装置，该装置包括导电载体；半导体芯片，设置在载体上；焊料层，设置在载体和半导体芯片之间，其中，半导体芯片具有邻近焊料层的多孔结构。
优选地，多孔结构是多孔硅层或多孔陶瓷层。
附图说明
附图被包括以提供对实施方式的进一步理解并且被结合到本说明书中并构成本说明书的一部分。附图示出了实施方式并且与描述一起用于说明实施方式的原理。因为其他实施方式和实施方式的多个预期的优点通过参考以下具体实施方式而变得更好理解，所以将更容易地理解它们。附图的元件不需要相对彼此按比例绘制。相同的参考标号表示对应的相似部件。
在附图和描述中，相同的参考标号通常用于指所有相同的元件。应注意，附图中示出的各种元件和结构无须按比例绘制。特征和/或元件主要为了清晰和易于理解而被示出为具有相对于彼此的特定尺寸；因此，在实际的实现中的相对尺寸可以与本文中示出的尺寸大不相同。
图1A至图1E示意性地示出了将半导体芯片接合在导电载体上的方法的一个实施方式的截面图；
图2A至图2D示意性地示出了将半导体芯片接合在导电载体上的方法的一个实施方式的截面图；
图3A至图3D示意性地示出了将半导体芯片接合在导电载体上的方法的一个实施方式的截面图；
图4A至图4D示意性地示出了设置具有多孔扩散焊料接合层的半导体芯片的方法的一个实施方式的截面图；
图5A至图5C是在增大放大率的情况下的多孔扩散焊料层的截面电子显微镜图像；以及
图6A至图6D示意性地示出了设置具有多孔接合层的半导体芯片的方法的一个实施方式的截面图。
具体实施方式
在以下具体实施方式中，对构成具体实施方式的一部分的附图进行了参照并且在附图中通过图示本发明可以实施的具体实施方式的方式来示出具体实施方式。鉴于此，将参照正在描述的附图的朝向来使用诸如“顶”、“底”、“前”、“后”、“领先”、“尾随”等的方向术语。因为实施方式的组件能够以多个不同的朝向放置，所以方向术语为了说明的目的而使用并且绝不作为限制。应当理解的是，在不偏离本发明的范围的情况下，可以采用其他实施方式并且可以做出结构或逻辑的改变。因此，以下具体实施方式不应当被认为是限制，而本发明的范围由所附权利要求来定义。
应当理解的是，本文中描述的各种示例性实施方式的特性可以彼此合并，除非另有具体地指示。
如在本说明书中采用的，术语“耦接”和/或“电耦接”并不意在表示元件必须直接耦接在一起的意思；可以在“耦接”或“电耦接”的元件之间设置中间元件。
下面将描述包含半导体芯片的装置。具体地，可以涉及具有垂直结构的半导体芯片，即，可以这样一种方式来制作半导体芯片，使得电流能够在与半导体芯片的主表面垂直的方向上流动。具有垂直结构的半导体芯片在其两个主表面上（即在其顶侧和底侧上）具有电极。
具体地，涉及功率半导体芯片。功率半导体芯片具有垂直的结构。该垂直的功率半导体芯片例如构造成功率MOSFET(金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结栅场效应晶体管）、功率双极晶体管或功率二极管。例如，功率MOSFET的源电极和栅极电极可以位于一个主表面上，同时功率MOSFET的漏电极布置在另一个主表面上。半导体芯片不需由例如，硅、碳化硅、锗化硅、砷化镓的特定半导体材料制造，并且此外可以包含不是半导体的无机和/或有机材料。半导体芯片可以是不同的类型并且可以由不同的技术制造。
半导体可以具有接触焊盘（或电极），该接触焊盘允许与在半导体芯片中包括的集成电路进行电接触。接触焊盘包括应用到半导体芯片的半导体材料中的一个或多个金属层。金属层可以以任何所希望的几何形状以及任何所希望的材料组合物来制造。例如，金属层可以是覆盖区域的层的形式。能够形成扩散焊料接合的任何所需的金属（例如，铜、磷化镍、锡化镍、金、银、铂、钯）以及这些金属中的一种或多种的合金可以用作材料。金属层无需是同质的或只由一种材料制造。即包含在金属层中的材料可以是各种组合物以及具有各种浓度。
多孔扩散焊料层可以用于将半导体芯片电连接和机械地连接至载体。导电多孔扩散焊料层可以提供低应力、机械稳定以及导热和导电性高的接合。
更具体地，通过多孔扩散焊料层传输的应力σ与ρ-2成比例，其中，ρ是多孔扩散焊料层中的孔隙密度，即，多孔扩散焊料层中的孔隙密度的增大（例如，两倍）大幅度地降低（例如，以22=4的因数）在半导体芯片和导电载体之间的应力。降低应力有益于提高封装的生产产量和寿命并且有益于防止在运行期间发生故障。
多孔扩散焊料层可以包括平均直径在0.1μm和30μm之间（更具体地，在1μm和10μm之间）的范围内的金属颗粒。这些颗粒中的大部分或几乎每个都包括金属间相。因为这些颗粒中存在金属间相，所以多孔焊料层称为多孔扩散焊料层。
金属间相由第一金属成分、第二金属成分、以及可选的第三或额外的金属成分制成。第一金属成分可以包括银、铜、金和铟中的一种或多种或由银、铜、金和铟中的一种或多种制成。第二金属成分可以包括锡和锌中的至少一种或多种或由锡和锌中的至少一种或多种制成。
多孔扩散焊料层包括第二金属成分的重量百分比是25%至50%的化学组合物。具体地，多孔扩散焊料层包括第一金属成分的重量的百分比是50%至75%、第二金属成分的重量百分比是25%至50%的化学组合物以及可选地包括一种或多种剩余金属组合物。该组合物是金属间相的组合物，该金属间设置在建立多孔扩散焊料层的颗粒的大部分或几乎每个中。
建立多孔扩散焊料层的颗粒中的大部分或几乎每个均是烧结的颗粒。因此，多孔扩散焊料层可以包括烧结的或相互扩散的结构。通过将热和压力施加到产生多孔扩散焊料层的预备层可以同时实现颗粒烧结的处理与在颗粒中形成金属间相的处理。在施加热量和压力的期间，预备层中的颗粒可以聚结，在邻近颗粒之间的过渡区域处以及在颗粒中可以发生扩散，从而在颗粒之间和颗粒中交换和分配第一金属成分和第二金属成分，并且颗粒可以烧结。
被施加以烧结和形成金属间相的温度可以大幅度地低于第二成分的金属的熔化温度（当以宏观尺寸设置时）。例如，可以施加在100℃和200℃之间或在100℃和180℃之间或在100℃和150℃之间的范围内的温度。
可以基于所施加的温度、所希望的孔隙率、所希望的导电率、层厚度、平均颗粒尺寸等来选择用于烧结和形成金属间相的所施加的压力。例如，可以施加在3MPa到40MPa之间或在5MPa到20MPa之间的范围内的压力。例如，在一些实施方式中，使用大约10MPa的压力。
多孔扩散焊料层的孔隙率的特征量（诸如，多孔扩散焊料层的孔隙密度和/或平均颗粒尺寸）可以很大程度上由在金属间相形成期间（以及，例如，在烧结期间）施加的温度和压力来控制。此外，该特征的属性可以受到在施加温度和/或压力之前所应用的颗粒的颗粒尺寸的选择的影响。例如，可以在预备层中使用在0.5μm和30μm之间（更具体地，在2μm和10μm之间）的范围内的第一金属成分和第二金属成分的平均颗粒尺寸。
多孔扩散焊料层可以具有在从1μm至50μm之间，并且更具体地，在1μm到20μm之间，并且又更具体地，在1μm到5μm之间的范围内的厚度。厚度越小，多孔焊料层的导电性和导热性就越好。
图1A至图1E示意性地示出了根据本公开将半导体芯片安装在导电载体上的方法。图1A示意性地示出了导电载体10。导电载体10可以是例如引线框的裸片焊盘、PCB（印刷电路板）、DCB（直接铜接合）等，DCB是在其顶表面和底表面上具有铜层的陶瓷衬底。导电载体10由能够形成扩散焊料接合的任何所希望的金属（例如，铜、磷化镍、锡、金、银、铂、钯、等或这些金属中的一种或多种的合金）制成或具有由这些金属制成的上表面11。此外，如将在以下进一步更详细地解释的，导电载体10的上表面11可以由具有低熔点的涂层覆盖。例如，该涂层可以包括或由锡、锌或这些材料中的一种或多种的任何合金制成。
在图1B中，焊料膏层21在载体10的上表面11之上形成。焊料膏层21可以通过涂覆包含分布在聚合物材料中的金属颗粒的膏剂来形成。该膏剂可以是液态的、粘性的或蜡状的。该膏剂可以包括第一金属成分、第二金属成分、以及优选的此外的金属成分的金属颗粒。第一金属成分可以包括银、铜、金以及铟中的至少一种或多种。第二金属成分可以包括锡和锌中的至少一种或多种。例如，聚合物材料可以是诸如b阶段树脂、α-松油脂等的树脂。聚合物材料可以是未填充的，即在聚合物材料中可以不包括填充物颗粒。
例如，包含金属颗粒的膏剂可以从Coocson Electronic、AdvancedNano-Particles(ANP)、Harima Chemicals或NBE Technologies购得。金属颗粒的尺寸（平均直径）可以小于30μm、10μm、5μm，或更具体地，小于1.0μm或0.5μm。金属颗粒的尺寸（平均直径）可以大于0.1μm、0.5μm、1.0μm，或更具体地，大于2μm或5μm。
例如，包含金属颗粒的膏剂可以通过混合各自包含一种或多种上述金属的颗粒的两种以上的商用膏剂来产生。例如，如果意图生产包含具有Ag3Sn金属间相的金属颗粒的多孔扩散焊料膏，则将三份包含第一金属成分的金属（银）的第一膏剂与一份包含第二金属成分的金属（锡）的膏剂混合。
包含分散到液态的、粘稠的或蜡状的聚合物或其组合中的（例如，不同的）金属颗粒的焊料膏层21的涂覆可以通过印刷技术（诸如，例如模版印刷、丝网印刷、喷墨印刷等）来进行。用于涂覆膏剂的其他技术（诸如，例如箔剥离技术或点胶技术（dispensing technique））也是可行的。所有这些技术同样允许在导电载体10的上表面11上涂覆可控量的膏剂材料。
焊料膏层21的厚度可以基本均匀。否则，可以应用变平技术（levelingtechnique）以便提供均匀（恒定）的焊料膏层厚度。具体地，如果点胶技术用于涂覆焊料膏层21，则变平技术可以是适合的。
可选地，例如如图1B中所示，载体10可以具有导电的下表面12。焊料膏层21也可以涂覆到下表面12。关于焊料膏层21的组成和在下表面12上涂覆焊料膏层21的技术和方法，对以上描述进行参考以避免重复。
如上所述，例如，聚合物材料可以是b阶段聚合物。在本文中，b阶段可固化聚合物应当被理解为通常可在两个阶段中固化的聚合物，这两个阶段称为预固化阶段和（最终）固化阶段。这样的聚合物通常在沉积在例如载体表面（诸如，载体10的表面11或12）上之后是可流动的和/或在预固化期间是可流动的。预固化可以将b阶段聚合物转换为固体状态并且使焊料膏层21粘附或粘合至导电载体10。在最终固化期间及之后，当总体上完成聚合物材料的交叉链接时，材料就不再是可流动的。
b阶段可固化聚合物可以包括各种材料（例如，包括a-松油脂型聚合物、氰基丙烯酸酯、聚酰亚胺、聚酰亚胺聚合物等）中的一种或多种。该聚合物可以包括粘合剂。例如，该粘合剂可以包括形式为（b阶段）树脂的环氧树脂粘合剂、形式为（b阶段）树脂的丙烯酸酯粘合剂或氰基丙烯酸酯粘合剂、包括环氧树脂和聚胺硬化的热固聚合物。
根据图1C，焊料膏层中的b阶段可固化聚合物可以通过施加例如热、UV辐射、γ辐射或其他技术来预固化。根据各种实施方式，例如，通过加热，可以在第一温度Tc实现预固化。例如，Tc可以小于或约为100℃。例如，聚合材料还可以是在预固化期间可挥发的溶剂或液体。
预固化焊料膏层由参考符号21a表示。如果没有使用b阶段聚合物材料，则省略参照图1C示出的处理并且参考符号21a指代与焊料膏层21相同的焊料膏层。
根据图1D，半导体芯片30放置在预固化的焊料层21a上（或，如果没有使用b阶段聚合物材料，则放置在焊料膏层21上）。例如，半导体芯片30可以具有在半导体芯片30的下表面32处的芯片电极（未示出）。可选地，在半导体芯片30的下表面32处的芯片电极可以由中间层40覆盖，中间层40由第一金属成分（例如，银、铜、金、铟）的一种或多种材料和/或第二金属成分（例如，锡、锌）的一种或多种材料制成。例如，中间层40可以包括银或由银制成、或可以包括涂有银的锡等或由涂有银的锡等制成。中间层40可以被布置为与预固化的焊料膏层21a（或焊料膏层21）邻接。
半导体芯片30可以进一步包括在半导体芯片30的上表面31处的一个或多个芯片电极。如上所述，半导体芯片30可以是垂直的半导体装置和/或功率装置。例如，功率MOSFET的源电极和栅极电极可以位于上表面31上，同时功率MOSFET的漏电极可以布置在下主表面32上。
图1E示意性地示出了预固化焊料膏层21a（或，如果没有执行预固化，则是焊料膏层21）加热到温度Ts，以便将半导体芯片30稳固地附着到导电载体10。例如，通过导电载体10和半导体芯片30放置在其上的加热板可以加热。
在下文中，如果没有另行说明，则术语焊料膏层21包括没有预固化的焊料膏层21和经过预固化的焊料膏层21a。在加热期间，焊料膏层21受扩散焊接处理的影响。更具体地，因为温度Ts保持低于第二金属成分的熔点，所以第二成分的金属材料不会熔化。例如，锡具有232℃的熔化温度。焊料膏层21暴露于低于232℃的最高温度Ts。例如，对焊料膏层施加的最高温度可以低于220℃、200℃、180℃、或150℃。
在施加的温度Ts，第一金属成分（例如，银、铜、金、铟）的颗粒还可以不熔化。因此，在图1E中的加热期间，基本保持焊料膏层21的粒状的颗粒结构。
在加热期间可以施加外部压力P。例如，外部压力可以在从3MPa到40MPa的范围内，更具体地，在5MPa到20MPa的范围内。即使施加外部压力P，也会保留焊料膏层21的粒状、颗粒型结构。然而，压力的施加可以增加在图1E中形成的多孔扩散焊料膏层的颗粒之间的孔隙率或内部接触区域的密度或影响。
在加热以及例如加压期间，形成金属间相。通过增加温度和施加的压力来促使或加速金属间相的形成。温度越高，在邻近颗粒中和在邻近颗粒之间的扩散动力就越高。温度越高，在邻近颗粒之间的接触就越剧烈，着也促进了特别是在(不同的金属的）邻近颗粒之间的边界处的金属间相的形成。
在形成金属间相的同时，烧结了焊料膏层21。烧结还可发生在相同金属的颗粒之间。烧结和形成金属间相均使焊料膏层获得高导电性和高导热性以及高级的机械属性。具体地，多孔扩散焊料层提供在机械上安全、强大而又耐用的半导体芯片30到导电载体10的附着，同时允许在半导体芯片30和导电载体10之间的低应力接合。因此，可以以高产量和低花费来获得低应力、机械稳定以及高导热性和高导电性的接合。
仍参照图1E，应当注意，加热还可导致聚合物材料从多孔扩散焊料层22蒸发。更具体地，根据使用的聚合物材料（例如，在是b阶段材料的情况下），聚合物材料在加热期间可大部分地或几乎全部从多孔扩散焊料层22去除。如在烧结领域中已知的，聚合物材料可以作为有机烧尽材料，有机烧尽材料具有对多孔扩散焊料层22的结构（例如，孔隙率、平均孔隙体积、孔隙密度）的影响。多孔扩散烧结层22可以因此由包含第一金属成分、第二金属成分以及可选的其他金属成分的烧结颗粒和在烧结金属颗粒之间的空间中形成的空间构成。
图2A至图2D例示了将半导体芯片30安装到导电载体10上的处理的阶段。联系图2A至图2D描述的处理的各个方面可以联系其他附图来与本文中描述的处理合并，反之亦然。
在图2A中，设置了导电载体10。对图1A的对应描述进行参考。
在图2B中，焊料层21沉积在导电载体10的上表面11上。与图1B示出的实施方式相对比来构造焊料膏层21。即，在沉积期间或通过诸如，掩模、蚀刻等后续处理，焊料膏层21可以被设计成具有特定的、希望的侧面形状和外延。例如，图2B中的焊料膏层21具有焊面（即，平坦的接触层）或拉长的导体形式。焊料膏层21可以只沉积在导电载体10的上表面11上。即，与图1B相对比，导电载体10的下表面12可以保持暴露。不言而喻的是，在所有的实施方式中，导电载体10的任意数量的表面可以由焊料膏层21来覆盖。
在图2C中，半导体芯片30放置在所构造的焊料膏层21上。如之前所述，半导体芯片30可配备有布置在焊料膏层21与半导体芯片30的底部电极（未示出）之间的中间层或可不配备有该中间层。中间层40还可以沉积在焊料膏层21的上表面上，而半导体芯片30放置在之前沉积的中间层40上。此外，中间层40可以是经过烧结的层。至于可以形成中间层40的材料，对以上公开进行参考。
进一步至图2C，焊料膏层21可以是在之前参照图1C和图1D描述的预固化焊料膏层21a。
根据图2D，半导体芯片30通过施加热量T以及例如压力P来固定至导电载体10。在该处理期间形成多孔扩散焊料层22。如图2D中示出的多孔扩散焊料层22的结构、组成、厚度以及所有其他属性可以与以上提出的对应属性相同。
图3A至图3D示出了将半导体芯片30安装到导电载体10上的处理的阶段。联系图1A至图1E和图2A至图2D描述的处理的各方面可以与下文中描述的合并，反之亦然。
在图3A中，设置了导电载体10，对图1A和图2A的描述进行参考。
在图3B中，导电载体10的上表面11由涂层50覆盖。涂层50可以包括诸如锡或锌的具有低熔点的金属或由这些金属制成。涂层50还包括薄（例如，约10-200nm，例如，约100nm）防锈保护层，该薄防锈保护层包括诸如银、金、钯等贵金属或由这些金属制成。防锈保护层防止涂层50的下层低熔点金属的氧化。
例如，如图3B中所示，导电载体10的下表面12也可由涂层50覆盖。
在图3C中，半导体芯片30放置在导电载体10上。如之前所述，半导体芯片30可以具有上表面31和下表面32。这些表面31和32中的每个都可以包含一个或多个芯片电极（未示出）。在图3C中，焊料膏层121覆盖位于半导体芯片30的下表面32的电极。焊料膏层121可以在所有属性上均与焊料膏层21或预固化的焊料膏层21a一致。如果与预固化的焊料膏层21a一致，则更早地执行联系图1C描述的预固化温度处理。下面将联系图4C进一步描述制造具有焊料膏层121的半导体芯片30的实施方式。
在图3D中，半导体芯片30通过加热（在焊料膏层121是温度Ts）和压力P固定至导电载体10。以这种方式，如上所述，焊料膏层121（或预固化的焊料膏层121a）转化为多孔扩散焊料膏层122。多孔扩散焊料膏层122在所有属性上都可以与多孔扩散焊料膏层22一致，并且因此，对本文中的对应公开进行参考以便避免重复。
如通过图3B至图3D的示例示出的，载体10的下表面12可以可选地由涂层50覆盖。在这种情况下，类似于联系图1A至图1E所述的示例性处理，半导体芯片30还可（例如，同时地）固定至导电载体10的下表面12。
图4A至图4D例示了设置如在上述图3C的处理中所使用的配备有焊料膏层121（包括预固化的焊料膏层121a）的半导体芯片30的处理的阶段。
在图4A中，设置了半导体晶圆200。半导体晶圆200可以包括在之前的半导体晶圆处理步骤中形成的集成电路。此外，例如，与相应集成电路相关联的芯片电极还可在之前的晶圆处理步骤中产生并且位于下主表面上并且可选地，也位于半导体晶圆200的上主表面上。
在图4B中，焊料膏层221沉积在半导体晶圆200的下主表面上。焊料膏层221以及将焊料膏层221涂覆到晶圆200的技术可以与如上所述的焊料膏层21的公开一致。还可使用在晶圆技术中已知的其他层形成和处理技术，诸如，旋涂、溅射、化学和/或机械抛光（CMP）。具体地，焊料膏层221可以具有相同的组成、相同的厚度并且可选地可以通过与本文中之前参照图1A至图1E以及图2A至图2E来解释的方式相同的方式来构造（未示出）。
在图4C中，类似于图1C，焊料膏层221可以被预固化以便生成预固化的焊料膏层221a。例如，如果焊料膏层221包含b阶段聚合物材料，则可以使用预固化方法。在温度Tc完成预固化过程。例如，Tc小于或约为100℃。联系图4A至图4C描述的所有处理步骤均可在晶圆级上实现。
如图4D所示，然后半导体芯片30通过分离半导体晶圆200并且可能分离焊料膏层221（或预固化的焊料膏层221a）来彼此分离。例如，锯、切、蚀刻或激光束切割可以用于分离步骤。不言而喻的是，如果之前已经构造焊料膏层221，则焊料膏层221（或预固化的焊料膏层221a)的分离可以是不必要的。图4D示出了可以在图3C的处理中使用的配备有预固化的焊料膏层121a的多个独立化的半导体芯片30。
不言而喻的是，如图4C中所示，焊料膏层221的预固化处理可以省去或在半导体晶圆200分为独立的半导体芯片30之后执行。更具体地，还可在分离步骤之后执行图4B至图4C中所示的处理。图4A至图4D中所示的处理还提供由未经固化的焊料膏层121涂覆的半导体芯片30。
图5A至图5C以不同放大率示出了显示多孔扩散焊料层22、122的结构的扫描电子显微镜（SEM）的图像。
图5A示出了显示设置在引线框10和半导体芯片30之间的多孔扩散焊料层22和122的SEM图像。此外，与涂层50对应的引线框镀层和与芯片电极对应的芯片后侧金属化70是可见的。在这个实施方式中，多孔扩散焊料层22和122具有50%的重量的银和50%的重量的锡的组合物。此外，使用了Ts=150℃和P=10MPa的处理参数。
如可以从图5A中看出的，在宏观尺度上，多孔扩散焊料层22和122更确切地是不均匀的。具体地，可以看见几十微米的量级的大空区（即，层厚度的量级）。
图5B以更大的放大率示出了图5A的部分视图的SEM图像。明显地，多孔扩散焊料层22、122示出了至少跨扩散焊料层22、122的大部分的微观孔隙率。
图5C是图5B的一部分的放大。可以从图5C中看出，由烧结的颗粒形成的微观多孔结构设置在多孔扩散焊料层22和122中。如从图像显而易见的，由烧结的颗粒和空区形成多孔构造。颗粒至少部分地彼此接触。通过调查证实了在颗粒中出现了金属间相。这里，例如，SEM图像示出了包括例如Ag3Sn金属间相的一些颗粒的多孔结构。当然，多孔扩散焊料层的结构和组成在整个层厚度上不可能是完全均匀的。多孔焊料层的区域的孔隙可以比其他区域更密集/更稀疏，并且还可以存在高压缩的实质上没有或很少孔隙的区域。然而，即使在层中的孔隙的分布有些不均匀的情况下，层的整个机械属性也会由于多孔结构极大地改变。
图6A至图6D例示了将半导体芯片30安装在导电载体10上的处理的阶段。如图6A所示，设置了导电载体10。
根据图6D，导电载体10可设置有例如之前参照图3B描述的一个或两个涂层50。
在图6C中，半导体芯片30放置在导电载体10上。半导体芯片30配备有多孔层321。例如，多孔层321可以由多孔陶瓷材料或多孔硅制成。可以通过蚀刻半导体晶圆200或半导体芯片30的对应表面（例如，下表面32）来获得多孔硅。
更具体地，具有多孔层321的半导体芯片30可以按照类似于图4A至图4D示出的处理来生产。如果多孔层321是多孔硅层，则图4B中示出的处理将转换成通过例如硅蚀刻（而非涂覆焊料膏层221）来生成此多孔硅层321。并且图4D中示出的处理将转换成对具有多孔硅层321的对应部分的对应半导体芯片30进行个别化或分离。如果多孔层321是多孔陶瓷层，则图4B中示出的处理转换成将多孔陶瓷层321（而非焊料膏层221）涂覆在半导体晶圆200的下表面上，并且图4D中示出的处理转换成将配备有多孔陶瓷层321的对应部分的独立半导体芯片30分离。
返回图6A至图6D示出的处理，半导体芯片30可以通过施加热量（温度Ts)和压力P附着至导电载体10。这里，涂层50的低熔点材料（即，焊接材料）连接至位于多孔层321底部的芯片电极（未示出），并且从而将半导体芯片30固定至导电载体10。多孔层321位于半导体芯片30的芯片电极（未示出）和体材料之间并且在半导体芯片30和导电载体10之间提供低应力和机械稳定的接合。
尽管本发明的实施方式的具体特征或方面可能只关于几个实现中的一个来公开，但是该特征或方面可以其他实现的一个或多个其他特征或方面结合，因为这可能是所希望的并且可能是对于任何给定或特定应用有利的。
尽管本文中已经示出和描述了特定的实施方式，但是本领域中的普通技术人员应当理解，在不偏离本发明的范围的情况下，可以对所示出和所描述的特定实施方式进行多种变形、执行多种改造并且实现多种变化。相应地，本文中讨论的特定实施方式的任何这样的变形、改造和变化旨在由权利要求覆盖并且本发明仅受权利要求的范围的限制。

Claims (27)

1.一种半导体装置，包括：
导电载体；
半导体芯片，设置在所述载体上；以及
多孔扩散焊料层，设置在所述载体和所述半导体芯片之间。
2.根据权利要求1所述的半导体装置，其中，所述多孔扩散焊料层包括具有金属间相的颗粒。
3.根据权利要求2所述的半导体装置，其中，所述颗粒包括从由银、铜、金和铟构成的组中选择的第一金属成分，以及从由锡和锌构成的组中选择的第二金属成分。
4.根据权利要求3所述的半导体装置，其中，所述多孔扩散焊料层包括所述第一金属成分的重量百分比是50%至75%并且所述第二金属成分的重量百分比是25%至50%的化学组合物。
5.根据权利要求2所述的半导体装置，其中，所述多孔扩散焊料层的颗粒被烧结或相互扩散。
6.根据权利要求1所述的半导体装置，进一步包括设置在所述载体和所述多孔扩散焊料层之间的第一中间层，其中，所述第一中间层包括锡或锌。
7.根据权利要求6所述的半导体装置，其中，所述第一中间层包括由防锈层形成的表面。
8.根据权利要求1所述的半导体装置，其中，所述多孔扩散焊料层包括在从1μm到50μm的范围内的厚度。
9.根据权利要求1所述的半导体装置，其中，所述载体是引线框。
10.根据权利要求1所述的半导体装置，进一步包括设置在所述多孔扩散焊料层和所述半导体芯片之间的第二中间层，其中，所述第二中间层包括烧结的或相互扩散的金属层。
11.一种半导体布置，包括：
半导体本体；以及
焊料膏层，设置在所述半导体本体的至少一个主表面的上方，所述焊料膏层包括从由银、铜、金和铟构成的组中选择的第一金属成分的第一颗粒；从由锡和锌构成的组中选择的第二金属成分的第二颗粒；以及埋设所述第一颗粒和所述第二颗粒的聚合物材料。
12.根据权利要求11所述的半导体布置，其中，所述聚合物材料包括B阶段聚合物材料。
13.根据权利要求12所述的半导体布置，其中，所述B阶段聚合物材料被预固化。
14.根据权利要求11所述的半导体布置，其中，所述聚合物材料是溶剂或液体。
15.根据权利要求14所述的半导体的布置，其中，所述溶剂或液体在预固化期间可蒸发。
16.根据权利要求11所述的半导体布置，其中，所述焊料膏层的总金属贡献包括所述第一金属成分的重量百分比是50%至75%并且所述第二金属成分的重量百分比是25%至50%的化学组合物。
17.一种在导电载体上接合半导体芯片的方法，所述方法包括：
在所述导电载体上形成焊料膏层，所述焊料膏层包括第一金属成分的第一颗粒和第二金属成分的第二颗粒；
将所述半导体芯片放置在所述焊料膏层上；以及
加热所述焊料膏层，从而将所述焊料膏层转换成多孔扩散焊料层。
18.根据权利要求17所述的方法，其中，在加热期间对所述焊料膏层施加的最高温度小于220℃。
19.根据权利要求17所述的方法，所述方法进一步包括在所述加热期间对所述焊料膏层施加外部压力。
20.根据权利要求19所述的方法，其中，所述外部压力在从3MPa到40MPa的范围内。
21.根据权利要求17所述的方法，其中，所述焊料膏层进一步包括埋设所述第一颗粒和所述第二颗粒的聚合物材料。
22.根据权利要求17所述的方法，其中，所述第一颗粒包括从由银、铜、金和铟构成的组中选择的第一金属成分，以及从由锡和锌构成的组中选择的第二金属成分。
23.一种提供具有焊料膏层的半导体芯片的方法，所述方法包括：
将包括第一金属成分的第一颗粒、第二金属成分的第二颗粒以及B阶段聚合物材料的焊料膏层涂覆在晶圆表面上；
加热所述焊料膏层以预固化所述B阶段聚合物材料；以及
将所述晶圆单个化为多个半导体芯片。
24.根据权利要求23所述的方法，其中，涂覆所述焊料膏层包括印刷、箔剥离、点胶、旋涂或溅射。
25.根据权利要求23所述的方法，其中，所述焊料膏层的总金属贡献包括所述第一金属成分的重量百分比是50%至75%并且所述第二金属成分的重量百分比是25%至50%的化学组合物。
26.一种半导体装置，包括：
导电载体；
半导体芯片，设置在所述载体上；
焊料层，设置在所述载体和所述半导体芯片之间，其中，所述半导体芯片具有邻近所述焊料层的多孔结构。
27.根据权利要求26所述的半导体装置，其中，所述多孔结构是多孔硅层或多孔陶瓷层。
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CN109565139A (zh) * 2016-08-11 2019-04-02 D.M.贝纳塔夫有限责任公司 多种直径的线材的连接
JP2019525423A (ja) * 2016-08-11 2019-09-05 ディー、エム、 ベナタフ リミテッド 複数の直径を有する電線の接続
CN109565139B (zh) * 2016-08-11 2021-05-14 D.M.贝纳塔夫有限责任公司 多种直径的线材的连接
JP7140747B2 (ja) 2016-08-11 2022-09-21 ディー、エム、 ベナタフ リミテッド 複数の直径を有する電線の接続

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