CN103681385A - Semiconductor device and making method thereof - Google Patents

Semiconductor device and making method thereof Download PDF

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Publication number
CN103681385A
CN103681385A CN201310012644.8A CN201310012644A CN103681385A CN 103681385 A CN103681385 A CN 103681385A CN 201310012644 A CN201310012644 A CN 201310012644A CN 103681385 A CN103681385 A CN 103681385A
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semiconductor device
temperature
epoxy resin
semiconductor chip
metallic
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佐藤慧
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
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    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/83909—Post-treatment of the layer connector or bonding area
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

The invention provides a semiconductor device and a making method thereof; a simple making method is employed to obtain high reliability under soldering tin connecting condition. Firstly, the temperature rises up to a preheating temperature (zone I: warming step); then, the preheating temperature is kept for 50-120 seconds (Zone II: preheating step), the preheating temperature is 20-40 DEG C lower than the hardening temperature (180 DEG C) of the epoxy resin, i.e., the preheating temperature is about 150 DEG C; then, a peak temperature is between 260 to 280 DEG C and is high than a melting point (220 DEG C) of metal particle (soldering tin) 52, for example, the peak temperature is 250 DEG C and kept about 30-50 seconds (Zone III: melting step). In the making method and preheating step, a welding agent is formed to surround a periphery of a semiconductor chip in a non-hardening state; then in the melting step, metal particles in a dense state are melted and fused.

Description

The manufacture method of semiconductor device, semiconductor device
Technical field
The present invention relates to have the manufacture method of the semiconductor device of the structure that is equipped with semiconductor chip on metallic plate.
Background technology
Generally speaking, when using semiconductor chip, form the semiconductor device with following structure: the structure that is equipped with semiconductor chip on metallic plate is packaged in insulating properties mold resin bed, as the lead-in wire of terminal, from mold resin bed, derives.
Fig. 5 is the perspective view of observing an example of this semiconductor device 90 from above.Here, in the mold resin bed 91 of the cuboid shape as growing crosswise, be provided with two lower bolsters (metallic plate).In this structure, semiconductor chip 92 is equipped on lower bolster 93, and semiconductor chip 94 is equipped on lower bolster 95.Lead-in wire 96 has respectively 4 at upside, downside, and being set to derives from mold resin bed 91.A part in lead-in wire 96 and the lower bolster 93,95 of adjacency are integrated, other lead-in wire 96 and lower bolster 93,95 insulation.Electrode in semiconductor chip 92,94, lower bolster 93,95, respectively go between and utilize thin bonding wire (bonding wire) 97 to connect between 96, so that their form the circuit of expectation.Bonding wire 97 is also encapsulated in mold resin bed 91.For example, can adopt power semiconductor chip as semiconductor chip 92, adopt the control IC chip that this power semiconductor chip is controlled as semiconductor chip 94.
Here, semiconductor chip 92,94 is engaged in respectively lower bolster 93,95 by scolding tin mostly.In this case, if at the back of the body surface forming electrode of semiconductor chip 92,94, this electrode engages with electricity between lower bolster 93,95 and the fixing of semiconductor chip 92,94 can utilize this scolding tin to carry out.
In order to utilize this scolding tin to engage, mostly adopt solder(ing) paste.As solder(ing) paste, adopt: the particle (metallic) consisting of the metal (alloy) that becomes scolding tin main component is blended in the material forming in unhardened resin material (solder flux (flux)).This solder(ing) paste is formed on metallic plate by for example silk screen printing.Afterwards, at semiconductor-chip-mounting, thereon, heat, after metallic fusing, be cured, engage thus.Now, after metallic fusing, after appropriateness diffusion, solidify, carried out thus good joint.Solder flux for become can coating metal particle state use, but also play, remove the oxide-film, activated metal plate surface of metallic or metal sheet surface and improve the effects such as wetability to solder(ing) paste, to the joint of strengthening scolding tin, be also effective.
In patent documentation 1, recorded following technology: when utilizing solder(ing) paste to carry out bump bond to semiconductor chip, at the electrode surface engaging, form pre-groove, control thus the wetting diffusion of scolding tin, can obtain the good bond that there is no short circuit or bad joint.
In addition, in patent documentation 2, record and utilize epoxy resin as the solder flux main component in solder(ing) paste.Generally speaking, engage after residual flux constituent can become the obstacle while connecting bonding wire etc.Therefore, mostly by cleaning, remove residual flux constituent, connect afterwards bonding wire etc.With respect to this, in the technology of recording, become still residual state of epoxy resin after sclerosis in patent documentation 2.Thus, can strengthen the joint of scolding tin and improve the reliability engaging.
Patent documentation 1: TOHKEMY 2009-4463 communique
Patent documentation 2: TOHKEMY 2003-124400 communique
But, in the technology of recording at patent documentation 1, need to process the face engaging.Here, the face of joint refers to the back side and the metallic plate of semiconductor chip.In this processing, need new step, particularly, when the situation areas different, composition surface of the bump bond of recording from patent documentation 1 are very large, it is complicated that manufacturing step becomes.Therefore,, from reducing the viewpoint of manufacturing cost, preferably append such step.In addition,, although the Surface Machining of metallic plate is possible, be in fact difficult to the back side of processing semiconductor chip.
In addition, metallic fusing and form the knitting layer of fusion, forms firmly alloy-layer between this knitting layer and the semiconductor chip engaging, metal sheet surface, can obtain high bond strength thus.Now, in knitting layer, be formed with empty in the situation that, be difficult to obtain high bond strength.When utilizing solder(ing) paste to engage, the space forming when metallic melts and fuses becomes cavity after cooling.In the technology of recording in patent documentation 2, in the moment of metallic fusing, in the situation that its epoxy resin has around hardened, this epoxy resin becomes the obstacle of air from discharging between molten metal particle while engaging, and therefore in soldering-tin layer, easily produces cavity.Therefore, be difficult to guarantee the high reliability in joint.The situation that this problem is little with the such bonding area of bump bond is compared, in the situation that bonding area is large remarkable especially during the whole back side of bond semiconductor chip.
That is, by easy manufacture method, being difficult to acquisition utilizes scolding tin to carry out the high reliability in joint situation.
Summary of the invention
The present invention completes just in view of the above problems, and its object is to provide the invention addressing the above problem.
The present invention, in order to solve above-mentioned problem, has formed the structure disclosing below.
The manufacture method of semiconductor device of the present invention, solder(ing) paste is clipped between semiconductor chip and metallic plate and engages described semiconductor chip and described metallic plate, this manufacture method is characterised in that, described solder(ing) paste comprises 85～90wt%(percentage by weight) metallic, epoxy resin as solder flux, curing agent and the activator with activation effect, this manufacture method has chips welding (die bond) step, in this chips welding step, after scolding tin engages, utilize unhardened described epoxy resin to cover at least a portion of the circumferential lateral surface of scolding tin joint and the circumferential lateral surface of described semiconductor chip.
In the manufacture method of semiconductor device of the present invention, it is characterized in that, described epoxy resin consists of thermosetting epoxy resin, the hardening temperature of this thermosetting epoxy resin is lower than the fusing point of described metallic, described chips welding step has: preheating step, at than the temperature of low 20～40 ℃ of described hardening temperature, within the time in 50～120 seconds, duplexer is kept, and this duplexer is that described solder(ing) paste and the described laminating metal plate in unhardened state forms by described semiconductor chip, described epoxy resin; Fusing step, after described preheating step, is heated to described duplexer than more than the high temperature of the fusing point of described metallic; And cooling step, after described fusing step, to described duplexer, carry out cooling.
The manufacture method of semiconductor device of the present invention is characterised in that, after described cooling step, at than the temperature of low 10～40 ℃ of described hardening temperature, keeps described duplexer, and described epoxy resin is hardened completely.
Semiconductor device of the present invention is characterised in that, this semiconductor device is to manufacture by the manufacture method of described semiconductor device.
The present invention forms as described above, therefore can be obtained and be utilized scolding tin to carry out the high reliability in joint situation by easy manufacture method.
Accompanying drawing explanation
Fig. 1 means the step cutaway view of the manufacture method of the semiconductor device that embodiment of the present invention relates to.
Fig. 2 means the figure of the temperature curve in the engagement step adopting in the manufacture method of the semiconductor device relating in embodiment of the present invention.
Fig. 3 is by the outward appearance photo of the semiconductor device of the manufacture method manufacture as embodiment.
Fig. 4 is by the section S EM photo of the semiconductor device of the manufacture method manufacture as embodiment.
Fig. 5 is the perspective view of the structure of general semiconductor device.
Symbol description
10,92,94: semiconductor chip; 20,93,95: metallic plate (lower bolster); 50: solder(ing) paste; 51: solder flux (resin material); 52: metallic (soldering tin powder); 53: knitting layer; 91: mold resin bed; 96: lead-in wire; 97: bonding wire.
Embodiment
Below, the manufacture method of the semiconductor device as embodiment of the present invention is described.Fig. 1 means the step cutaway view of the semiconductor device of manufacturing by this manufacture method.Here shown in is the cross section that semiconductor chip 10 is engaged in metallic plate (lower bolster) 20 o'clock (chips welding step).This joint utilizes solder(ing) paste 50 to carry out.And, in fact, as shown in Figure 5, after this engages, carry out as inferior step, manufacture semiconductor device: by semiconductor chip 10, metallic plate 20 are connected to bonding wire, by having connected bonding wire total afterwards, be encapsulated in mold resin bed.In these steps, identical with the technology conventionally, therefore description thereof is omitted.Only chips welding step is described below.
First as shown in Fig. 1 (a), by methods such as silk screen printings by solder(ing) paste 50 compositions and be coated on metallic plate 20.Solder(ing) paste 50 is configured in solder flux (resin material) 51 and mixes and be dispersed with the metallic (soldering tin powder) 52 as scolding tin.The content of solder flux 51 in solder(ing) paste 50 is for example about 13 quality %.Solder flux 51, by for example resin (epoxy resin, aqueous bisphenol A-type), has the curing agent (acid anhydride) of active sclerosis, solvent (glycols), and thixotropic agent (amine), activator (organic acid) forms.The viscosity of solder(ing) paste 50 is for example about 70～130Pas under the state of coating.
Metallic 52 for example consists of silver (Ag)-copper (Cu)-Xi (Sn) alloy, for example, can use to take Sn and be about respectively the material of 3 quality % and 0.5 quality % as main component, Ag and Cu.Its average grain diameter is about 25～45 μ m.The composition of metallic 52 in solder(ing) paste 50 is about 85～90wt%.
Under the state following closely after being coated with solder(ing) paste 50, solder flux 51, in unhardened state, has appropriate viscosity, so solder(ing) paste 50 can maintain the shape in (a) of Fig. 1.And the flat shape of the flat shape of solder(ing) paste 50 now and engaged semiconductor chip 10 about equally.Thus, whole lower surface that can bond semiconductor chip 10.
Below, as shown in Fig. 1 (b), under this state, semiconductor chip 10 is carried on solder(ing) paste 50.Utilize solder(ing) paste 50(solder flux 51) viscosity maintain this state.
Then, the stepped construction (structure) of this semiconductor chip 10, solder(ing) paste 50, metallic plate 20 is dropped in reflow soldering and heat-treated.Thus, after 52 fusings of metallic in solder(ing) paste 50, solidify, carry out engage (engagement step) between semiconductor chip 10 and metallic plate 20.Fig. 2 represents an example of the temperature curve (temperature over time) in engagement step.Here, as the hardening temperature of the epoxy resin of solder flux 51 main components, be 180 ℃, the fusing point of metallic 52 is than its high 220 ℃.Particularly, engagement step consists of heating step (region I), preheating step (region II), fusing step (region III), cooling step (region IV), in reflow soldering, under nitrogen environment, carries out.Feature in this engagement step is the preheating step keeping within a certain period of time under being arranged on than the low temperature of the hardening temperature of epoxy resin before fusing step.
In Fig. 2, first make temperature rise to preheat temperature (region I: heating step).Then, this preheat temperature is held (region II: preheating step) in 50～120 seconds.Preheat temperature is the temperature of low 20～40 ℃ of hardening temperature (180 ℃) than epoxy resin, is about 150 ℃ in present embodiment.In this step, carry out the gasification of the organic solvent in solder flux 51, the metallic 52 in the activation of solder flux 51, solder flux 51 and the oxide removal on metallic plate 20 surfaces.On the other hand, due to the activation of not carrying out sclerous reaction and having improved solder flux 51, therefore form the wetting diffusion of epoxy resin of solder flux 51.In addition, preheat temperature is lower than the fusing point of metallic 52, so the form of metallic 52 does not change.And the time of preferred heating step is shorter, to shorten the time of whole engagement step, and the time of prolongation preheating step.
Therefore,, after preheating step, as shown in Fig. 1 (c), solder(ing) paste 50 attenuation of semiconductor chip 10 bottoms, become the form that the bottom of semiconductor chip 10 is only supported by metallic 52.On the other hand, the wetting diffusion of solder flux 51, the circumferential lateral surface of surrounding semiconductor chip 10 by surface tension, becomes the peripheral part of semiconductor chip 10 by the form of presclerotic solder flux 51 coverings.The quantitative change of the solvent 51 that metallic under semiconductor chip 10 is 52 is few, becomes the state that metallic 52 is intensive.In addition, the activation of the epoxy resin of mixing, surface, reducing metal, improves scolding tin degree of wetting.
Afterwards, making peak temperature is 260～280 ℃ scopes higher than the fusing point of metallic (scolding tin) 52 (220 ℃), for example 250 ℃, and keeps for 30～50 seconds (region III: fusing step).Now, owing to reaching the hardening temperature of solder flux 51, surpass afterwards the fusing point of metallic 52, therefore, first solder flux 51 starts sclerosis, then metallic 52 fusings.Wherein, solder flux 51 needs the time from starting sclerous reaction to abundant sclerosis, therefore in fact at metallic 52, starts the moment of fusing, and solder flux 51 is also unhardened.On the other hand, metallic 52 is fusing rapidly in the situation that temperature surpasses its fusing point, and the fusion of metallic 52 advances.
In this manufacture method, become solder flux 51 in preheating step and under unhardened state, surround the form of the peripheral part of semiconductor chip 10.Then, in fusing step, the metallic 52 of high density state melts and fuses.Now, solder flux 51 is not sclerosis completely also, therefore becomes air from the passage of 52 discharges of metallic.Therefore, be difficult for forming cavity.On the other hand, the state that semiconductor chip 10 is fixed on metallic plate 20 guarantees by being present in the solder flux 51 of periphery.Therefore, in this step, be difficult to occur the position deviation of semiconductor chip 10.
Wherein, the temperature in preheating step be time of or preheating step lower than the temperature of low 80 ℃ of hardening temperature for than in 50 seconds short situations, the effect of preheating step is insufficient., solder flux 51 is difficult to become the form of Fig. 1 (c).In addition, this temperature for than the time of the temperature of low 15 ℃ of hardening temperature high (approaching hardening temperature) or preheating step than 120 clock seconds when long, the moment sclerosis of the morning of solder flux 51 in ensuing fusing step therefore easily produces empty in knitting layer 53.
Then, carry out cooling (region IV: cooling step).Along with temperature reduces, molten metal particle 52 solidifies under the state of fusion, forms knitting layer 53.Solder flux 51 hardens surrounding under knitting layer 53 state around, therefore becomes the form shown in (d) of Fig. 1.Now, as previously mentioned, suppressed to produce cavity in knitting layer 53.Here, spent for 30～60 seconds, in the temperature range from 270 ℃ to 100 ℃ (170 ℃ of temperature differences), carry out cooling.Above, chips welding step finishes.
In order further to advance the sclerosis of solder flux 51 to obtain sufficient intensity (sclerosis completely), effectively: at the temperature with preheat temperature same degree, for example, than the temperature of low 10～40 ℃ of the hardening temperature of epoxy resin (180 ℃), at 150 ℃, carry out the curing processing (curing schedule) of long-time (approximately 5 hours).Thus, solder flux 51 also can obtain sufficient intensity.And when carrying out this curing processing, the bubble in solder flux 51 is removed.
Here, about following the state and the state (state of sclerosis completely) that follows the solder flux 51 after curing schedule closely of chips welding step (cooling step) solder flux 51 afterwards closely, on experimental substrate, print above-mentioned solder(ing) paste 50, carry chip part and also engage, at joint, measure afterwards with the distribution intensity of the flux residue of experimental substrate fluid-tight engagement and evaluate.In this experiment (mensuration), following cooling step distribution intensity afterwards closely is 20N, and following curing schedule distribution intensity afterwards closely is 40N.Like this, in above-mentioned manufacture method, be characterised in that, solder flux 51 is not sclerosis at once after cooling step.
Generally speaking, the flux constituent of using in welding is removed mostly after joint, but the solder flux 51(epoxy resin of this sclerosis) do not need to remove, just can join to semiconductor chip 10 and the metallic plate 20 such as bonding wire.In addition,, by the solder flux 51 of sclerosis, strengthen knitting layer 53.In addition, keep semiconductor chip, and improved bond strength.For this point, be identical with the technology of recording in patent documentation 2.
Then, bonding wire is connected in to semiconductor chip 10, metallic plate 20 etc., then they is encapsulated and is formed mold resin bed, can obtain semiconductor device thus.In above-mentioned example, to carry the example of single semiconductor chip in single metal plate, record, but in fact mostly utilize a plurality of metallic plates (lower bolster) and on same metallic plate, carry a plurality of semiconductor chips.In addition, adopt at the lead frame that is arranged with the structure of a plurality of metallic plates suitable with a plurality of semiconductor devices, on each metallic plate, carry respectively semiconductor chip, connect bonding wire and form respectively mold resin bed afterwards, manufacture thus a plurality of semiconductor devices.Then, by suitably cutting off lead frame, obtain each semiconductor device.
Fig. 3 is from observing the outward appearance photo of the semiconductor device of manufacturing by above-mentioned manufacture method above.In this structure, be equipped with a plurality of semiconductor chips 10, but no matter about which semiconductor chip 10, all confirmed to surround the solder flux 51 of semiconductor chip 10 peripheries sclerosis.
Fig. 4 is electron microscope (SEM) photo at the interface of the semiconductor chip end in the semiconductor device same with Fig. 3.Here, be also formed with the mold resin bed 91 of Fig. 5.Different from mold resin bed 91, can confirm that solder flux 51 forms peripheral part at semiconductor chip 10 and is diffused into approximately 180 μ m and surrounds.On the other hand, can confirm to be about in the knitting layer 53 of 30 μ m and not find to have formed good joint in cavity at thickness.The side of the end of knitting layer 53, semiconductor chip 10 is covered by solder flux 51.As mentioned above, can confirm: realized the shape of Fig. 1 (d), obtained empty few knitting layer 53.In addition, preferred solder flux 51 covers the more than 2/3 of side of semiconductor chips 10.
But also known, even in the situation that the composition of solder flux, metallic is different from above-mentioned example, as thering are the hardening temperature of same characteristic, particularly solder flux or the fusing point of metallic etc. when equal, just can obtain same effect.

Claims (5)

1. a manufacture method for semiconductor device, is clipped in solder(ing) paste between semiconductor chip and metallic plate and engages described semiconductor chip and described metallic plate,
This manufacture method is characterised in that,
The metallic that described solder(ing) paste comprises 85 percentage by weight～90 percentage by weights, the epoxy resin as solder flux, the curing agent with activation effect and activator,
This manufacture method has chips welding step, in this chips welding step, after scolding tin engages, utilizes unhardened described epoxy resin to cover at least a portion of the circumferential lateral surface of scolding tin joint and the circumferential lateral surface of described semiconductor chip.
2. the manufacture method of semiconductor device according to claim 1, is characterized in that,
Described epoxy resin consists of thermosetting epoxy resin, and the hardening temperature of this thermosetting epoxy resin is lower than the fusing point of described metallic,
Described chips welding step has:
Preheating step, at～the temperature of 40 ℃ lower 20 ℃ than described hardening temperature, within the time in 50～120 seconds, duplexer is kept, this duplexer is that described solder(ing) paste and the described laminating metal plate in unhardened state forms by described semiconductor chip, described epoxy resin;
Fusing step, after described preheating step, is heated to described duplexer than more than the high temperature of the fusing point of described metallic; With
Cooling step, after described fusing step, carries out cooling to described duplexer.
3. the manufacture method of semiconductor device according to claim 2, is characterized in that,
After described cooling step, at～the temperature of 40 ℃ lower 10 ℃ than described hardening temperature, keep described duplexer, described epoxy resin is hardened completely.
4. a semiconductor device, is characterized in that,
This semiconductor device is to manufacture by the manufacture method of the semiconductor device described in claim 1 or 2.
5. a semiconductor device, is characterized in that,
This semiconductor device is to manufacture by the manufacture method of semiconductor device claimed in claim 3.
CN201310012644.8A 2012-08-31 2013-01-14 Semiconductor device and making method thereof Pending CN103681385A (en)

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JP2012-192277 2012-08-31
JP2012192277A JP2014049647A (en) 2012-08-31 2012-08-31 Manufacturing method of semiconductor device, semiconductor device

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