CN103681361B - 微凸块结构的制造方法 - Google Patents

微凸块结构的制造方法 Download PDF

Info

Publication number
CN103681361B
CN103681361B CN201310108676.8A CN201310108676A CN103681361B CN 103681361 B CN103681361 B CN 103681361B CN 201310108676 A CN201310108676 A CN 201310108676A CN 103681361 B CN103681361 B CN 103681361B
Authority
CN
China
Prior art keywords
ball
cushion
stannum
stannum ball
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310108676.8A
Other languages
English (en)
Other versions
CN103681361A (zh
Inventor
廖宗仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Publication of CN103681361A publication Critical patent/CN103681361A/zh
Application granted granted Critical
Publication of CN103681361B publication Critical patent/CN103681361B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • H01L2224/05582Two-layer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/111Manufacture and pre-treatment of the bump connector preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/111Manufacture and pre-treatment of the bump connector preform
    • H01L2224/1111Shaping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Abstract

本揭露涉及一种微凸块(micro bump)结构的制造方法,其包含提供一基板;形成一球下冶金层于该基板中供容置锡球;设置一缓冲层于该基板上;置放一锡球于该球下冶金层上并与其接合;以及硏磨该锡球使其高度达到一预定值。

Description

微凸块结构的制造方法
技术领域
本发明系关于一种微凸块结构的制造方法,特别是关于一种使用一般尺寸锡球即可形成之微凸块结构之制造方法。
背景技术
电子装置结合许多不同的电子元件和电连接器以执行预先决定的功能。锡球是电子装置中广泛使用的导电元件。近年来由于可携式产品的潮流,电子装置面临体积上的大幅减少。因此,安装于电子装置中的电子元件和导电元件必须制造出更小的体积以符合小型电子装置的需求。因此为了缩小导电元件,一般都适用价格较高的微凸块来形成微凸块结构。是故,产业界对于价格适中的微凸块结构制造方法仍有一定需求。
发明内容
本揭露内容的一个目的系提供一成本便宜的微凸块结构制造方法,此方法可利用原尺寸锡球制作成微凸块结构。
为达上述目的,本揭露内容提供一种微凸块结构的制造方法,包含提供一基板的步骤;形成一球下冶金层于该基板中供容置锡球的步骤;设置一缓冲层于该基板上的步骤;置放一锡球于该球下冶金层上并与其接合的步骤;以及研磨该锡球使其高度达到一预定值的步骤,以供完成微凸块结构。
本揭露内容亦提供另一种微凸块结构的制造方法,包含提供一基板的步骤;形成一球下冶金层于该基板中,该球下冶金层供容置一锡球的步骤;提供一离型层的步骤;设置一锡球于该离型层上的步骤;研磨该锡球使该锡球高度达到一预定值的步骤;接合具有该预定值之该锡球于该球下冶金层的步骤;以及去除该离型层的步骤,以供完成微凸块结构。
上文已相当广泛地概述本揭露内容的技术特征,俾使下文之本揭露详细描述得以获得较佳了解。构成本揭露内容的申请专利范围标的的其他技术特征将描述于下文。本揭露内容所属技术领域中具有通常知识者应了解,可相当容易地利用下文揭示之概念与特定实施例可作为修改或设计其他结构或制程而实现与本揭露内容相同之目的。本揭露内容所属技术领域中具有通常知识者亦应了解,这类等效建构无法脱离后附之申请专利范围所界定的本揭露内容的精神和范围。
附图说明
图1显示为本揭露内容一实施例之微凸块结构的制造方法之步骤流程图;
图2显示为本揭露内容一实施例之提供基板之示意图;
图3显示为本揭露内容一实施例之形成球下冶金层于基板之示意图;
图4显示为本揭露内容一实施例之设置缓冲层于基板之球下冶金层上之示意图;
图5显示为本揭露内容一实施例之经由曝光显影方式移除部分缓冲层之示意图;
图6显示为本揭露内容一实施例之置放锡球于球下冶金层上并与其接合之示意图;
图7显示为本揭露内容一实施例之硏磨锡球使其高度达到一预定值之示意图;
图8显示为本揭露内容一实施例之回焊步骤加热研磨后的锡球之示意图;
图9显示为本揭露内容一实施例之自基板剥离缓冲层进而完成微凸块结构之示意图;
图10显示为本揭露内容另一实施例之将锡球设置于球下冶金层上并与其接合之示意图;
图11显示为本揭露内容另一实施例之将缓冲层设置于基板之锡球上并覆盖锡球之示意图;
图12显示为本揭露内容另一实施例之微凸块结构的制造方法之步骤流程图;
图13显示为本揭露内容又一实施例之提供离型层之示意图;
图14显示为本揭露内容又一实施例之设置锡球于离型层上之示意图;
图15显示为本揭露内容又一实施例之研磨锡球,进而使锡球高度达到一预定值之示意图;
图16显示为本揭露内容又一实施例之自该基层剥离该缓冲层之示意图;
图17显示为本揭露内容又一实施例之接合具有预定值高度之锡球于球下冶金层之示意图;
图18显示为本揭露内容又一实施例之去除离型层之示意图;以及
图19显示为本揭露内容再一实施例之微凸块结构之示意图。
【主要元件符号说明】
10基板
110晶圆层
120氮化物层
12球下冶金层
14缓冲层
20锡球
21微凸块结构
30离型层
31基层
33缓冲层
40铜柱
具体实施方式
本发明在此所探讨的方向为微凸块结构的制造方法。为了能彻底地了5解本发明,将在下列的描述中提出详尽的步骤及结构。显然地,本发明的施行并未限定于相关领域之技艺者所熟习的特殊细节。另一方面,众所周知的结构或步骤并未描述于细节中,以避免造成本发明不必要之限制。本发明的较佳实施例会详细描述如下,然而除了这些详细描述之外,本发明还可以广泛地施行在其他实施例中,且本发明的范围不受限定,其以之后的申请专利范围为准。
在下文中本揭露的实施例系配合所附图式以阐述细节。说明书所提及的「实施例」、「此实施例」、「其他实施例」等等,意指包含在本发明之该实施例所述有关之特殊特性、构造、或特征。说明书中各处出现之「在此实施例中」的片语,并不必然全部指相同的实施例。此外,本发明之申请专利范围及发明说明描述的元件若无特别标示其数量时则为单数。若标示元件的量词为一时,则量词包含一单位或至少一单位。若标示元件的量词为复数个时,则量词包含两个以上的单位。若标示元件的量词未显示时,则量词包含一单位或两个以上的单位。
如图1所示,微凸块结构的制造方法包含步骤1010提供一基板;步骤1020形成一球下冶金层于该基板中供容置锡球;步骤1030设置一缓冲层于该基板上;步骤1040置放一锡球于该球下冶金层上并与其接合;以及步骤1050硏磨该锡球使其高度达到一预定值。上述步骤的数字并不必然为各步骤的顺序,如步骤1040亦可先于步骤1030执行。
图1所示之步骤流程图配合图2至图9所示各步骤结构的描述如下。在步骤1010中,提供如图2所示之基板10。基板10包含复数层结构层(例如晶圆层110及氮化物层120),可为晶圆或晶片等。
在步骤1020中,如图3所示,形成一球下冶金层12于该基板10上以供容置锡球(图未示)。
在步骤1030中,如图4所示,设置一缓冲层14于该基板10之球下冶金层12上,因此缓冲层14完全覆盖该球下冶金层12。
由于球下冶金层12系用于容置锡球(图未示),因此覆盖球下冶金层12的缓冲层14需被移除。此外,本揭露内容之微凸块结构的制造方法另包含步骤以供曝光显影或加入蚀刻缓冲层14而去除部分缓冲层14,如图5所示。此外,在其他实施例中,缓冲层14设置步骤亦可将缓冲层14设置于基板10,同时缓冲层14并不覆盖球下冶金层12,而如图5所示。换言之,缓冲层14亦可设置于供锡球接合之球下冶金层12周围。
在此实施例中,缓冲层14的材质可选自负型光阻、正型光阻、液态光阻及干膜(DryFilm),因此缓冲层14经由曝光显影后,缓冲层14则暴露球下冶金层12。缓冲层14厚度范围介于锡球20高度的1/2至1/3之间。
在步骤1040中,如图6所示,置放一锡球20于该球下冶金层12上并与其接合。
在步骤1050中,如图7所示,研磨该锡球20使其高度达到一预定值(小于原本高度)。
如图8所示,本揭露内容的微凸块结构的制造方法另包含一回焊步骤,其加热研磨后的锡球20,进而使锡球20形成微凸块结构,经由回焊步骤加热后的锡球20高度小于或等于研磨前锡球20高度的一半。
参照图8及图9所示,本揭露内容的微凸块结构的制造方法另包含一步骤,此步骤自基板10移除(如剥离)缓冲层14进而完成微凸块结构21。
本揭露的微凸块结构的制造方法之另一实施例中,当步骤1010及1020执行后,先执行步骤1040而将锡球20设置于球下冶金层12上并与其接合,如图10所示。
在步骤1030中,如图11所示,将缓冲层14设置于基板10的锡球20上并覆盖锡球20。在此实施例中,缓冲层14的材质可选自负型光阻、正型光阻、液态光阻及干膜。缓冲层14厚度范围介于锡球20高度的1/2至1/3之间。
此外,本揭露内容的微凸块结构的制造方法另包含曝光显影缓冲层14的步骤。如图6所示,缓冲层14经由曝光显影或加以蚀刻后,缓冲层14则曝露球下冶金层12上之锡球20。而后之步骤如上述图7至图9的描述而完成本揭露内容的微凸块结构21,在此不再赘述。
如图12所示,微凸块结构的制造方法包含步骤1210提供一基板;步骤1220形成一球下冶金层于该基板中供容置锡球;步骤1230提供一离型层;步骤1240设置一锡球于该离型层上;步骤1250研磨该锡球使该锡球高度达到一预定值;步骤1260接合具有该预定值高度之该锡球于该球下冶金层以及步骤1270去除该离型层。上述步骤的数字并不必然为各步骤的顺序。
图12所示之步骤流程图配合图13至图18所示各步骤结构的描述如下。步骤1210及1220相似于上述步骤1010及1020,因此在此不再赘述。
在步骤1230中,如图13所示,提供一离型层30,离型层30包含一基层31及缓冲层33。缓冲层33设置于基层31上。在此实施例中,基层31包含一铜膜,而缓冲层33为一干膜,该干膜厚度范围介于该锡球20高度的1/2至1/3之间。其中缓冲层33可为一种干膜光阻,其可由盖膜(成份:聚烯Polyester/PET)、光阻(Photoresist)及分隔膜(成份:聚乙烯Polyethylene/PE)所组成。前述干膜光阻组成仅为本揭露内容中其一之实施例,实务上并不以此为限。在其他实施例中,如图13所示,缓冲层33暴露部分基层31,此暴露的结构系由曝光显影该缓冲层33的步骤来暴露基层31。此实施例中,缓冲层33的材质可选自负型光阻、正型光阻及液态光阻,因此缓冲层33经由曝光显影后,缓冲层33则暴露基层31。
在步骤1240中,如图14所示,设置一锡球20于该离型层30上。具体而言,锡球20系设置于缓冲层33暴露基层31之处,换言之,锡球20系设置于基层31上。此外,在其他实施例(图未示)中,锡球20可直接设置于基层31而后再设置缓冲层33于锡球20周围,而产生如图14所示之结构。
在步骤1250中,如图15所示,研磨锡球20,进而使锡球20高度达到一预定值。
参照图15及图16所示,本揭露之微凸块结构的制造方法进一步包含自该基层31剥离该缓冲层33。
在步骤1260中,如图17所示,接合具有该预定值高度之该锡球20于该球下冶金层12。在此一步骤中,该球下冶金层12上可预先涂设助焊剂(未图示),俾以接合该锡球20,在此锡球接合步骤进一步包含一回焊步骤用以供加热研磨后的锡球20,该回焊步骤加热后的锡球20高度小于或等于研磨前锡球20高度的一半。由于基层31包含一铜膜,因此锡球接合步骤中的回焊步骤势必熔化一部分铜与锡球20混合进而提升锡球20中的铜比例。
在步骤1270中,如图17及图18所示,当完成锡球接合步骤后,则可去除离型层30之基层31进而形成如图18所示之微凸块结构。
此外,在步骤1220中,另包含设置铜柱40于球下冶金层12上,如图19所示。于步骤1250研磨锡球20后,将研磨后的锡球20接合于铜柱40上,进而完成如图19所示之微凸块结构。同样地,在该铜柱40上亦可预先涂设些许之助焊剂(未图示),以供锡球20接合于铜柱40上。
本揭露内容的技术内容及技术特点已揭示如上,然而本揭露内容所属技术领域中具有通常知识者应了解,在不背离后附申请专利范围所界定之本揭露精神和范围内,本揭露内容的教示及揭示可作种种之替换及修饰。例如,上文揭示之许多装置或结构或方法步骤可以不同之方法实施或以其他结构予以取代,或者采用上述二种方式之组合。
本案之权利范围并不局限于上文揭示之特定实施例的制程、机台、制造、物质之成份、装置、方法或步骤。本揭露内容所属技术领域中具有通常知识者应了解,基于本揭露教示及揭示制程、机台、制造、物质之成份、装置、方法或步骤,无论现在已存在或日后开发者,其与本案实施例揭示者系以实质相同的方式执行实质相同的功能,而达到实质相同的结果,亦可使用于本揭露。因此,以下之申请专利范围系用以涵盖用以此类制程、机台、制造、物质之成份、装置、方法或步骤。

Claims (19)

1.一种微凸块结构的制造方法,包含:
提供一基板;
形成一球下冶金层于该基板中供容置锡球;
设置一缓冲层于该基板上,该缓冲层厚度范围介于该锡球高度的1/2至1/3之间;
置放一锡球于该球下冶金层上并与其接合;以及
研磨该锡球使其高度达到一预定值。
2.根据权利要求1所述的制造方法,其中该缓冲层置于该球下冶金层上。
3.根据权利要求2所述的制造方法,进一步包含步骤:曝光显影该缓冲层,进而暴露该球下冶金层。
4.根据权利要求1所述的制造方法,其中该缓冲层设置步骤进一步包含设置该缓冲层于该基板并不覆盖该球下冶金层。
5.根据权利要求1所述的制造方法,其中该缓冲层设置步骤进一步包含设置该缓冲层于该锡球周围。
6.根据权利要求4及5所述的任一制造方法,进一步包含步骤:自该基板剥离该缓冲层。
7.根据权利要求6所述的制造方法,进一步包含一回焊步骤加热研磨后的锡球。
8.根据权利要求7所述的制造方法,其中该回焊步骤加热后的锡球高度小于或等于研磨前锡球高度的一半。
9.根据权利要求1所述的制造方法,进一步包含设置铜柱于球下冶金层上。
10.一种微凸块结构的制造方法,包含:
提供一基板;
形成一球下冶金层于该基板中,该球下冶金层供容置一锡球;
提供一离型层,该离型层包含一基层及一缓冲层,该缓冲层设置于该基层上,该缓冲层包含一干膜,且该干膜厚度范围介于该锡球高度的1/2至1/3之间;设置一锡球于该离型层上;
研磨该锡球使该锡球高度达到一预定值;
接合具有该预定值的该锡球于该球下冶金层;以及
去除该离型层。
11.根据权利要求10所述的制造方法,其中该基层包含一铜膜。
12.根据权利要求10所述的制造方法,其中该缓冲层为一干膜。
13.根据权利要求10所述的制造方法,进一步包含步骤:曝光显影该缓冲层,进而暴露该基层。
14.根据权利要求10所述的制造方法,其中该缓冲层设置步骤进一步包含设置该缓冲层于该锡球周围。
15.根据权利要求10-14所述的任一制造方法,进一步包含步骤:自该基层剥离该缓冲层。
16.根据权利要求10所述的制造方法,其中该锡球接合步骤进一步包含一回焊步骤加热研磨后的锡球。
17.根据权利要求16所述的制造方法,其中该回焊步骤加热后的锡球高度小于或等于研磨前锡球高度的一半。
18.根据权利要求10所述的制造方法,其中该锡球接合步骤提升该锡球中的铜比例。
19.根据权利要求10所述的制造方法,进一步包含设置一铜柱于球下冶金层上。
CN201310108676.8A 2012-08-31 2013-03-29 微凸块结构的制造方法 Active CN103681361B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101131683A TWI474454B (zh) 2012-08-31 2012-08-31 微凸塊結構的製造方法
TW101131683 2012-08-31

Publications (2)

Publication Number Publication Date
CN103681361A CN103681361A (zh) 2014-03-26
CN103681361B true CN103681361B (zh) 2016-08-03

Family

ID=50188137

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310108676.8A Active CN103681361B (zh) 2012-08-31 2013-03-29 微凸块结构的制造方法

Country Status (3)

Country Link
US (1) US9190324B2 (zh)
CN (1) CN103681361B (zh)
TW (1) TWI474454B (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834848A (en) * 1996-12-03 1998-11-10 Kabushiki Kaisha Toshiba Electronic device and semiconductor package
CN101853793A (zh) * 2009-03-27 2010-10-06 日东电工株式会社 半导体器件的制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US20070045840A1 (en) * 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
TWI378517B (en) * 2006-02-27 2012-12-01 Chipmos Technologies Inc Bumping process
US8035226B1 (en) * 2008-06-05 2011-10-11 Maxim Integrated Products, Inc. Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
US8927391B2 (en) * 2011-05-27 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package process for applying molding compound
US8735273B2 (en) * 2011-07-08 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Forming wafer-level chip scale package structures with reduced number of seed layers
US9111949B2 (en) * 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834848A (en) * 1996-12-03 1998-11-10 Kabushiki Kaisha Toshiba Electronic device and semiconductor package
CN101853793A (zh) * 2009-03-27 2010-10-06 日东电工株式会社 半导体器件的制造方法

Also Published As

Publication number Publication date
US9190324B2 (en) 2015-11-17
TW201409637A (zh) 2014-03-01
TWI474454B (zh) 2015-02-21
CN103681361A (zh) 2014-03-26
US20140065814A1 (en) 2014-03-06

Similar Documents

Publication Publication Date Title
US8890269B2 (en) Optical sensor package with through vias
CN103066081B (zh) 双向相机组合件
CN103119712A (zh) 使用在包括嵌入式管芯的内建非凹凸层衬底上的硅通孔的管芯堆叠,以及其形成工艺
CN101652695B (zh) 晶片级相机模块及制造方法
US9136289B2 (en) Camera module housing having built-in conductive traces to accommodate stacked dies using flip chip connections
US9419047B2 (en) Image sensor device with aligned IR filter and dielectric layer and related methods
WO2009066704A1 (ja) はんだ材料及びその製造方法、接合体及びその製造方法、並びにパワー半導体モジュール及びその製造方法
CN102969324B (zh) 半导体装置及用于在其上形成经图案化辐射阻挡的方法
JP2013544444A5 (zh)
WO2011051670A3 (en) Security device and method of manufacturing the same
CN103811448A (zh) 弯曲轮廓的堆叠封装件接头
US9013017B2 (en) Method for making image sensors using wafer-level processing and associated devices
US20160027751A1 (en) Semiconductor device having solder joint and method of forming the same
CN103681361B (zh) 微凸块结构的制造方法
TW201216420A (en) System and method of chip package build-up
US20190302913A1 (en) Touch panel and manufacturing method thereof
US9554468B2 (en) Panel with releasable core
CN108010930A (zh) 图像传感器及形成图像传感器的方法
KR102464716B1 (ko) 반도체 장치 및 그 제조 방법
CN105590937B (zh) 一种背照式图像传感器及其制备方法、电子装置
US20120241209A1 (en) Wafer-level electromagnetic interference shielding structure and manufacturing method thereof
US9378987B2 (en) Semiconductor packages including gap in interconnection terminals and methods of manufacturing the same
US20110272799A1 (en) Ic chip and ic chip manufacturing method thereof
US8956909B2 (en) Method of fabricating an electronic device comprising photodiode
CN205645813U (zh) 一种影像芯片模组

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant