CN103678250B - System level chip and its method for designing - Google Patents
System level chip and its method for designing Download PDFInfo
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Abstract
The invention provides a kind of system level chip and its method for designing, the system level chip includes Part I circuit and Part II circuit, wherein, the Part I circuit includes one or more SOC digital units；The Part II circuit includes one or more SOC analog components；The Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device, are connected by communication interface between the Part I circuit and Part II circuit.The present invention enables to SOC and reduction design cost is replied in process node escalation process, shortened time to market (TTM), reduced flow risk.
Description
Technical field
The present invention relates to SOC technologies, more particularly to a kind of system level chip and its method for designing.
Background technology
Existing system level chip（SOC, System on Chip）Method for designing, generally by various Digital Logic IP and
Various analogue unit IP are integrated on one chip, to improve integrated level to greatest extent.Wherein, Digital Logic IP can be wrapped
Include central processing unit（CPU）, digital signal processor（DSP）, enumerator（TIMER）, house dog（WATCHDOG）Etc. various things
The various computing units such as business processing unit, figure, video, audio frequency, encryption and decryption, SDMMC, universal asynchronous receiving-transmitting transmitter
（UART）, Serial Peripheral Interface (SPI)（SPI）Etc. various digital interfaces, USB (universal serial bus)（USB）, PCIe, SATA, HDMI etc. it is various
The protocol layer of HSSI High-Speed Serial Interface and connect the on-chip bus of each equipment, but be not limited to this；Analogue unit IP can be wrapped
Include modulus to walk around device（ADC）, digital to analog converter（DAC）, system, audio frequency and video phaselocked loop（PLL）And various HSSI High-Speed Serial Interfaces
Physical layer（PHY）, but it is not limited to this.Although all the above modules are all integrated on one chip can improve integrated
Degree, but problem is also following.
With the continuous lifting of prevailing technology node in recent years, chip companies are to keep up with prevailing technology node to reduce flow
Cost or in order to obtain higher system frequency, SOC products generally need constantly to change flow technique.Changing flow work
During skill, the upgrading of digital logic portion IP generally seldom brings increase and the potential risk of cost, but analogue unit IP
Generally need to redesign or authorized, the R ＆ D Cost or mandate expense for often leading to these analogue units IP is high；
And the upgrading of chip again flow can delay product Time To Market, once go wrong, loss will and its it is serious.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of system level chip and its method for designing, enables to SOC and exists
Design cost is greatly reduced in process node escalation process, is shortened time to market (TTM), reduced flow risk.
To solve above-mentioned technical problem, the invention provides a kind of system level chip, including Part I circuit and second
Partial circuit, wherein,
The Part I circuit includes one or more SOC digital units；
The Part II circuit includes one or more SOC analog components；
The Part I circuit and Part II circuit are arranged on different domains, nude film, chip or Programmable
On part, connected by communication interface between the Part I circuit and Part II circuit.
According to one embodiment of present invention, the Part I circuit and Part II circuit share same external storage
Device.
According to one embodiment of present invention, the communication interface is SERDES interfaces, and the Part I circuit includes：
First SERDES interfaces；
First general SERDES data link layers, are connected with a SERDES interfaces；
The Part II circuit includes：
2nd SERDES interfaces, are connected with a SERDES interface physicals；
Second general SERDES data link layers, are connected with the 2nd SERDES interfaces；
Memory Controller Hub and physical layer, SERDES data link layers general with described second are connected, the Part II electricity
Road is connected with the external memory storage via rambus；
Wherein, the right to use of the Part I circuit by the application rambus, general via described first
SERDES data link layers, a SERDES interfaces, the 2nd SERDES interfaces, the second general SERDES data link layers, internal memory
Controller and physical layer and rambus access the external memory storage；The Part II circuit is by applying for the internal memory
The right to use of bus, accesses the external memory storage via the Memory Controller Hub and physical layer and rambus.
According to one embodiment of present invention, the communication interface is SERDES interfaces, and the Part I circuit includes：
First SERDES interfaces；
First general SERDES data link layers, are connected with a SERDES interfaces；
Memory Controller Hub and physical layer, SERDES data link layers general with described first are connected, the Part I electricity
Road is connected with the external memory storage via rambus；
The Part II circuit includes：
2nd SERDES interfaces, are connected with a SERDES interface physicals；
Second general SERDES data link layers, are connected with the 2nd SERDES interfaces；
Wherein, the Part I circuit accesses the external memory storage via the rambus；The Part II
Circuit is via the described second general SERDES data link layers, the 2nd SERDES interfaces, a SERDES interfaces, first general
SERDES data link layers and Memory Controller Hub and physical layer and the rambus access external memory storage.
According to one embodiment of present invention, the Part I circuit also includes：
On-chip bus, SERDES data link layers general with described first are connected；
Issued transaction unit and computing unit, are connected with the on-chip bus, the issued transaction unit and computing unit Jing
Part II electricity by the on-chip bus, the first general SERDES data link layers and described in a SERDES interface accessings
Road.
According to one embodiment of present invention, the issued transaction unit include central processing unit, digital signal processor,
Enumerator and/or house dog, the computing unit include：Graphics calculations unit, video computing unit and/or encryption and decryption calculate single
Unit.
According to one embodiment of present invention, the Part I circuit also includes or many in circuits below module
It is individual：
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layers, SERDES data link layers general with described first are connected and on-chip bus phase
Even：
High-speed interface application layer, SERDES data link layers general with described first and on-chip bus are connected；
Storage communication digital interface, is connected with the on-chip bus；
System phaselocked loop, produces the first Digital Logic drive clock for other circuit moulds in the Part I circuit
Block is used.
According to one embodiment of present invention, the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer includes the data processing of audio frequency DAC
The data processing module of module, the data processing module of video AD C and/or touch screen；The high-speed interface application layer includes USB
Interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI application layer；The storage communication numeral
Interface includes SDMMC digital interfaces, UART digital interfaces and/or SPI digital interfaces.
According to one embodiment of present invention, the described first general SERDES data link layers will be from the on-chip bus
Data flow, the data flow of the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer and the data flow from the high-speed interface application layer
Data fusion is carried out, the data flow after combination of management, and set up data flow transmission, receive and retransmission mechanism.
According to one embodiment of present invention, the Part II circuit also includes or many in circuits below module
It is individual：
High speed interface protocol layer, SERDES data link layers general with described second are connected；
Digital interface, SERDES data link layers general with described second are connected；
Association's processing unit, SERDES data link layers general with described second are connected；
Physical layer, is connected with the high speed interface protocol layer；
ADCs and DACs, is connected with the digital interface；
Audio frequency and video phaselocked loop, produces the second Digital Logic drive clock for other circuits in the Part II circuit
Module is used.
According to one embodiment of present invention, the high speed interface protocol layer is by the data flow from high-speed interface application layer
Packing is packaged into the protocol package that meets interface definition and sends to the physical layer；The digital interface produce the ADCs and
The sequential interface of DACs, and send data to corresponding DACs or data are read in from corresponding ADCs；The physical layer
Including SATA physical layers, USB physical layers, PCIe physical layer and/or HDMI physical layers；Association's processing unit is used for described second
The operation initialization and operation control of partial circuit.
According to one embodiment of present invention, the described second general SERDES data link layers split general by described first
Data flow or encapsulation uplink data after the fusion of SERDES data link layers, wherein, the data flow after fractionation is distinguished
Send to the high speed interface protocol layer, ADCs and DACs or association's processing unit.
According to one embodiment of present invention, a SERDES interfaces and the 2nd SERDES interfaces include string simultaneously/and
String device, transmitting-receiving FIFO, receiving data align unit, timer manager, transmitting-receiving line interface, line codec and/or passage
Binding part.
According to one embodiment of present invention, the communication interface is ddr interface, and the Part I circuit includes：
First DDR master controllers and physical layer；
The Part II circuit includes：
DDR is connected from controller with a DDR master controllers and physical layer；
2nd DDR master controllers and physical layer, are connected from controller with the DDR, the DDR master controllers and physical layer
It is connected with external memory storage via rambus；
Wherein, the right to use of the Part I circuit by the application rambus, via a DDR master controls
Device processed and physical layer, DDR access the external storage from controller, the 2nd DDR master controllers and physical layer and rambus
Device；The right to use of the Part II circuit by the application rambus, via the 2nd DDR master controllers and physics
Layer and rambus access the external memory storage.
According to one embodiment of present invention, the Part I circuit also includes：
On-chip bus, are connected with a DDR master controllers and physical layer；
Issued transaction unit and computing unit, are connected with the on-chip bus, the issued transaction unit and computing unit Jing
The Part II circuit is accessed by the on-chip bus and a DDR master controllers and physical layer interface.
According to one embodiment of present invention, the issued transaction unit include central processing unit, digital signal processor,
Enumerator and/or house dog, the computing unit include：Graphics calculations unit, video computing unit and/or encryption and decryption calculate single
Unit.
According to one embodiment of present invention, the Part I circuit also includes or many in circuits below module
It is individual：
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layers, are connected with the on-chip bus and a DDR master controllers and physical layer：
High-speed interface application layer, is connected with the on-chip bus and a DDR master controllers and physical layer；
Storage communication digital interface, is connected with the on-chip bus；
System phaselocked loop, produces the first Digital Logic drive clock for other circuit moulds in the Part I circuit
Block is used.
According to one embodiment of present invention, the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer includes the data processing of audio frequency DAC
The data processing module of module, the data processing module of video AD C and/or touch screen；The high-speed interface application layer includes USB
Interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI application layer；The storage communication numeral
Interface includes SDMMC digital interfaces, UART digital interfaces and/or SPI digital interfaces.
According to one embodiment of present invention, a DDR master controllers and physical layer will be from the on-chip bus
Data flow, the data flow of the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer and the data flow from the high-speed interface application layer
Data fusion is carried out, the data flow after combination of management, and set up data flow transmission, receive and retransmission mechanism.
According to one embodiment of present invention, the Part II circuit also includes or many in circuits below module
It is individual：
High speed interface protocol layer, is connected from controller with the DDR；
Digital interface, is connected from controller with the DDR；
Association's processing unit, is connected from controller with the DDR；
Physical layer, is connected with the high speed interface protocol layer；
ADCs and DACs, is connected with the digital interface；
Audio frequency and video phaselocked loop, produces the second Digital Logic drive clock for other circuits in the Part II circuit
Module is used.
According to one embodiment of present invention, the high speed interface protocol layer is by the data flow from high-speed interface application layer
Packing is packaged into the protocol package that meets interface definition and sends to the physical layer；The digital interface produce the ADCs and
The sequential interface of DACs, and send data to corresponding DACs or data are read in from corresponding ADCs；The physical layer
Including SATA physical layers, USB physical layers, PCIe physical layer and/or HDMI physical layers；Association's processing unit is used for described second
The operation initialization and operation control of partial circuit.
According to one embodiment of present invention, the DDR is split by a DDR master controllers and physics from controller
Data flow or encapsulation uplink data after layer fusion, wherein, the data flow after fractionation is respectively sent to described second
DDR master controllers and physical layer, high speed interface protocol layer, ADCs and DACs or association's processing unit.
Present invention also offers a kind of system-Level IC Design method, including：
Each circuit module is divided into into Part I circuit and Part II circuit, the Part I circuit includes one
Individual or multiple SOC digital units, the Part II circuit include one or more SOC analog components；
The Part I circuit and Part II circuit are arranged on into different domains, nude film, chip or programmable
On device, connected by communication interface between the Part I circuit and Part II circuit.
According to one embodiment of present invention, the Part I circuit and Part II circuit share same external storage
Device.
According to one embodiment of present invention, the communication interface is SERDES interfaces or ddr interface.
Compared with prior art, the present invention has advantages below：
The system level chip of the embodiment of the present invention is divided into Part I circuit and Part II circuit, Part I circuit
It is relatively low to the dependency degree of technique, various SOC digital units can be for example included, Part II circuit is to the dependency degree for doing individual
It is higher, various SOC analog components can be for example included, wherein Part I circuit and Part II circuit is arranged on different versions
Figure, nude film（die）, chip（chip）Or on programming device, between the two by SERDES interfaces, ddr interface etc
Communication interface connects.Due to a variety of causes needs to reselect process node flow again when, it is only necessary to redesign
One for updating, upgrading is needed in a part of circuit and Part II circuit, and another in the two can still continue to use original
First domain, nude film, chip or programming device, as long as the communication interface specification that original definition is still complied between them connects
Connect, it is possible to form complete SOC devices, so as to significantly reduce design cost, shorten time to market (TTM), reduce stream
Piece risk.
Description of the drawings
Fig. 1 is the structured flowchart of the system level chip of first embodiment of the invention and coupled external memory storage；
Fig. 2 is the structured flowchart of the system level chip of second embodiment of the invention and coupled external memory storage；
Fig. 3 is the structured flowchart of the system level chip of third embodiment of the invention and coupled external memory storage.
Specific embodiment
In the present invention, each circuit module in traditional SOC is divided into into two parts：Part I circuit and
Two partial circuits, two parts are separately positioned on different domains, nude film, chip or programming device, are adopted between the two
Connected with communication interface, the communication interface can be serialization/de-serialization（SERDES）Interface, Double Data Rate synchronous dynamic with
Machine memorizer（DDR）Interface, or other appropriate high-speed interfaces.
Furthermore, the basic norm of division is the degree size for relying on manufacturing process, and wherein Part I circuit is not
Depend on concrete manufacturing process or dependency degree relatively low, for example, can include various SOC digital units, it can in addition contain include this
SOC digital units are in order to realize partial simulation part that its function is relied on；And Part II circuit is relied heavily on or
Person is completely dependent on concrete manufacturing process, for example, can include various SOC analog components, it can in addition contain include the SOC simulation parts
Part is in order to realize part number part that its function is relied on.
The distribution of Part I circuit and Part II circuit can for example have following situation：Part I circuit and second
Partial circuit can be arranged on different domains, that is, in same nude film（die）Different layout areas；Part I electricity
Road and Part II circuit can be arranged on different nude films, subsequently can be being encapsulated in the two using modes such as stacked packages
Same chip（chip）It is interior；Part I circuit and Part II circuit can be arranged on different chips, subsequently can be with
Using printed circuit board (PCB)（PCB）The two is coupled together etc. mode；One of Part I circuit and Part II circuit position
On chip, and another is located at programming device（Such as FPGA, but not limited to this）On, can subsequently adopt printed panel
（PCB）The two is coupled together etc. mode.
It should be noted that no matter a kind of any of the above described mode is adopted, between Part I circuit and Part II circuit
All connected by communication interface, to realize the data interaction between two parts.The communication interface be preferably SERDES interfaces and
Ddr interface, as the data interaction amount of system level chip is larger, the transmission bandwidth of needs is higher, and SERDES and ddr interface can be with
Meet the demand of data transfer bandwidth.
With reference to specific embodiments and the drawings, the invention will be further described, but should not limit guarantor of the invention with this
Shield scope.
First embodiment
With reference to Fig. 1, the system level chip of first embodiment（Or referred to as system level devices）It is divided into two parts：First
Partial circuit 100 and Part II circuit 200, the two is arranged on different domains, nude film, chip or programming device,
And connected by SERDES interfaces each other, data interaction therebetween follows SERDES related specifications.Wherein,
Part I circuit 100 mainly includes general digital part, such as one or more SOC digital units；Part II circuit 200
Mainly include SOC high-speed interfaces and analog portion, such as one or more SOC analog components.
Used as a preferred embodiment, Part I circuit 100 and Part II circuit 200 share same external storage
Device 300.External memory storage 300 can be various appropriate volatile memory, such as DDR1/2/3, LPDDR etc..
Furthermore, Part I circuit 100 includes a SERDES interfaces 101 and the first general SERDES Data-Links
Road floor 102, Part II circuit 200 include the 2nd SERDES interfaces 201 and the second general SERDES data link layers 202, its
In, the first general SERDES data link layers 101 are connected with a SERDES interfaces 102, the 2nd SERDES interfaces 201 and first
101 physical connection of SERDES interfaces, the second general SERDES data link layers 202 are connected with the 2nd SERDES interfaces 201.First
General SERDES data link layers 102 and the second general SERDES data link layers 202 can realize the upper strata of SERDES interfaces
Agreement.
Wherein, a SERDES interfaces 101 and the 2nd SERDES interfaces 102 are the realizations of high-speed serial I/O, are generally included
But be not limited to string simultaneously/and go here and there device, transmitting-receiving FIFO, receiving data align unit, timer manager, transmitting-receiving line interface, circuit compile
Decoder and/or passage binding part.Connection line 1 between first SERDES interfaces 101 and the 2nd SERDES interfaces 201 can
To follow LVDS specifications, but it is not limited to this.
Part II circuit 200 can also include Memory Controller Hub and physical layer（PHY）203, Memory Controller Hub and physics
203 SERDES data link layers general with second 202 of layer are connected, and Memory Controller Hub and physical layer 203 can also be total by internal memory
Line 2 is connected with external memory storage 300.
Furthermore, Part I circuit 100 can also include on-chip bus 103, issued transaction unit 106, calculate
Unit 107, ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 104, high-speed interface application layer 105, storage communication and are at digital interface 108
System phaselocked loop 109.It should be noted that above-mentioned modules are generality illustrating, the similar a certain class of representative feature or characteristic
Module, does not represent a certain concrete module or equipment, and the annexation between each module is as shown in figure 1, represent all kinds of moulds
There is data flow relation between block.
Wherein, issued transaction unit 106 includes but is not limited to central processing unit（CPU）, digital signal processor（DSP）、
Enumerator（TIMER）, house dog（WATCHDOG）Deng.
Computing unit 107 includes but is not limited to graphics calculations unit, video computing unit, encryption and decryption computing unit etc..
Storage communication digital interface 108 includes but is not limited to SDMMC digital interfaces, UART digital interfaces, SPI numerals and connects
Mouthful.High-speed interface application layer 105 include but is not limited to USB interface application layer, PCIe interface application layer, SATA interface application layer,
HDMI application layer, its input or output can be and operating system（OS）Interactive application data stream.
ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 104 includes but is not limited to the data processing module of audio frequency DAC, the number of video AD C
According to processing module, the data processing module of touch screen.The function of above-mentioned all kinds of processing modules implements can include：Video go every
The functions such as the functions such as row, scaling, post processing, the encoding and decoding of audio frequency, post processing, or the application data of touch screen processes etc..It is right
In audio frequency and video, its input or output are usually relatively simple data flow, directly can be processed by the next stage of data flow；And it is right
In other application or module, such as touch screen etc., its data flow can be directly processed by operating system.
System phaselocked loop 109 is used to produce the first Digital Logic drive clock for other in Part I circuit 100
Circuit module is used.
On-chip bus 103 and the first general SERDES data link layers 102, ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 104, height
The modules phases such as fast interface application layer 105, issued transaction unit 106, computing unit 107, storage communication digital interface 108
Even.
The first general SERDES data link layers 102 in Part I circuit 100 are by the internal memory from on-chip bus 103
Manipulation of data stream (shown in line 16), the data flow 18 used by various DACs, ADCs, and from high-speed interface application layer 105
Data flow 11 carry out data fusion, while the data flow after combination of management, and set up and guarantee that data flow sends, receives and weighs
The mechanism of sending out；First general SERDES data link layers 102 are exactly used for realizing the unified data flow mechanism that first is general
SERDES data link layers 102 are connected to a SERDES interfaces 101 by connecting path 10.
Part II circuit 200 can also include：High speed interface protocol layer 204, digital interface 205, association's processing unit
206th, physical layer（PHYs）207th, ADCs and DACs208, audio frequency and video phaselocked loop 209.Similarly, above-mentioned modules are generality
Illustrate, the similar a certain generic module of representative feature or characteristic does not represent a certain concrete module or equipment, the company between each module
Connect relation and there is data flow relation between each generic module as shown in figure 1, representing.
Wherein, the digital interface 205 includes but is not limited to the digital interface of various ADC, DAC and its correlation；The physics
Layer 207 includes the protocol layer of the physical layer and correlation of various HSSI High-Speed Serial Interfaces.
Second general SERDES data link layers 202 of Part II circuit 200 are via the 2nd SERDES interfaces 201 and
First SERDES interfaces 101 of a part of circuit 201 connect, and the second general SERDES data link layers 202 are split by first
Data flow after the first general fusion of SERDES data link layers 102 of parallel circuit 100, or encapsulation uplink data.Tear open
Data after point are sent to respective high speed interface protocol layer 204, or via data path 24 via data path 25 respectively
And digital interface 205 is sent to ADCs and DACs208, or send to association's processing unit 206 via data path 23.
Wherein first general SERDES data link layers 102 and the second general SERDES data link layers 103 are symmetrical：
Can be decapsulated in Part II circuit 200 through the data flow of encapsulation in Part I circuit 100, in Part II circuit
200 data flows for passing through encapsulation can be decapsulated in Part I circuit 100.
The system phaselocked loop 109 of Part I circuit 100 is used to produce Digital Logic drive clock, and Part II circuit
200 audio frequency and video phaselocked loop 209 is used to produce the second Digital Logic drive clock.
The digital interface 205 of Part II circuit 200 produces the sequential interface that various DAC/DAC are required, and data are sent
Enter corresponding DAC or data are read in from corresponding ADC.The ADCs and DACs of Part II circuit 200 is included but is not limited to
Video DAC, audio ADC, touch screen ADC etc..
Data flow from high-speed interface application layer 105 is packed by the high speed interface protocol layer 204 of Part II circuit 200
The protocol package for meeting respective interface definition is packaged into, and sequential as requested sends into corresponding physical layer 207.Wherein, the height
Fast interface includes but is not limited to SATA, USB, PCIe interface etc..
The physical layer 207 of Part II circuit 200 includes but is not limited to SATA physical layers, USB physical layers, PCIe physics
Layer, HDMI physical layers etc..
The Memory Controller Hub and physical layer 203 of Part II circuit 200 can be the relevant controls of LPDDR, DDR1/2/3
Device and physical layer.
Association's processing unit 206 can be responsible for whole as simple issued transaction or computing unit in Part II circuit 200
The operation initialization and operation control of individual Part II circuit 200.
More specifically, Part II circuit 200 can apply for the use of rambus 2 by request for arbitration path 3
Power, accesses external memory storage 300 by rambus 2.And Part I circuit 100 can unfetteredly pass through connection line
1 accesses（Including reading and writing）Other all circuit moulds in Part II circuit 200 in addition to Memory Controller Hub and physical layer 203
Block.
In addition, Part I circuit 100 can be by applying the right to use of rambus 2 come via Part II circuit
Memory Controller Hub and physical layer 203 in 200 accesses external memory storage 300.External memory storage is accessed in Part I circuit 100
During 300, access operation and Part II circuit 200 is reached by connection line 1 first, then by the second general SERDES
Data link layer 202 isolates the data flow of operation memorizer, reaches Memory Controller Hub and physical layer via data path 21
203, external memory storage 300 can be accessed by rambus 2 then.
Second embodiment
With reference to Fig. 2, Fig. 2 shows the structured flowchart of the system level chip or device of second embodiment, with first embodiment
Similar, which is divided into two parts：Part I circuit 400 and Part II circuit 500, the two be arranged on different domains,
On nude film, chip or programming device, and connected by SERDES interfaces each other, data interaction therebetween is abided by
Follow SERDES related specifications.Wherein, Part I circuit 400 mainly includes general digital part, for example one or more
SOC digital units；Part II circuit 500 mainly includes SOC high-speed interfaces and analog portion, such as one or more SOC
Analog component.
Used as a preferred embodiment, Part I circuit 400 and Part II circuit 500 share same external storage
Device 600.External memory storage 600 can be various volatile memory, such as DDR1/2/3, LPDDR etc..
Furthermore, Part I circuit 400 can include a SERDES interfaces 401, the first general SERDES numbers
According to link layer 402 and Memory Controller Hub and physical layer 410, Part II circuit 500 includes the 2nd SERDES interfaces 501 and the
Two general SERDES data link layers 502, wherein, the first general SERDES data link layers 401 and a SERDES interfaces 402
Connection, the 2nd SERDES interfaces 501 and 401 physical connection of a SERDES interfaces, the second general SERDES data link layers 502
It is connected with the 2nd SERDES interfaces 501.First general SERDES data link layers 402 and the second general SERDES data link layers
502 upper-layer protocols that can realize SERDES interfaces.
Memory Controller Hub and physical layer（PHY）410, its SERDES data link layer general with first 402 is connected, internal memory control
Device processed and physical layer 410 can also be connected with external memory storage 600 by rambus 2.
With first embodiment similarly, Part I circuit 400 can also include on-chip bus 403, issued transaction unit
406th, computing unit 407, ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 404, high-speed interface application layer 405, storage communication digital interface
408 and system phaselocked loop 409.
Part II circuit 500 can also include：High speed interface protocol layer 504, digital interface 505, association's processing unit
506th, physical layer（PHYs）507th, ADCs and DACs508, audio frequency and video phaselocked loop 509.
The annexation and its function of above-mentioned modules refer to the associated description in first embodiment, no longer go to live in the household of one's in-laws on getting married here
State.
More specifically, Part I circuit 400 can access external memory storage 300 by rambus 2.In addition,
Part I circuit 400 unfetteredly can be accessed by connection line 1（Including reading and writing）In Part II circuit 500
All circuit modules.
In addition, Part II circuit 500 can be via the Memory Controller Hub in Part I circuit 400 and physical layer 410
Access external memory storage 600.During Part II circuit 500 accesses external memory storage 600, operation is accessed first by connecting
Link 1 reaches Part I circuit 400, then isolates operation storage by the first general SERDES data link layers 402
The data flow of device, is reached Memory Controller Hub and physical layer 410 via data path 19, can be accessed by rambus 2 then
External memory storage 600.
3rd embodiment
With reference to Fig. 3, Fig. 3 shows the structured flowchart of the system level chip or device of 3rd embodiment, with first and second
Embodiment is similar to, and which is divided into two parts：Part I circuit 700 and Part II circuit 800, the two is arranged on different
On domain, nude film, chip or programming device, and connected by ddr interface each other, data interaction therebetween
Follow DDR related specifications.Wherein, Part I circuit 700 mainly includes general digital part, for example one or more
SOC digital units；Part II circuit 800 mainly includes SOC high-speed interfaces and analog portion, such as one or more SOC
Analog component.
Used as a preferred embodiment, Part I circuit 700 and Part II circuit 800 share same external storage
Device 900.External memory storage 900 can be various volatile memory, such as DDR1/2/3, LPDDR etc..
Furthermore, Part I circuit 700 can include a DDR master controllers and physical layer 701；Part II
Circuit 800 includes：DDR is from controller 801, the 2nd DDR master controllers and physical layer 802.Wherein, DDR is from controller 801 and
One DDR master controllers and physical layer 701 are connected, and the 2nd DDR master controllers and physical layer 802 are connected from controller 801 with DDR,
2nd DDR master controllers and physical layer 802 are connected with external memory storage 900 by rambus 2.
Furthermore, Part I circuit 700 can also include on-chip bus 703, issued transaction unit 706, calculate
Unit 707, ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 704, high-speed interface application layer 705, storage communication digital interface 708, system lock
Phase ring 709.It should be noted that above-mentioned modules are generality illustrate, the similar a certain generic module of representative feature or characteristic,
A certain concrete module or equipment are not represented, the annexation between each module is as shown in figure 3, represent between each generic module
There is data flow relation.
Wherein, issued transaction unit 706 includes but is not limited to central processing unit（CPU）, digital signal processor（DSP）、
Enumerator（TIMER）, house dog（WATCHDOG）Deng.Computing unit 707 includes but is not limited to graphics calculations unit, video and calculates
Unit, encryption and decryption computing unit etc..Storage communication digital interface 708 includes but is not limited to SDMMC digital interfaces, UART numerals and connects
Mouth, SPI digital interfaces.High-speed interface application layer 705 includes but is not limited to USB interface application layer, PCIe interface application layer, SATA
Interface application layer, HDMI application layer, its input or output can be and operating system（OS）Interactive application data stream.
ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 704 includes but is not limited to the data processing module of audio frequency DAC, the number of video AD C
According to processing module, the data processing module of touch screen.The function of above-mentioned all kinds of processing modules implements can include：Video go every
The functions such as the functions such as row, scaling, post processing, the encoding and decoding of audio frequency, post processing, or the application data of touch screen processes etc..It is right
In audio frequency and video, its input or output are usually relatively simple data flow, directly can be processed by the next stage of data flow；And it is right
In other application or module, such as touch screen etc., its data flow can be directly processed by operating system.
System phaselocked loop 709 is used to produce the first Digital Logic drive clock for other in Part I circuit 100
Circuit module is used.
On-chip bus 703 can be with a DDR master controllers and physical layer 701, issued transaction unit 706, computing unit
707th, ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer 704, high-speed interface application layer 705 and storage communication digital interface 708 are connected.
Part I circuit 700 can pass through a DDR master controllers and physical layer 707, connecting path 1 and DDR from
Controller 801 is communicated with Part II circuit 800.Furthermore, the DDR master controllers in Part I circuit 700
And physical layer 701 is by the internal memory operation data flow (shown in line 12) from on-chip bus 703, used by various DACs, ADCs
Data flow 18, and data fusion is carried out from the data flow 11 of high-speed interface application layer 105, while the data after combination of management
Stream, and foundation guarantees that data flow sends, receives and retransmission mechanism.
Part II circuit 800 can also include：High speed interface protocol layer 804, digital interface 805, association's processing unit
806th, physical layer 807, ADCs and DACs808, similarly, above-mentioned modules are generality signal, representative feature or characteristic class
As a certain generic module, do not represent a certain concrete module or equipment, the annexation between each module as shown in figure 3, represent
There is data flow relation between each generic module.
Wherein, high speed interface protocol layer 804, digital interface 805, association's processing unit 806 are connected from controller 801 with DDR,
Association's processing unit 806 is also connected with the 2nd DDR master controllers and physical layer 802, physical layer 807 and high speed interface protocol layer 804
Connection, ADCs and DACs808 are connected with digital interface 805.
The digital interface 805 includes but is not limited to the digital interface of various ADC, DAC and its correlation；The physical layer 207
Including the protocol layer of the physical layer and correlation of various HSSI High-Speed Serial Interfaces.
DDR is split from controller 801 after being merged by a DDR master controllers and physical layer 701 of Part I circuit 700
Data flow, or encapsulation uplink data.Data after fractionation are sent to respective high speed via data path 25 respectively
Protocol layer of the interface 804, or send to ADCs and DACs808, or via number via data path 24 and digital interface 805
Send to association's processing unit 206 according to path 23.
The system phaselocked loop 709 of Part I circuit 700 is used to produce Digital Logic drive clock, and Part II circuit
800 audio frequency and video phaselocked loop 809 is used to produce the second Digital Logic drive clock.
The digital interface 805 of Part II circuit 800 produces the sequential interface that various DAC/DAC are required, and data are sent
Enter corresponding DAC or data are read in from corresponding ADC.The ADCs and DACs of Part II circuit 800 is included but is not limited to
Video DAC, audio ADC, touch screen ADC etc..
Data flow from high-speed interface application layer 805 is packed by the high speed interface protocol layer 804 of Part II circuit 800
The protocol package for meeting respective interface definition is packaged into, and sequential as requested sends into corresponding physical layer 807.Wherein, the height
Fast interface includes but is not limited to SATA, USB, PCIe interface etc..
The physical layer 807 of Part II circuit 800 includes but is not limited to SATA physical layers, USB physical layers, PCIe physics
Layer, HDMI physical layers etc..
Association's processing unit 806 can be responsible for whole as simple issued transaction or computing unit in Part II circuit 800
The operation initialization and operation control of individual Part II circuit 800.
More specifically, Part I circuit 700 can apply for the use of rambus 2 by request for arbitration path 3
Power, accesses external memory storage 900 by rambus 2.In addition, Part I circuit 700 can unfetteredly by connection
Path 1 is accessed（Including reading and writing）All circuit modules in Part II circuit 800.
In addition, Part I circuit 700 can be by applying the right to use of rambus 2 come via Part II circuit
DDR in 800 accesses external memory storage 900 from controller 801 and the 2nd DDR master controllers and physical layer 802.Second
During partial circuit 800 accesses external memory storage 900, access operation and Part II circuit is reached by connecting path 1 first
800, the 2nd DDR master controllers and physical layer 802 are reached from controller 801 by DDR then, rambus can be passed through then
2 access external memory storage 900.
In addition, the present embodiment additionally provides a kind of system-Level IC Design method, comprise the steps：By each circuit mould
Block is divided into Part I circuit and Part II circuit, and the Part I circuit includes one or more SOC digital units,
The Part II circuit includes one or more SOC analog components；The Part I circuit and Part II circuit are set
Put on different domains, nude film, chip or programming device, lead between the Part I circuit and Part II circuit
Communication interface connection is crossed, the communication interface is preferably the high-speed interfaces such as SERDES interfaces, ddr interface.
In manufacturing process or comparatively wherein, dependency degree is higher for Part I circuit absolute dependence, and Part II
Circuit is relatively lower to the dependency degree of manufacturing process.Part I circuit mainly includes various digital units, but while can also
The analog component of the digital unit depended in Part I circuit is arranged in Part I circuit；Part II circuit master
Various analog components are included, but while the digital unit of the analog component depended in Part II circuit can also be arranged
In Part II circuit.
Low-risk, low cost when the primary concern point of above-mentioned SOC design method is the upgrading of chip, and tradition SOC
To consider be a little integrated level.Above-mentioned SOC design method is by the modules or equipment of SOC according to the journey for depending on manufacturing process
The different demarcation of degree is two parts：Part I circuit and Part II circuit.
Wherein Part I circuit does not generally rely on concrete manufacturing process to a certain extent, generally can be describing language
The form of speech（Such as RTL）Occur, the domain of manufacture is formed after synthesis, placement-and-routing, the change of technique, upgrading are designed to which
Affect little；And for third party authorizes IP, will not also produce extra-pay.
Part II circuit is generally largely dependent upon concrete manufacturing process, it will usually directly in the form of domain
Provide design, the change of technique, upgrading, the impact designed to which is all huge；For third party authorizes IP, need to obtain again
Must authorize, these designs or mandate expense are huge, also bring flow risk in addition therewith.
It should be noted that the division of Part I circuit and second circuit can be finely adjusted according to the realization of function,
For example in Part I circuit, it is also possible to including necessary analog module, can such as produce the first Digital Logic drive clock
System PLL, connect the general SERDES data link layers of Part I circuit and Part II circuit, and in Part II electricity
Lu Zhong, it is possibility to have various necessary digital modules.The analog component that is present in Part I circuit and it is present in second
Digital unit in partial circuit, its purpose is to make the function of the respective part being located more independent, rather than makes respective institute
Function in part is more comprehensive.
To sum up, had the advantage that using the system level chip or device and its method for designing of the present invention：By by tradition
SOC is divided into Part I circuit and Part II circuit so that the cost and flow risk of two parts circuit is controllable, makes
SOC is obtained when process node changes, upgrades, quick time to market (TTM) can be exchanged for the cost and risk cost of very little.
It is to be understood that above-described embodiment is the description of the invention, rather than limitation of the present invention, it is any
Without departing from the innovation and creation in the range of true spirit, change including but not limited to local structure, to components and parts
The replacement of type or model, and the replacement or modification of other unsubstantialities, each fall within the scope of the present invention.
Claims (23)
1. a kind of system level chip, it is characterised in that including Part I circuit and Part II circuit, wherein,
The Part I circuit includes one or more SOC digital units；
The Part II circuit includes one or more SOC analog components；
The Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device,
Connected by communication interface between the Part I circuit and Part II circuit,
Wherein, the Part I circuit and Part II circuit share same external memory storage；
Wherein, the communication interface is SERDES interfaces,
The Part I circuit includes：
First SERDES interfaces；
First general SERDES data link layers, are connected with a SERDES interfaces；
The Part II circuit includes：
2nd SERDES interfaces, are connected with a SERDES interface physicals；
Second general SERDES data link layers, are connected with the 2nd SERDES interfaces；
Memory Controller Hub and physical layer, SERDES data link layers general with described second are connected, the Part II circuit Jing
It is connected with the external memory storage by rambus；
Wherein, the right to use of the Part I circuit by the application rambus, via the described first general SERDES
Data link layer, a SERDES interfaces, the 2nd SERDES interfaces, the second general SERDES data link layers, Memory Controller Hub
And physical layer and rambus access the external memory storage；The Part II circuit is by applying for the rambus
The right to use, accesses the external memory storage via the Memory Controller Hub and physical layer and rambus.
2. a kind of system level chip, it is characterised in that including Part I circuit and Part II circuit, wherein,
The Part I circuit includes one or more SOC digital units；
The Part II circuit includes one or more SOC analog components；
The Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device,
Connected by communication interface between the Part I circuit and Part II circuit,
Wherein, the Part I circuit and Part II circuit share same external memory storage；
Wherein, the communication interface is SERDES interfaces,
The Part I circuit includes：
First SERDES interfaces；
First general SERDES data link layers, are connected with a SERDES interfaces；
Memory Controller Hub and physical layer, SERDES data link layers general with described first are connected, the Part I circuit Jing
It is connected with the external memory storage by rambus；
The Part II circuit includes：
2nd SERDES interfaces, are connected with a SERDES interface physicals；
Second general SERDES data link layers, are connected with the 2nd SERDES interfaces；
Wherein, the Part I circuit accesses the external memory storage via the rambus；The Part II circuit
Via the described second general SERDES data link layers, the 2nd SERDES interfaces, a SERDES interfaces, the first general SERDES
Data link layer and Memory Controller Hub and physical layer and the rambus access external memory storage.
3. system level chip according to claim 1 and 2, it is characterised in that the Part I circuit also includes：
On-chip bus, SERDES data link layers general with described first are connected；
Issued transaction unit and computing unit, are connected with the on-chip bus, and the issued transaction unit and computing unit are via institute
State on-chip bus, the first general SERDES data link layers and Part II circuit described in a SERDES interface accessings.
4. system level chip according to claim 3, it is characterised in that the issued transaction unit includes central process
Device, digital signal processor, enumerator and/or house dog, the computing unit include：Graphics calculations unit, video calculate single
Unit and/or encryption and decryption computing unit.
5. system level chip according to claim 3, it is characterised in that the Part I circuit also includes circuits below
One or more in module：
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layers, SERDES data link layers general with described first are connected and on-chip bus are connected：
High-speed interface application layer, SERDES data link layers general with described first and on-chip bus are connected；
Storage communication digital interface, is connected with the on-chip bus；
System phaselocked loop, produces the first Digital Logic drive clock so that other circuit modules in the Part I circuit make
With.
6. system level chip according to claim 5, it is characterised in that the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer includes
The data processing module of the data processing module of audio frequency DAC, the data processing module of video AD C and/or touch screen；The high speed
Interface application layer includes USB interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI application layer；
The storage communication digital interface includes SDMMC digital interfaces, UART digital interfaces and/or SPI digital interfaces.
7. system level chip according to claim 5, it is characterised in that the first general SERDES data link layers will
Data flow, the data flow of the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer from the on-chip bus and connect from the high speed
The data flow of mouth application layer carries out data fusion, the data flow after combination of management, and sets up data flow transmission, receives and retransmit
Mechanism.
8. system level chip according to claim 1 and 2, it is characterised in that the Part II circuit also includes following
One or more in circuit module：
High speed interface protocol layer, SERDES data link layers general with described second are connected；
Digital interface, SERDES data link layers general with described second are connected；
Association's processing unit, SERDES data link layers general with described second are connected；
Physical layer, is connected with the high speed interface protocol layer；
ADCs and DACs, is connected with the digital interface；
Audio frequency and video phaselocked loop, produces the second Digital Logic drive clock for other circuit modules in the Part II circuit
Use.
9. system level chip according to claim 8, it is characterised in that the high speed interface protocol layer will be connect from high speed
The data flow packing of mouthful application layer is packaged into the protocol package that meets interface definition and sends to the physical layer；The digital interface
The sequential interface of the ADCs and DACs is produced, and is sent data to corresponding DACs or data is read from corresponding ADCs
Enter；The physical layer includes SATA physical layers, USB physical layers, PCIe physical layer and/or HDMI physical layers；The association processes single
Operation initialization and operation control of the unit for the Part II circuit.
10. system level chip according to claim 8, it is characterised in that the second general SERDES data link layers
Split by the data flow or encapsulation uplink data after the described first general SERDES data link layers fusion, wherein, tear open
Data flow after point is respectively sent to the high speed interface protocol layer, ADCs and DACs or association's processing unit.
11. system level chips according to claim 1 and 2, it is characterised in that a SERDES interfaces and second
SERDES interfaces include string simultaneously/and go here and there device, transmitting-receiving FIFO, receiving data align unit, timer manager, transmitting-receiving line interface,
Line codec and/or passage binding part.
12. a kind of system level chips, it is characterised in that including Part I circuit and Part II circuit, wherein,
The Part I circuit includes one or more SOC digital units；
The Part II circuit includes one or more SOC analog components；
The Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device,
Connected by communication interface between the Part I circuit and Part II circuit,
Wherein, the Part I circuit and Part II circuit share same external memory storage；
Wherein, the communication interface is ddr interface, and the Part I circuit includes：
First DDR master controllers and physical layer；
The Part II circuit includes：
DDR is connected from controller with a DDR master controllers and physical layer；
2nd DDR master controllers and physical layer, are connected from controller with the DDR, the DDR master controllers and physical layer via
Rambus are connected with external memory storage；
Wherein, the right to use of the Part I circuit by the application rambus, via a DDR master controllers
And physical layer, DDR access the external memory storage from controller, the 2nd DDR master controllers and physical layer and rambus；Institute
Part II circuit is stated by applying for the right to use of the rambus, via the 2nd DDR master controllers and physical layer and
Rambus access the external memory storage.
13. system level chips according to claim 12, it is characterised in that the Part I circuit also includes：
On-chip bus, are connected with a DDR master controllers and physical layer；
Issued transaction unit and computing unit, are connected with the on-chip bus, and the issued transaction unit and computing unit are via institute
State on-chip bus and a DDR master controllers and physical layer interface accesses the Part II circuit.
14. system level chips according to claim 13, it is characterised in that the issued transaction unit includes central process
Device, digital signal processor, enumerator and/or house dog, the computing unit include：Graphics calculations unit, video calculate single
Unit and/or encryption and decryption computing unit.
15. system level chips according to claim 13, it is characterised in that the Part I circuit also includes following electricity
One or more in the module of road：
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layers, are connected with the on-chip bus and a DDR master controllers and physical layer：
High-speed interface application layer, is connected with the on-chip bus and a DDR master controllers and physical layer；
Storage communication digital interface, is connected with the on-chip bus；
System phaselocked loop, produces the first Digital Logic drive clock so that other circuit modules in the Part I circuit make
With.
16. system level chips according to claim 15, it is characterised in that the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer bag
Include the data processing module of the data processing module of audio frequency DAC, the data processing module of video AD C and/or touch screen；The height
Fast interface application layer includes USB interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI application
Layer；The storage communication digital interface includes SDMMC digital interfaces, UART digital interfaces and/or SPI digital interfaces.
17. system level chips according to claim 15, it is characterised in that a DDR master controllers and physical layer
By the data flow from the on-chip bus, the data flow of the ADCs/DACs Apple talk Data Stream Protocol Apple Tas layer and from the high speed
The data flow of interface application layer carries out data fusion, the data flow after combination of management, and sets up data flow transmission, receives and weigh
The mechanism of sending out.
18. system level chips according to claim 12, it is characterised in that the Part II circuit also includes following electricity
One or more in the module of road：
High speed interface protocol layer, is connected from controller with the DDR；
Digital interface, is connected from controller with the DDR；
Association's processing unit, is connected from controller with the DDR；
Physical layer, is connected with the high speed interface protocol layer；
ADCs and DACs, is connected with the digital interface；
Audio frequency and video phaselocked loop, produces the second Digital Logic drive clock for other circuit modules in the Part II circuit
Use.
19. system level chips according to claim 18, it is characterised in that the high speed interface protocol layer will be from a high speed
The data flow packing of interface application layer is packaged into the protocol package that meets interface definition and sends to the physical layer；The numeral connects
Mouthful produce the sequential interface of the ADCs and DACs, and send data to corresponding DACs or from corresponding ADCs by data
Read in；The physical layer includes SATA physical layers, USB physical layers, PCIe physical layer and/or HDMI physical layers；The association is processed
Unit is used for the operation initialization of the Part II circuit and runs control.
20. system level chips according to claim 18, it is characterised in that the DDR is split by described the from controller
Data flow or encapsulation uplink data after one DDR master controllers and physical layer fusion, wherein, the data flow quilt after fractionation
It is respectively sent at the 2nd DDR master controllers and physical layer, high speed interface protocol layer, ADCs and DACs or the association
Reason unit.
A kind of 21. system-Level IC Design methods, it is characterised in that the system level chip is such as any one of claim 1-20
Described system level chip, the system-Level IC Design method include：
Each circuit module is divided into into Part I circuit and Part II circuit, the Part I circuit include one or
Multiple SOC digital units, the Part II circuit include one or more SOC analog components；
The Part I circuit and Part II circuit are arranged on into different domains, nude film, chip or programming device
On, connected by communication interface between the Part I circuit and Part II circuit.
22. system-Level IC Design methods according to claim 21, it is characterised in that the Part I circuit and
Two partial circuits share same external memory storage.
23. system-Level IC Design methods according to claim 21, it is characterised in that the communication interface is SERDES
Interface or ddr interface.
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| US10573598B2 (en) * | 2017-09-28 | 2020-02-25 | Xilinx, Inc. | Integration of a programmable device and a processing system in an integrated circuit package |
| CN110609805B (en) * | 2018-06-14 | 2024-04-12 | 格科微电子（上海）有限公司 | Method for realizing system-on-chip |
| CN113675811A (en) * | 2020-05-14 | 2021-11-19 | 国网福建省电力有限公司电力科学研究院 | CPU plug-in and relay protection device based on SOC chip |
| CN112988248B (en) * | 2021-03-09 | 2023-03-31 | 南昌黑鲨科技有限公司 | Computer readable storage medium and method for starting intelligent terminal operating system from multiple storage media |
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