CN107484344A - PCB layout methods based on acp chip PIN - Google Patents
PCB layout methods based on acp chip PIN Download PDFInfo
- Publication number
- CN107484344A CN107484344A CN201710763371.9A CN201710763371A CN107484344A CN 107484344 A CN107484344 A CN 107484344A CN 201710763371 A CN201710763371 A CN 201710763371A CN 107484344 A CN107484344 A CN 107484344A
- Authority
- CN
- China
- Prior art keywords
- pcb
- chip
- acp chip
- acp
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of PCB layout methods based on acp chip PIN, comprise the steps of：1) acp chip in PCB design, is determined；2) function confirmation, is carried out to the PIN of acp chip；3) functional regional division, is carried out by function to the PIN of acp chip；4), according to the division of the functional area of acp chip, functional circuit unit corresponding to the periphery supplement in the corresponding functional area of acp chip；5), according to whole PCB power supply requirement and power connector position, while consider whole PCB thermal balance, determine the placement of power supply chip；6), according to whole PCB clock service condition, the placement of clock chip is determined.The PCB layout methods disclosure satisfy that the efficient fast layout demand to all types PCB, be particularly suitable for the layout of the PCB to the acp chips of SOC containing high integration.
Description
Technical field
Patent of the present invention belongs to electronic engineering field, is related to PCB topology.
Background technology
PCB (Printed Circuit Board), Chinese is printed circuit board, is important electronic unit, is electricity
The supporter of sub- component, PCB will undergo strict design before manufacture, and PCB design is divided into " layout " and " wiring " two
The individual stage, so-called " layout " be exactly by principle design used in all components laid on PCB, lay including
Determination, the consideration in component direction of component locations, prepared for follow-up " wiring ".
Traditional " layout " method includes autoplacement and manual layout, and autoplacement is that all PCB design instruments all have
A basic function having, it is placed according to the strategy, rule, the constrained procedure that are carried in PCB design instrument to component,
So that PCB design personnel refer to, here is the citing of these policing rules：
A) all components all should be arranged in PCB the same face, could be by some height only when top layer element is overstocked
Limited and small caloric value device, such as Chip-R, patch capacitor are placed on bottom.
B) component should be placed on grid and be parallel to each other and be arranged vertically, in the hope of it is neat, attractive in appearance, do not allow component
Overlapping, component arrangement is compact, and input and output component are as far as possible remote.
C) it is located at the component of edges of boards edge, is at least kept with a distance from 2 thicknesss of slab from edges of boards edge.
D) component should be evenly distributed on whole PCB, density it is consistent.
Manual layout is then that PCB design personnel carry out laying operation manually to component, can be with reference to autoplacement
On the basis of carry out or full manual layout, manual layout typically using based on signal stream trend layout method, specifically
Have：
A) position of each functional circuit unit is arranged one by one according to the flow of signal, with the core member of each functional circuit
Centered on part, it is laid out around it.
B) layout of component should be easy to signal to circulate, the direction for making signal be consistent as far as possible, such as from left to right or
From top to bottom, the component being joined directly together with input, output end should be placed on close to the ground of input, output connector or connector
Side.
Although autoplacement and the manual layout based on signal stream trend are the first choices of current PCB layout methods, this two
Kind of layout method can not meet the application demand of many occasions, such as the rule constraint of autoplacement is too general, and simple PCB is adopted
With manually adjustment can realize PCB final layout after autoplacement, and complicated PCB is past using the result of autoplacement
It is past disorderly and unsystematic, have no reference value for follow-up manual layout；Manual layout based on signal stream trend can realize letter
The optimal transmission paths of number stream, but it is less convenient on the position arrangement of each functional circuit unit, for whole PCB heat
It is also inconvenient that balance considers, often can repeatedly be changed to obtain a good PCB layout, spend longer time.
The content of the invention
The goal of the invention of the present invention is to give a kind of PCB layout methods based on acp chip PIN, such as Fig. 1 institutes
Show, the PCB layout methods disclosure satisfy that the efficient fast layout demand to all types PCB, be particularly suitable for containing highly integrated
Spend the PCB of SOC acp chips layout.
The goal of the invention of the present invention is achieved through the following technical solutions：
A kind of PCB layout methods based on acp chip PIN, are comprised the steps of：
Step 1), determine acp chip in PCB design；
Step 2), each PIN to acp chip carry out function confirmation；
Step 3), the PIN to acp chip carry out functional regional division by function；
Step 4), the division according to the functional area of acp chip, on the periphery of the corresponding functional area of acp chip
Functional circuit unit corresponding to supplement；
Step 5), the power supply requirement according to whole PCB and power connector position, while consider whole PCB thermal balance,
Determine the placement of power supply chip；
Step 6), the clock service condition according to whole PCB, determine the placement of clock chip.
Preferably, the method for determining the acp chip in PCB design is：The institute that will be used according to schematic diagram in PCB design
There is component to imported into PCB design interface and PCB framework is primarily determined that using Interactive Design method, flown in PCB
Line and BOM inventories draw the acp chip in the PCB design.
Preferably, the principle for determining the placement of power supply chip is：Supply voltage is disperseed using position, then corresponding power
Chip is placed close to input source；Supply voltage is concentrated using position, then corresponding power chip is placed close to output destination end.
Preferably, the placement of clock chip uses nearby principle.
Further, the PCB layout methods based on acp chip PIN also include：
Step 7)：Comprehensive each functional circuit unit, power supply chip, the position of clock chip, to functional circuit unit, power supply
Chip, the relative position of clock chip carry out local directed complete set.
Step 8)：Situation about being connected according to component after layout with input, output signal, readjust input, output
Signal distribution on connector.
The advantages of PCB layout methods based on acp chip PIN is that operation is clear, simple efficient, exhaustive, it with
Centered on acp chip, by the region division of acp chip itself function PIN, using nearby principle radially by peripheral work(
Energy circuit unit adds to the surrounding of acp chip, as shown in Fig. 2 the thermal balance of whole plate is considered simultaneously, by the big device of power consumption
Spread out, the signal on input and output connector is suitably adjusted as far as possible finally, this is to be based on acp chip PIN
PCB layout all operations.
With the continuous development of microelectric technique and the continuous progress of integrated circuit technology, the volume of chip is less and less,
Integrated level more and more higher, the function of realization is more and more, and many chips are a SOC in itself at present, thus when realize it is some both
When fixed operation or complex task, all it is around single SOC expansion and in the functional circuit unit needed for surrounding increase, has been come with this
Into the drafting of schematic diagram, PCB and schematic diagram are inseparable entirety again, and it is specific implementation of the schematic diagram in engineering, base
Thought is realized in the PCB layout method similar principles figures of acp chip PIN, it is by PCB layout thinking with schematic diagram
Implementation method perfect unity, improve the efficiency and reliability of engineering design.
Brief description of the drawings
PCB layout method flow charts of the Fig. 1 based on acp chip PIN
The structural representation of PCB shown in Fig. 2 embodiments；
Fig. 3 is the schematic diagram of the fly line in PCB；
Fig. 4 is XC7Z045-2FFG900I I/O Banks；
Fig. 5 XC7Z045-2FFG900I functional block division schematic diagram
Fig. 6 central processing modules power supply generates schematic diagram；
The PCB layouts of Fig. 7 central processing modules；
The thermograph of Fig. 8 central processing modules.
Embodiment
The embodiment of the present invention proposes a kind of PCB layout methods based on acp chip PIN, and it compensate for traditional PCB
The deficiency of layout method, the specific embodiment of the present invention is provided by taking the PCB construction that Fig. 2 is provided as an example below.
Assuming that the schematic diagram of certain central processing module (CPM) engineering design has been drawn and finished, next it is in the principle
PCB layout operations are carried out on the basis of figure, as shown in figure 1, operating procedure given below：
The first step：It is determined that the acp chip in design.
By schematic diagram by this design in all components for using imported into PCB design interface and use Interactive Design
Method primarily determines that PCB framework, and as shown in Figure 3, fly line and BOM inventories in PCB can draw the core in the design
Chip centroid is XC7Z045-2FFG900I, and it is a SoC chip of XILINX companies development ＆ production.
Second step：Function confirmation is carried out to each PIN of acp chip.
XC7Z045-2FFG900I is a large-scale chip bga, 900 PINs is shared, according to XILINX companies
The handbook of offer, from function division on can be divided into Bank9, Bank10, Bank11, Bank12, Bank13, Bank33, Bank34,
Bank35, Bank109, Bank110, Bank111, Bank112, Bank500, Bank501, Bank502 totally 15 I/O
Banks, as shown in Figure 4.Including memory interface, Ethernet interface, UART serial line interfaces, Serdes interfaces, power interface, when
Clock interface etc..
3rd step：Position division is carried out by function to the PIN of acp chip.
Position pair of the PIN in chip package according to corresponding to each functional units of XC7Z045-2FFG900I
XC7Z045-2FFG900I carries out region division, as shown in figure 5, XC7Z045-2FFG900I is divided into 9 functional blocks, PS
(Processing System)-DDR functional blocks, PL (Programmable Logic)-DDR functional blocks, Flash functional blocks,
PS-UART functional blocks, PL-UART functional blocks, Ethernet functional blocks, LocalBus functional blocks, Serdes functional blocks, audio frequency and video
Functional block.
4th step：According to the functional regional division of acp chip, functional circuit corresponding to the surrounding supplement in acp chip
Unit.
According to XC7Z045-2FFG900I functional regional division, the functional circuit unit in combination principle figure designs,
Device corresponding to XC7Z045-2FFG900I surrounding layout：
√ PS (Processing System)-DDR functional circuits：The functional circuit unit includes two panels DDR3 SDRAM
Chip MT41J128M16HA-125IT and subsidiary resistance capacitance, two panels DDR3 SDRAM use the same PS- of form of daisy chain
DDR controller is connected；
√ PL (Programmable Logic)-DDR functional circuits：The functional circuit unit by two panels independence DDR3
SDRAM chips MT41J128M16HA-125IT and subsidiary resistance capacitance are formed, and every DDR3 SDRAM is connected to corresponding
Independently used on PL-DDR controllers；
√ Flash functional circuits：The functional circuit unit by two panels independence SPI FLASH chips
S25FL128SAGMFIR01 and subsidiary resistance capacitance are formed, and every SPI FLASH is connected on corresponding QSPI interfaces；
√ PS-UART functional circuits：The functional circuit unit is by a piece of RS232 transceiving chips MAX3386EEUP and attaches
Resistance capacitance form, MAX3386EEUP is directly connected on PS-UART controllers；
√ PL-UART functional circuits：The functional circuit unit realizes two-way RS485 communication functions and two-way HDLC communication work(
Can, the same external communication of PL-UART controllers is realized by MAX3485EESA chips, wherein two-way RS485 communications need two panels
MAX3485EESA, two-way HDLC communication need four MAX3485EESA；
√ Ethernet functional circuits：The functional circuit unit realizes ethernet communication function all the way, by an Ethernet
Receive and dispatch PHY chip 88E1116RA0-NNC1C000, an Ethernet transformer chip HX5008NL and subsidiary resistance capacitance magnetic
Pearl inductance is formed, and 88E1116RA0-NNC1C000 is directly connected on PS ethernet controllers；
√ LocalBus functional circuits：The functional circuit unit is by a piece of NVRAM chips FM22L16-55-TG and a piece of
CPLD chips XC2C256-7VQ100I is formed, and two kinds of chips share LocalBus, and the company of signal is realized using chrysanthemum chain pattern
Connect；
√ Serdes functional circuits：The functional circuit unit realizes the transmission of high-speed serial bus signal, in MGT interfaces and
The transmission of the bus signals of two-way SATA buses and 1 road PCIe × 4 is completed between aerial lug；
√ audio frequency and video functional circuits：The functional circuit unit realizes the reception and the simulation of 2 tunnels of 5 road S-VIDEO analog videos
Differential video, audio signal are converted into single-ended signal by the reception processing of audio, operational amplifier chip AD813ARZ-14,5
The S-VIDEO videos received are converted into the digital video signal of BT.656YCbCr forms by video coding chip GM7150A, and 1
Simulated audio signal is converted into I2S data signals by TLV320AIC23BIPW chips.
5th step：According to the power supply requirement of whole plate and power connector position, while the thermal balance of whole plate is considered, it is determined that electric
The placement of source chip.The principle of the placement of power supply chip is：Supply voltage is disperseed using position, then corresponding power core
Piece is placed close to input source；Supply voltage is concentrated using position, then corresponding power chip is placed close to output destination end.Simultaneously
Consider thermal balance, multiple power supply chip suggestions are scattered to place.
CPM external input power is VCC5.0V, is converted into a variety of secondary power supplies by the power supply chip on plate, has
VCC1.0V, VCC3.3V, VCC1.5V, VCC1.8V, AVCC1.0V, AVCC1.2V, VTT0.75V, as shown in fig. 6, considering following
Several factors：
√ power input connectors are in the CPM lower right corner；
Big power consuming devices on √ CPM have：Acp chip XC7Z045-2FFG900I, power supply chip LTM4616IV#PBF,
TPS74401RGWT、TPS51200DRC；
The input power of √ two panels LTM4616IV#PBF chips is total input power VCC5.0V；
Inputs of the √ VCC3.3V as 18 chips, inputs of the VCC1.5V as 6 chips, VCC1.8V conducts
The input of 13 chips, these three voltage's distribiutings are relatively scattered；
√ AVCC1.0V, AVCC1.2V, VTT0.75V are produced by independent power supply chip, and use range is concentrated.
The placement of each power supply chip can be determined, i.e. two panels LTM4616IV#PBF chips connect close to power input
Device is placed, and two panels TPS74401RGWT chips are placed close to XC7Z045-2FFG900I Serdes functional blocks, a piece of
TPS51200DRC chips are placed close to PS-DDR functional blocks.
6th step：According to the clock service condition of whole plate, the placement of clock chip is determined, general use is former nearby
Then.
A variety of crystal oscillators are used on CPM, for producing required various clock signals, including 1 33.333MHz crystal oscillators, 5
Individual 14.31818MHz crystal oscillators, 2 25MHz crystal oscillators, 1 100MHz difference crystal oscillator, 1 150MHz difference crystal oscillator, according to schematic diagram
Design, these crystal oscillators is positioned as close to their objective chip, reduces the length of clock line, while with due regard to phase vincial faces
The spacing shaken, keep suitable distance.
7th step：Comprehensive each functional circuit unit, power supply chip, the position of clock chip, enter to their relative position
Row local directed complete set.
Complete the first six step, it may be said that CPM PCB layouts are basically completed, and the 7th step is on the basis of the first six step
Local uniqueness is carried out, is such as uniformly distributed the device of whole plate, the device position from the equal function of the convenient angle adjustment of wiring.
8th step：Situation about being connected according to component after layout with input, output signal, readjust input, output
Signal distribution on connector.
The first seven step is completed, CPM PCB layouts then 100% complete, and the 8th step can be described as one to schematic diagram
Individual reversely change, is mainly adjusted so that signal on connector to the road of each functional chip to the signal on connector
Footpath is most short, as SATA buses and PCIe bus signals are all connected in XC7Z045-2FFG900I Serdes functional blocks, and
Serdes functional blocks are in CPM lower left, then SATA buses and PCIe bus signals are just adjusted to the connector of CPM lower lefts
On, it can make it that transmission path is most short.
The CPM completed according to the PCB layout methods based on acp chip PIN PCB is laid out as shown in Figure 7, finally
The thermograph that CPM works on power is as shown in Figure 8.
PCB layout methods based on acp chip PIN can be completed in a relatively short time a complicated circuit design
PCB layouts, operation is clear, it is simple efficiently, be not in multiple design adjustment repeatedly；The PCB completed with this method is laid out
Preparation has been done for follow-up PCB wiring so that PCB wiring more becomes normative and reasonable；The layout method of the PCB is by the warm of whole plate
Balance takes into account, and avoids the heat of whole plate because concentration of local causes reliability to reduce, improve product success rate and
Reliability, so as to also shorten the development cost and Time To Market of product indirectly.PCB layout sides based on acp chip PIN
Method is applied to all PCB design instruments, and generalization is extremely strong, it will has wide market to use space and significant economic benefit.
Claims (6)
1. a kind of PCB layout methods based on acp chip PIN, are comprised the steps of：
Step 1), determine acp chip in PCB design；
Step 2), each PIN to acp chip carry out function confirmation；
Step 3), the PIN to acp chip carry out functional regional division by function；
Step 4), the division according to the functional area of acp chip, in the periphery supplement of the corresponding functional area of acp chip
Corresponding functional circuit unit；
Step 5), the power supply requirement according to whole PCB and power connector position, while consider whole PCB thermal balance, it is determined that
The placement of power supply chip；
Step 6), the clock service condition according to whole PCB, determine the placement of clock chip.
2. the PCB layout methods according to claim 1 based on acp chip PIN, it is characterised in that determine PCB design
In the method for acp chip be：All components used in PCB design are imported into simultaneously by PCB design interface according to schematic diagram
PCB framework is primarily determined that using Interactive Design method, the fly line and BOM inventories in PCB are drawn in the PCB design
Acp chip.
3. the PCB layout methods according to claim 1 based on acp chip PIN, it is characterised in that determine power supply core
The principle of the placement of piece is：Supply voltage is disperseed using position, then corresponding power chip is placed close to input source；Power supply
Voltage is concentrated using position, then corresponding power chip is placed close to output destination end.
4. the PCB layout methods according to claim 1 based on acp chip PIN, it is characterised in that clock chip
Placement uses nearby principle.
5. the PCB layout methods according to claim 1 based on acp chip PIN, it is characterised in that also include：
Step 7)：Comprehensive each functional circuit unit, power supply chip, the position of clock chip, to functional circuit unit, power supply core
Piece, the relative position of clock chip carry out local directed complete set.
6. the PCB layout methods according to claim 5 based on acp chip PIN, it is characterised in that also include：
Step 8)：Situation about being connected according to component after layout with input, output signal, readjust input, output connection
Signal distribution on device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710763371.9A CN107484344B (en) | 2017-08-30 | 2017-08-30 | PCB layout method based on core chips PIN foot |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710763371.9A CN107484344B (en) | 2017-08-30 | 2017-08-30 | PCB layout method based on core chips PIN foot |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107484344A true CN107484344A (en) | 2017-12-15 |
| CN107484344B CN107484344B (en) | 2019-10-01 |
Family
ID=60604102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710763371.9A Active CN107484344B (en) | 2017-08-30 | 2017-08-30 | PCB layout method based on core chips PIN foot |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107484344B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109858092A (en) * | 2018-12-27 | 2019-06-07 | 遵义市水世界科技有限公司 | Method, apparatus, computer equipment and the storage medium of PCB component placement |
| CN110113874A (en) * | 2019-05-27 | 2019-08-09 | 杭州迪普科技股份有限公司 | PCB component and preparation method thereof |
| WO2019242784A1 (en) * | 2018-06-22 | 2019-12-26 | 北京比特大陆科技有限公司 | Multi-node chip connection system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101539955A (en) * | 2008-03-20 | 2009-09-23 | 英业达股份有限公司 | Layout method for circuit design |
| CN101639870A (en) * | 2009-05-19 | 2010-02-03 | 上海闻泰电子科技有限公司 | Method for introducing PCB design document from schematic diagram |
| CN203151866U (en) * | 2013-03-26 | 2013-08-21 | 深圳金塔科技有限公司 | PCB board for LED perpetual calendar |
| US9008981B2 (en) * | 2008-03-25 | 2015-04-14 | Nec Corporation | Apparatus, method and program for design validity verification of electronic circuit board with regard to power supply noise suppression |
| CN204539606U (en) * | 2014-12-26 | 2015-08-05 | 睿能科技(北京)有限公司 | A kind of high-speed digital video camera circuit board |
| CN105653765A (en) * | 2015-12-23 | 2016-06-08 | 无锡江南计算技术研究所 | Four-side layout method of multi-phase VRM (Voltage Regulator Module) power circuit |
| CN105653744A (en) * | 2014-11-13 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Method and device for designing layout |
-
2017
- 2017-08-30 CN CN201710763371.9A patent/CN107484344B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101539955A (en) * | 2008-03-20 | 2009-09-23 | 英业达股份有限公司 | Layout method for circuit design |
| US9008981B2 (en) * | 2008-03-25 | 2015-04-14 | Nec Corporation | Apparatus, method and program for design validity verification of electronic circuit board with regard to power supply noise suppression |
| CN101639870A (en) * | 2009-05-19 | 2010-02-03 | 上海闻泰电子科技有限公司 | Method for introducing PCB design document from schematic diagram |
| CN203151866U (en) * | 2013-03-26 | 2013-08-21 | 深圳金塔科技有限公司 | PCB board for LED perpetual calendar |
| CN105653744A (en) * | 2014-11-13 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Method and device for designing layout |
| CN204539606U (en) * | 2014-12-26 | 2015-08-05 | 睿能科技(北京)有限公司 | A kind of high-speed digital video camera circuit board |
| CN105653765A (en) * | 2015-12-23 | 2016-06-08 | 无锡江南计算技术研究所 | Four-side layout method of multi-phase VRM (Voltage Regulator Module) power circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019242784A1 (en) * | 2018-06-22 | 2019-12-26 | 北京比特大陆科技有限公司 | Multi-node chip connection system |
| CN110636694A (en) * | 2018-06-22 | 2019-12-31 | 北京比特大陆科技有限公司 | Multi-node chip connecting system |
| CN110636694B (en) * | 2018-06-22 | 2022-09-30 | 北京比特大陆科技有限公司 | Multi-node chip connecting system |
| CN109858092A (en) * | 2018-12-27 | 2019-06-07 | 遵义市水世界科技有限公司 | Method, apparatus, computer equipment and the storage medium of PCB component placement |
| CN109858092B (en) * | 2018-12-27 | 2024-01-30 | 深圳市沃特沃德信息有限公司 | Method and device for PCB element layout, computer equipment and storage medium |
| CN110113874A (en) * | 2019-05-27 | 2019-08-09 | 杭州迪普科技股份有限公司 | PCB component and preparation method thereof |
| CN110113874B (en) * | 2019-05-27 | 2020-07-07 | 杭州迪普科技股份有限公司 | PCB component and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107484344B (en) | 2019-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107484344A (en) | PCB layout methods based on acp chip PIN | |
| CN102789512B (en) | Method and device for design of electronic design automation (EDA) tool of multi-field programmable gate array (FPGA) system | |
| CN207976832U (en) | Power supply circuit, circuit board with level conversion unit and virtual digit coin dig mine machine | |
| CN107153622B (en) | A kind of drive control method based on spi bus | |
| CN107908586A (en) | A kind of NVME hard-disc storages structure and its implementation | |
| US20130304961A1 (en) | Hub control chip | |
| CN107315448A (en) | A kind of Clock management architecture design method of low-Power Multicore SoC | |
| US11669664B2 (en) | System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design | |
| CN102497206A (en) | Clock control device and system-on-chip comprising same | |
| CN107209525B (en) | Capacity coupled mixing parallel connection power supply | |
| CA2704023C (en) | Reduction of jitter in a semiconductor device by controlling printed circuit board and package substrate stackup | |
| CN103678250B (en) | System level chip and its method for designing | |
| CN107490756A (en) | A kind of logic control signal system of usb bus | |
| CN116232365A (en) | High sampling rate intermediate frequency receiving and transmitting communication system based on FPGA | |
| CN102473198A (en) | Method for manufacturing integrated circuit, and semiconductor integrated circuit | |
| CN207992281U (en) | Module occurs for multichannel reference clock | |
| Cai et al. | Scalable power delivery design methodology for SoC on cost driven platforms | |
| TWI484350B (en) | Hub control chip | |
| US11575383B2 (en) | Clocking system and a method of clock synchronization | |
| CN106685412A (en) | Frequency divider, frequency divider system and frequency division processing method | |
| CN210270654U (en) | System circuit board, electronic equipment and server | |
| CN206757616U (en) | A kind of cloth plate structure of SSD control chips | |
| Wolff | What's New with IBIS and Upcoming Opportunities for SI and PI Engineers to Learn More | |
| CN109634886A (en) | A kind of multi-serial ports communication crystal oscillating circuit | |
| Andrejević et al. | Top-Level Layout Design of Solid-State Energy Meter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |