CN116232365A

CN116232365A - High sampling rate intermediate frequency receiving and transmitting communication system based on FPGA

Info

Publication number: CN116232365A
Application number: CN202310181738.1A
Authority: CN
Inventors: 田建松; 王诗力; 王晓东; 安瑞琪
Original assignee: Beijing Galaxy Xintong Technology Co ltd
Current assignee: Beijing Galaxy Xintong Technology Co ltd
Priority date: 2023-02-21
Filing date: 2023-02-21
Publication date: 2023-06-06

Abstract

The embodiment of the application discloses a high sampling rate intermediate frequency transceiver communication system based on FPGA, including: the device comprises an FPGA processor, an ADC circuit, a DAC circuit, a memory circuit, a power supply circuit, a clock circuit, a connector module and a communication interface circuit; the AD and DA chips in the ADC circuit and the DAC circuit are connected with the FPGA processor through a high-speed serial bus JESD204B interface so as to realize real-time sampling processing of front-end data; the clock circuit is used for generating device clocks of the ADC circuit, the DAC circuit and the FPGA processor, and a synchronous clock and a reference clock of a high-speed serial bus JESD204B interface so as to provide a synchronous sampling clock, a synchronous trigger signal and a control signal and meet the requirement of synchronous sampling of a system; the memory circuit is connected with the FPGA processor and used for caching the broadband data acquired by the ADC circuit; the connector module is connected with the FPGA processor and used for providing an interface of system equipment; the communication interface circuit is connected with the FPGA processor and used for providing an interface for interaction with the outside.

Description

High sampling rate intermediate frequency receiving and transmitting communication system based on FPGA

Technical Field

The application relates to the technical field of communication system design, in particular to a high sampling rate intermediate frequency receiving and transmitting communication system based on an FPGA.

Background

Today, where information technology is rapidly developing, the data volume and data rate of information systems are continuously increasing, and thus the implementation of high-speed data acquisition systems has become an increasingly important research direction. As the frequency of the intermediate frequency becomes higher in the present communication system, the bandwidth range becomes wider, and it becomes more difficult to accurately capture and reconstruct the reproduced signal without errors, and the requirement for the intermediate frequency communication system becomes higher, which means that the intermediate frequency must have a high sampling rate. The front end of the sampling rate of Gsps magnitude is difficult to realize at present, the data receiving module has strict requirements on the clock, the jitter is low, the signal to noise ratio of the high-quality clock can be improved, and the data acquisition precision is improved, so that the clock with low jitter and high quality is required to be used.

The intermediate frequency processing platform is mostly interconnected through an FMC (field programmable gate array) interface by adopting a mode that three boards of intermediate frequency receiving, baseband processing and intermediate frequency transmitting are separated, which is unfavorable for miniaturization of the system and leads to complexity of the whole system.

The traditional intermediate frequency communication processing platform adopts a plurality of parallel CMOS or parallel LVDS input-output ADC or DAC to realize signal acquisition and emission, a large number of parallel signals occupy a large amount of IO resources, and simultaneously, as the synchronism requirement of a plurality of data lines is required, the equilong and impedance control is required to be carried out on a large number of data lines, the technical requirement on the layout and wiring of a PCB is higher, strict phase consistency is difficult to achieve, and the phase calibration of a signal processing end is extremely difficult, so that a large amount of data is difficult to process in real time.

In summary, the conventional intermediate frequency transceiver communication system cannot meet the current requirements, and a high sampling rate is urgently needed, and the intermediate frequency transceiver communication system can process a large amount of data in real time, and has low design difficulty, high integration level and high sampling accuracy.

Disclosure of Invention

An object of the embodiment of the present application is to provide a high sampling rate intermediate frequency receiving and transmitting communication system based on FPGA, which is used for solving the problems of complex design, low integration level, difficulty in real-time processing of a large amount of data, and low sampling accuracy of the intermediate frequency receiving and transmitting communication system in the prior art.

To achieve the above object, an embodiment of the present application provides a high sampling rate intermediate frequency transceiver communication system based on FPGA, including: the device comprises an FPGA processor, an ADC circuit, a DAC circuit, a memory circuit, a power supply circuit, a clock circuit, a connector module and a communication interface circuit; wherein,,

AD and DA chips in the ADC circuit and the DAC circuit are connected with the FPGA processor through a JESD204B interface of a high-speed serial bus so as to realize real-time sampling processing of front-end data;

the clock circuit is used for generating a device clock of the ADC circuit, the DAC circuit and the FPGA processor, a synchronous clock of the high-speed serial bus JESD204B interface and a reference clock so as to provide a synchronous sampling clock, a synchronous trigger signal and a control signal, thereby meeting the requirement of synchronous sampling of a system;

The memory circuit is connected with the FPGA processor and used for caching the broadband data acquired by the ADC circuit;

the connector module is connected with the FPGA processor and used for providing an interface of system equipment;

the communication interface circuit is connected with the FPGA processor and used for providing an interface for interaction with the outside.

Optionally, the clock circuit adopts a low-jitter high-performance broadband synthesizer LMX2594 to provide a sampling clock for the ADC circuit, adopts an HMC7044 capable of outputting 14 paths of clocks to provide clocks for a system full board card, and reserves an LMK04828 clock chip capable of outputting 14 paths of clocks so as to improve the fault tolerance of a hardware system.

Optionally, the clock circuit input includes a clock provided by a system board internal temperature compensation crystal oscillator or an external input homologous clock, the clock enters an ultra-low jitter clock buffer LMK00304 chip capable of being used for 4-way output of synchronization of the internal clock or the external clock, the chip outputs three clocks, namely input reference clocks of HMC7044 and LMX2594 and LMK04828 respectively, the HMC7044 and LMK04828 respectively output one output clock which is convenient to be homologous with the external system, and outputs multiple clocks to the FPGA processor and the ADC circuit and the DAC circuit.

Optionally, the power supply circuit adopts a two-stage power supply method of combining a DCDC switching power supply and an LDO linear stabilized power supply, uses a high-efficiency switching converter to step down, and then performs second-stage regulation to reduce switching noise and improve voltage precision.

Optionally, the board card of the FPGA-based high-sampling-rate intermediate-frequency transceiving communication system adopts sixteen stacked layer designs, and the stacked layers are a TOP signal layer, a first ground plane, a first signal layer, a second ground plane, a second signal layer, a third ground plane, a first power plane, a second power plane, a fourth signal layer, a fourth ground plane, a fifth signal layer, a fifth ground plane and a bootom signal layer, and eight signal layers, six ground planes, two power layers, and further include a shielding layer and a grounded heat dissipation layer for reducing distortion of circuit signals and reducing local overheating phenomenon.

Optionally, the front end of the ADC circuit is connected with the TCM2-43X+ balun and connected with an analog signal to be acquired, and the front end of the DAC circuit is connected with the TCM2-43X+ balun and connected with the SMA head and connected with a medium frequency signal.

Optionally, the connector module is a VPX connector.

Optionally, the communication interface circuit includes a network interface circuit, a fiber optic interface circuit and/or an RS422 circuit.

Optionally, the interfaces of the communication interface circuit include 1 PCIE3.0 x 16 interface, 1-way SFP optical fiber interface, 1-way gigabit network interface, 1-way 422 interface and/or two-way LVDS interface, a PHY chip RTL8211 is used to convert an RGMII interface into the gigabit network interface, and then the gigabit network interface is output through a physical interface RJ45 for interaction with an upper computer, and the RS422 interface is used to control an external device.

Optionally, the board card of the FPGA-based high-sampling-rate intermediate-frequency transceiving communication system adopts an AD9172+adc12dj3200+xcku115 architecture.

The embodiment of the application has the following advantages:

the embodiment of the application provides a high sampling rate intermediate frequency receiving and transmitting communication system based on an FPGA, which comprises the following steps: the device comprises an FPGA processor, an ADC circuit, a DAC circuit, a memory circuit, a power supply circuit, a clock circuit, a connector module and a communication interface circuit; the AD and DA chips in the ADC circuit and the DAC circuit are connected with the FPGA processor through a high-speed serial bus JESD204B interface so as to realize real-time sampling processing of front-end data; the clock circuit is used for generating a device clock of the ADC circuit, the DAC circuit and the FPGA processor, a synchronous clock of the high-speed serial bus JESD204B interface and a reference clock so as to provide a synchronous sampling clock, a synchronous trigger signal and a control signal, thereby meeting the requirement of synchronous sampling of a system; the memory circuit is connected with the FPGA processor and used for caching the broadband data acquired by the ADC circuit; the connector module is connected with the FPGA processor and used for providing an interface of system equipment; the communication interface circuit is connected with the FPGA processor and used for providing an interface for interaction with the outside.

Through the system, the high sampling rate ADC and the DAC are connected with the FPGA through the JESD204B interface, so that the design difficulty of a PCB is reduced, the integration level of the board card is increased, and the system has the AD acquisition with the sampling rate up to 6.4Gsps and the DA transmission with the sampling rate up to 12.6Gsps, so that the full-bandwidth real-time acquisition of a large-bandwidth signal is realized; the clock chip with extremely low jitter is used for providing a clock for the whole global, wherein the clock jitter for ADC sampling is only 45fs, the signal-to-noise ratio and the spurious-free dynamic range of ADC and DAC sampling are improved, the clock homology of the whole board card is realized, the phase relation between data and the clock is adjusted, the establishment and maintenance time is optimized, and the correct sampling is ensured.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those skilled in the art from this disclosure that the drawings described below are merely exemplary and that other embodiments may be derived from the drawings provided without undue effort.

Fig. 1 is a system block diagram of an FPGA-based high-sampling-rate intermediate-frequency transceiving communication system according to an embodiment of the present application;

Fig. 2 is a power block diagram of an FPGA-based high-sampling-rate intermediate-frequency transceiving communication system according to an embodiment of the present application;

fig. 3 is a clock block diagram of an FPGA-based high-sampling-rate intermediate-frequency transceiving communication system according to an embodiment of the present application;

fig. 4 is a power-on timing block diagram of an FPGA in a high sampling rate intermediate frequency transceiver communication system according to an embodiment of the present application;

FIG. 5 is a DDR4 power block diagram in a high sampling rate intermediate frequency transceiver communication system based on an FPGA provided in an embodiment of the application;

fig. 6 is a clock block diagram of an FPGA-based high-sampling-rate intermediate-frequency transceiving communication system operating at a 4.8G sampling rate according to an embodiment of the present application.

Detailed Description

Other advantages and advantages of the present application will become apparent to those skilled in the art from the following description of specific embodiments, which is to be read in light of the present disclosure, wherein the present embodiments are described in some, but not all, of the several embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.

An embodiment of the present application provides an FPGA-based high-sampling-rate intermediate-frequency transceiving communication system, and referring to fig. 1, fig. 1 is a system block diagram of an FPGA-based high-sampling-rate intermediate-frequency transceiving communication system provided in an embodiment of the present application, it should be understood that the system may further include additional blocks not shown and/or blocks shown may be omitted, and the scope of the present application is not limited in this respect.

The main purpose of the application is to provide a high sampling rate intermediate frequency receiving and dispatching communication system hardware board card based on FPGA, preferably, the board card has the functions of AD sampling rate up to 6.4Gsps and DA sampling rate of 12.6Gsps, DDR4 cache can reach 128Gbit in total, and is used for caching broadband data acquired by ADC, PCIE 3.0X16 bandwidth can reach 100Gbit, and is used for uploading original or processed intermediate frequency data to other systems in real time.

The integrated board card comprises the following parts: the whole structure of the FPGA processor, the ADC circuit, the DAC circuit, the memory circuit, the power circuit, the clock circuit, the connector module and the communication interface circuit is shown in figure 1.

In some embodiments, the board card employs an AD9172+ADC12DJ3200+XCKU115 architecture, wherein a main processing FPGA (Field Programmable Gate Array ) chip employs an Ultrascale series chip XCKU115-2FLVB2104,1Gbit QSPI interface FLASH of Xilinx company for solidifying programs and storing data. Meanwhile, the board card integrates an AD chip ADC12DJ3200 with the sampling rate of 6.4Gsps and a DA chip AD9172 with the sampling rate of 12.6 Gsps.

AD and DA chips in the ADC circuit and the DAC circuit are connected with the FPGA processor through a high-speed serial bus JESD204B interface, and balun TCM2-43+ is connected with an SMA interface so as to realize real-time sampling processing of front-end data.

Specifically, the XCKU115 chip provides optimal cost, performance and power consumption ratio at a 20nm process node, and is suitable for signal processing tasks with high signal bandwidth and high complexity. The highest speed of the high-speed transceiver of the XCKU115 chip supports 16.3Gb/s, and can be used for the design of JESD204B, PCIE and other high-speed serial buses. Considering that a high sampling rate is required, an analog-to-digital conversion chip (ADC) ADC12DJ3200 is selected to realize the sampling processing of front-end data, and the ADC12DJ3200 device is a radio frequency sampling gigabit sampling analog-to-digital converter (ADC) and can directly sample the input frequency from direct current to more than 10 GHz. The maximum sampling rate of the ADC12DJ3200 is 3.2Gsps under the dual channel, and 6.4Gsps under the single channel mode. AD9172 is selected as a digital-to-analog conversion chip (DAC), and the chip is a high-performance dual-channel 16-bit DAC supporting the sampling rate of 12.6Gsps, and the device adopts an 8-wire 15Gbps JESD204B data input port, a high-performance on-chip DAC clock frequency multiplier and a digital signal processing function, so that the digital-to-analog conversion chip is suitable for single-band and multi-band direct-to-Radio Frequency (RF) wireless application occasions.

In some embodiments, the power supply circuit employs a two-stage power supply method of combining a DCDC switching power supply and an LDO linear regulated power supply, uses an efficient switching converter to step down, and then performs a second stage regulation to reduce switching noise and improve voltage accuracy.

Specifically, the switching power supply and the linear power supply are cooperatively designed, the peak value of the output current of the power supply chip is fully considered, the power supply plane is reasonably layered, and the noise of the switching power supply is ensured not to influence sensitive devices in the board card. The board card is provided with 8 pieces of memory (magnesium light (micro) DDR4 memory is selected), and the total memory is 16GB. The main frequency of the memory data is up to 1200MHz, the data bandwidth can be up to 2400MHz multiplied by 64bit, the problem of crosstalk is easy to occur to the high-speed signal of 8-chip memory, and reasonable layout and equal length design are performed.

The power supply of the board card is critical, any power supply has a problem, the whole system cannot work normally, the estimated power of the whole board card is about 50W, the input voltage is designed to be 12V, and the whole power supply circuit block diagram of the board card is shown in fig. 2.

In board-level hardware circuit design, a DCDC switching power supply and an LDO linear regulated power supply are often used for building a power supply topology. The DCDC switching power supply has the advantages of high conversion efficiency, low power consumption and high output current. While LDOs have the advantage of small output ripple and low noise, and are suitable for the scenario of powering precision devices, DCDC is needed for high current power supplies, such as the core power supply of FPGAs, however, for ADCs and DACs and clock chips, which are extremely sensitive to power supply noise and ripple, the power supply voltage must be low noise and provide the current needed to achieve nominal device performance. Therefore, the chips adopt a two-stage power supply scheme of combining a DCDC switching power supply and an LDO linear stabilized power supply, and the high-efficiency switching converter is used for reducing voltage, and then the second-stage regulation is carried out to reduce switching noise and improve voltage precision.

The clock circuit is used for generating the device clocks of the ADC circuit, the DAC circuit and the FPGA processor, and the synchronous clock and the reference clock of the high-speed serial bus JESD204B interface so as to provide a synchronous sampling clock, a synchronous trigger signal and a control signal and meet the requirement of synchronous sampling of the system.

In some embodiments, the clock circuit uses a low-jitter high-performance broadband synthesizer LMX2594 to provide a sampling clock for the ADC circuit, uses an HMC7044 capable of outputting 14 paths of clocks to provide clocks for the whole system board, and reserves an LMK04828 clock chip capable of outputting 14 paths of clocks to improve the fault tolerance of the hardware system.

Specifically, the clock is the core of the board card, and the clock circuit provides a synchronous sampling clock, a synchronous trigger signal and other forms of control signals for the whole board, so as to meet the requirement of synchronous sampling of the system.

The signal to noise ratio of AD and DA samples is directly related to the jitter of the sampling clock, the specific relationship is shown in formula (1), where t _j Is the jitter of the sampling clock, and reduces the jitter of the clock as much as possible to improve the signal-to-noise ratio.

SNR＝20lg(1/2πt _j ) (1)

After comprehensive consideration, a clock architecture is selected, the clock structure is shown in fig. 3, the clock circuit input can be selected to be a clock provided by a thermal compensation crystal oscillator in the board card or an external input homologous clock, then the clock enters an ultralow jitter clock buffer LMK00304 chip capable of being used for 4-way output of synchronization of the internal clock or the external clock, the chip outputs three ways of clocks which are respectively input reference clocks of the HMC7044 and the LMX2594 and the LMK04828, the HMC7044 and the LMK04828 respectively output one way of output clock which is convenient to be homologous with an external system, and in addition, multiple ways of clocks are also output to the FPGA, the ADC and the DAC circuit, so that the homology of the clock of the board card is achieved.

The connector module is connected with the FPGA processor and used for providing an interface of system equipment.

In some embodiments, the connector module is a VPX connector. Specifically, in order to facilitate equipment integration, the whole medium frequency transceiving communication system adopts a 6U VPX board card design (plug connector module of a VPX interface), the length is 233.35mm, the width is 160mm, and a backboard power supply mode is adopted for power supply.

In some embodiments, the communication interface circuitry includes network port circuitry, fiber optic interface circuitry, and/or RS422 circuitry.

Specifically, to facilitate interaction with the outside, the board card expands a rich interface circuit, including a network interface circuit, an optical fiber interface circuit, and an RS422 circuit. In some embodiments, the interface specifically includes: 1 PCIE 3.0X16 interface, 1 path SFP fiber interface, 1 path gigabit network interface, 1 path 422 interface, and reserved two-receive two-transmit LVDS interface. The RGMII interface is converted into a gigabit network interface by adopting a PHY chip RTL8211, and then the gigabit network interface is output through a physical interface RJ45 for interaction with an upper computer, and an RS422 interface can be used for controlling external equipment.

Specifically, the I/O pins of an FPGA are classified as High Range (HR), high Performance (HP), or High Density (HD). hr_i/O provides the most extensive voltage support, from 1.2V to 3.3V. HP_I/O is optimized for highest performance operation, from 1.0V to 1.8V. hd_i/O is reduced function I/O, 24 per group, providing 1.2V to 3.3V voltage support. All I/O pins are organized in banks, each bank having 52 HP or HR pins, or 24 HD pins. Each bank has a common VCCO output buffer power supply that also powers some of the input buffers. Furthermore, the HR group may be divided into two half groups, each with its own VCCO power supply. Some single ended input buffers require an internally generated or externally applied reference Voltage (VREF). The VREF pin may be driven directly from the PCB or may be generated internally using internal VREF generator circuitry in each bank.

There are many conflicting requirements for most of the design PCB performance requirements, target costs, manufacturing technology and system complexity, and the like, high speed digital circuits and radio frequency circuits are typically multi-layer board designs. Multiple ground reference planes (ground planes) can provide a good low impedance current return path, which can reduce common mode EMI. The ground plane and the power plane should be tightly coupled and the signal layer should also be tightly coupled with the adjacent reference plane. The signal wiring driven by the same high-speed digital device is ensured to take the same power layer as a reference plane as much as possible.

In some embodiments, the board card is of sixteen stacked layer design and is stacked exactly in a symmetrical design with TOP signal layer-first ground plane-first signal layer-second ground plane-second signal layer-third ground plane-first power plane-second power plane-fourth signal layer-fourth ground plane-fifth signal layer-fifth ground plane-BOTTOM signal layer, eight total signal layers, six ground planes, two power layers. The circuit has the advantages that circuit functions and miniaturization of the circuit board are realized, the overall weight is reduced, the wiring density is improved, the distance between components is reduced, the signal transmission path is shortened, the shielding layer is additionally arranged, the signal distortion of the circuit is reduced, the grounding heat dissipation layer is introduced, the phenomenon of local overheating can be reduced, and the reliability of overall operation is improved when factors such as signal integrity, EMI, EMC and the like are ensured.

The top and bottom layers of a multi-layer PCB are typically used to place components and a small number of traces, which are not required to be too long to reduce direct radiation generated by the traces.

The multiple power reference plane will be divided into several physical areas of different voltages. If the signal layer is in close proximity to the multi-supply layer, then signal currents on the signal layer in its vicinity will encounter undesirable return paths, causing gaps to appear in the return paths. For high speed digital signals, this unreasonable return path design can present serious problems, so it is desirable that the high speed digital signal wiring should be far from the multiple power reference planes.

The key clock signal selects LVDS level instead of CMOS level as much as possible, LVDS differential signals have the same amplitude and opposite phases, common mode interference can be resisted, the effect of EMI is better, and signals on a loop cancel each other because of opposite polarities, so that no energy is radiated.

The bonding pad in the center of the chip must be grounded in order to reduce the ground resistance, to be well grounded, and to form a stable and reliable electrical connection and heat dissipation connection.

The stub of the signal, which is the resistor, capacitor, inductor and is usually the stub of some residual wires when the PCB is wired, will generate antenna radiation effect, and seriously will cause signal reflection, and the high-speed serial bus of the top layer is replaced to the fifth signal layer, so that the stub of the via hole is reduced.

It should be ensured that the direction of most of the wirings is uniform while being orthogonal to the wiring direction of the adjacent signal layer. The key signals need to be perforated in a covered area, devices are placed, a power supply is put together, analog and digital places in a circuit need to be divided, and shielding covers can be added to places with serious interference sources. The impedance of the ground wire is reduced, so that the reset and interruption can be reduced, and sensitive circuit signals such as control signal wires and the like are easily interfered by noise.

The two wires are too close to each other, so that crosstalk can be generated, the 3W criterion or the 5W criterion is generally met as much as possible, the root is the coupling of signals through an electric field or a magnetic field, noise is generated, the crosstalk is reduced, firstly, the distance between the two wires is increased, secondly, the heights of a signal layer and a reference layer are changed, the larger the thickness of a medium is, the larger the relative coupling degree is, the larger the crosstalk is, and the backflow area of the signals can be reduced by adding a protection ground wire.

Through the system, the high sampling rate ADC and the DAC are connected with the FPGA through the JESD204B interface, so that the design difficulty of a PCB is reduced, the integration level of the board card is increased, and the system has the AD acquisition with the sampling rate up to 6.4Gsps and the DA transmission with the sampling rate up to 12.6Gsps, so that the full-bandwidth real-time acquisition of a large-bandwidth signal is realized;

The power supply structure is reasonably distributed and designed, so that the stability of FPGA, ADC, DAC and clock chips is ensured, and the robustness of the system to jitter interference under high-speed sampling rate operation is improved;

the clock chip with extremely low jitter is used for providing a clock for the whole global, wherein the clock jitter for ADC sampling is only 45fs, and the signal-to-noise ratio and the spurious-free dynamic range of ADC and DAC sampling are improved. In addition, a clock chip is reserved, so that the stability and fault tolerance of the board clock structure are ensured, the clock homology of the whole board is realized, the phase relation between data and clocks is adjusted, the establishment holding time is optimized, and the correct sampling is ensured.

In order to make the present application more clear, the present application will be further clearly and specifically described with reference to the accompanying drawings and specific examples.

To verify the feasibility of the present board method, the following embodiment uses ADC and DAC operating at 4.8G sampling rate, and DA transmitting 300M symbol rate signal to explain JESD204B link synchronization details and clock design details, and other hardware design details.

As shown in fig. 1, in some embodiments, the hardware design of the FPGA-based high-sampling rate intermediate frequency transceiving communication system is that the main processing chip is an FPGA, the complete model is XCKU115-2FLVB2104I, four pieces of DDR4 are respectively placed on the left and right sides of the board, and each piece of 2GB memory is used for caching data. The VPX standard is a new high-speed bus standard, the VPX bus supports multiple high-speed serial bus protocols, and the board card receives PCIE3.0 x 16 through the VPX interface.

The FPGA is connected with an SPI control line of the clock chip and a control line of the optical fiber interface through a 3.3V level bank, a serial port is led out, the serial port is converted into an RS422 level through a MAX3490 chip to be connected out, and the serial port is connected with an FM24C256 chip through an IIC interface and used for solidifying certain instruction information which needs to be powered down and not lost. The QSPI_FLASH chip MT25QL256ABA1EW9 is selected and can be used for solidifying programs, saving data and configuration files and initializing a system. QSPI_FLASH clock pin FLASH_CLK, chip select pin FLASH_nCS and data pin FLASH_IO are all connected to BANK0 of the FPGA; the QSPI_FLASH loading speed is 66MHz at the highest by using FLASH-CLK, namely an FPGA internal clock.

The FPGA is connected with SPI control lines of the ADC and the DAC through a 1.8V level bank, and is connected with data interfaces of the ADC-ADC12DJ3200 and the DAC-AD9172 through a JESD204B interface. The front end of the ADC is connected with the analogue signal to be collected by the TCM2-43X+ balun, and the front end of the DAC is connected with the intermediate frequency signal of the SMA head by the TCM2-43X+ balun. The FPGA is connected with an RGMII interface of 1.8V level and is connected with a gigabit network PHY chip, and the RGMII interface is led out through an RJ45 interface to interact with the outside. The external serial-parallel transceiver chip TLK2711 can support the serial interface speed of 1.6Gbps to 2.7Gbps and is led out through the HJ30J-12ZKW chip. The FPGA is connected with the ADN4654BRSZ chip to receive and transmit two-to-receive LVDS signals, isolated from the outside and led out through the HJ30J-12ZKW chip. The board card is provided with one path of SFP optical fiber interface which can be connected with a general optical module on the market and is used for high-speed signal transmission.

As shown in fig. 2: the FPGA uses a single channel to output a 50A switch mode buck DC-DC, a uModule (power supply module) voltage stabilizer LTM4650 supplies power for a nuclear power supply VCCINT of the FPGA, and a switch controller, a power FET, an inductor and all supporting components are arranged in the packaging of the LTM 4650. A plurality of TPS82130SILT voltage stabilizing chips are used for outputting 1.2V,1.8V and 3.3V to supply power for VCCIO of the FPGA, and the VCCAUX is also supplied with power by the TPS82130SILT voltage stabilizing chips. The MGT high-speed transceiver of the FPGA uses two-stage power supply, the high-speed transceiver is divided into two groups of RIGHT and LEFT, the two groups are respectively and independently powered, the DC-DC, namely TPS54821 RHRLR chip is used for converting 12V into 1.26V, and then the LDO, namely TPS7A8500RGRT chip is used for converting 1.26V into 1.0V and 1.2V to supply power (two-stage power supply) to MGTAVCC and MGTAVTT of the FPGA.

The hardware design of the FPGA-based high-sampling rate intermediate-frequency transceiving communication system in some embodiments works at a 4.8G sampling rate by the following steps:

step 1.1: the power supply of the FPGA has a strict power-on sequence, the power-on sequence is shown in fig. 4, namely, firstly, a nuclear power supply of 0.95V, secondly, an FPGA auxiliary power supply of 1.8V, then a BANK power supply of 3.3V,1.8V,1.5V and 1.2V of the FPGA, and finally, the power supplies of MGT_BANK are 1.0V and 1.2V, wherein the auxiliary power supply of 1.8V of the MGT does not participate in time sequence.

Step 1.2: the board ADC chip adopts a 1.9V and 1.1V power supply mode, the current required by each of 1.9V and 1.1V is not more than 2A, the whole power is not more than 4W, and the power supply chip of the board can output 4A current to meet the system requirement. And the power supply is orderly powered up, 1.9V is needed to be powered up first, and 1.1V is needed to be powered up. The ADC chip was powered (secondary power supply) using first a DC-DC, i.e., TPS82130SILT chip to convert 12V to 2.2V and 1.4V, and then an LDO, i.e., TPS7a8500RGRT chip to convert 2.2V and 1.4V to 1.9V and 1.1V.

Step 1.3: the power supply design of the DAC part of the board card, the AVDD1.0 power supply for supplying power to the clock receiver and the DAC analog core circuit and the AVDD1.8 power supply for supplying power to the DAC output and the DAC_PLL module are the power supplies which are the most sensitive to noise on the device. It is strongly recommended that AVDD1.0 and AVDD1.8 be supplied separately from the ultra-low noise voltage regulator to achieve the best possible phase noise performance.

AVDD1.0V the maximum current required by the sum of AVDD1.8V and DVDD1.8V is not more than 1.2A, the maximum current required by DVDD1.0V is not more than 0.2A, the maximum current required by DVDD1.0V is not more than 0.8A, and the maximum power consumption of the whole chip is not more than 4W. DVDD1.0V power supplies power to the digital datapath modules and SVDD1.0V power supplies power to the SERDES circuitry on the chip. DVDD1.8V power supplies power to the circuit blocks associated with the SPI, SYNCOUTx+ -transmitter, SYSREF receiver, IRQx, RESE, and TXENx circuits.

The DA chip also adopts a two-stage power supply scheme, namely a DC-DC (direct current-direct current) or TPS82130SILT chip is used for converting 12V into 1.8V and 3.3V, two LDOs (ADP 1763) or ACPZ chips are used for converting 1.8V into AVDD1.0, DVDD1.0V and SVDD1.0V, and one LDO or ADM7154ACPZ chip is used for converting 3.3V into 1.8V to supply power for the DAC chip.

Step 1.4: the board card has four clock chips, and clock jitter affects the performance of the board card, so that the clock needs a low-noise power supply to supply power to the board card. Therefore, LDO is selected to supply power, the power supply is 3.3V, wherein the current required by LMK04828 is not more than 1.5A, the current required by LMK00304SQ is not more than 0.2A, the current required by LMX2594RHAR is not more than 1A, and the TPS7A8500RGRT chip can output 4A current, so that the current meets the requirement. The clock chip adopts a scheme of two-level power supply, firstly uses a DC-DC (direct current-direct current) or TPS82130SILT chip to convert 12V into 3.8V, and then uses an LDO (low dropout regulator) or TPS7A8500RGRT chip to convert 3.8V into 3.3V to supply power for the three clock chips.

And to the clock power supply, adopted the punching electric capacity to carry out further filtering to the power, the punching electric capacity is three terminal capacity, and the earth inductance is littleer, does not have the influence of lead wire inductance, so there is higher self-resonance to the input/output end is kept apart by the metal sheet, has eliminated high frequency coupling, and ordinary electric capacity lead wire inductance can cause the electric capacity resonance, presents great impedance to high frequency signal, has weakened the bypass effect to high frequency signal, and parasitic capacitance between the wire also can make high frequency signal take place the coupling.

Step 1.5: the requirement of the DDR main power supply is vddq=vdd, VDDQ is a power supply for supplying power to the IObuffer, and VDD is a power supply for supplying power to the chip, but VDDQ and VDD are combined into one power supply for use in general use. Since DDR currents are generally large, PCB designs require a complete power plane to be laid down on the pins and capacitor storage to be added at the power inlet.

Vref is a reference voltage, and is required to be accurate and constant and used for judging the basis of the high and low levels of the signal. The reference power Vref is required to follow VDDQ, and vref=vddq/2, so it can be provided using a power chip, or can be obtained by means of resistor voltage division. Because Vref is generally smaller in current, on the order of several mA to tens mA, the voltage division mode of resistors can be used, so that the cost is saved, the layout is flexible, the voltage is placed nearer to Vref pins, and the voltage closely follows the VDDQ voltage. The VTT is used for a power supply of a pull-up resistor and a pull-down resistor, and has large current, large fluctuation and large noise. VTT is the power supply to which the matched resistor is pulled up, vtt=vddq/2. In the design of DDR, according to different topological structures, some designs cannot use VTT, such as the situation that DDR devices with controller are less. If VTT is used, the current requirements of VTT are relatively large, so traces need to be plated out with copper. And VTT requires a power supply to both supply and sink current.

The TPS51200 device is a sink-current and pull-current Double Data Rate (DDR) terminal voltage regulator designed specifically for low input voltage, low cost, low noise, space-constrained systems. TPS51200 can maintain a fast transient response, requiring only a 20 μF ultra low output capacitance. TPS51200 supports the remote sensing function and meets all power requirements of the VTT bus terminals of DDR3 and DDR4, and the sink current and pull current terminal voltage stabilizer with the voltage drop compensation function, and REFIN input allows flexible input tracking directly or through a resistor divider.

DDR4 requires VDD1.2V power, except that they require VTT, VTTREF power. For DDR4, the voltages are both 0.6V, VTT and VTTREF are all supplied through DDR power special chip TPS51200DRCR, and the DDR4 power supply block diagram is shown in FIG. 5.

Step 2: FPGA-XCKU115 includes 12 HP_BANK,3 HRBANK,16 GTHBANK, split into two sides, 10 and continuous on one side RIGHT, six on the other side LEFT, three continuous, discontinuous between two groups.

Step 2.1:44 The 45, 46BANK interface level is 1.8V, connecting the control lines of AD9172 and ADC12DJ3200, and there are two pairs of clock lines fpga_clka and fpga_sysrefa (given by clock chip LMK 04828). 51 The 52, 53BANK interface level is also 1.8V, the control lines connecting TLK2711 and RGMII and part of ADC12DJ3200 and the outgoing two-receive two-transmit LVDS lines and a 100M clock, and there are two pairs of clock lines FPGA_CLKB and FPGA_SYSREFB (given by HMC 7044).

Step 2.2:66 The 67, 68BANK interface level is 1.2V, which is respectively connected with four data lines and address lines of DDR3 and 125M clock given by an external crystal oscillator. 71 The level of the BANK interface of 72 and 73 is 1.2V, and the data line and the address line of four DDR4 are respectively connected with a 125M clock given by an external crystal oscillator.

Step 2.3:65 85, 94BANK is HRBANK, interface level is 3.3V, all control lines of EEPROM, RS422, HMC7044, LMX2594, optical fiber, LMK04828 and VPX are respectively connected, and two GPIOs and two LED lamps are reserved.

Step 2.4:224 Four mgtbanks, 225, 226, 227 total sixteen pairs of high speed lines, PCIE3.0 x 16 lines, total four clock reference inputs, two pairs from the crystal oscillator, and two pairs from HMC 7044. 133BANK is connected with one optical fiber interface, and the clock can come from LMK04828 or HMC 7044. 126 and 127BANK receive eight pairs of receive and eight pairs of transmit JESD204B high-speed lines of ADC and DAC, and the reference clock can be from LMK04828 or HMC7044 or crystal oscillator. 131 The 132BANK is connected with eight pairs of JESD204B lines of the ADC, reserved for use, and the reference clock can be from LMK04828 or HMC7044 or crystal oscillator. Other BANK suspension designs.

Step 3: the link synchronization process in JESD204B interface is divided into three stages of code group synchronization, link alignment and data transmission

Step 3.1: the code group synchronization stage is that the receiver of JESD204B first pulls down the SYNC synchronization signal, which is equivalent to the receiver sending a synchronization request signal to the sender, and then the sender starts sending/K28.5/symbol after receiving the request signal, which is represented in the program as BCBCBCBC, and when the receiver receives at least four/K28.5/symbol, it represents to accept the synchronization process and pulls up the SYNC, and then enters the link alignment stage.

Step 3.2: and in the link alignment stage, all channels in the link are aligned, and character offset caused by routing errors with different lengths is adjusted. After the transmitting end internally tracks the data of one complete frame to be transmitted, 4 multiframes are started to be transmitted, the receiving end aligns channels from all links, and the link parameters are verified.

Multiframe 1: beginning with/K28.0/symbol and ending with/K28.3/symbol;

multiframe 2: beginning with/K28.0/symbol, followed by/K28.4/symbol, followed by 14 parameters of 8 bits for link configuration, ending with/K28.3/symbol;

multi-frame 3: the same as multiframe 1;

multiframe 4: the same as the multi-frame 1, after the multi-frame data is sent, the data is sent;

step 3.3: the data transmission stage comprises the following steps: after the multi-frame data transmission is completed, character frame substitution is performed at the end of the frame, and data transmission is started.

By controlling the character monitor frame alignment, the transmitter and receiver each maintain a multi-frame counter LMFC, which is a clock reference for JESD204B to complete deterministic latency functions, that counts to FxK-1 and then becomes 0 to recount, which can be reset by SYSREF. To accomplish synchronous transmission of multi-channel data, the LMFCs between the channels must be synchronized and the SYSREF signal is sampled by the edge alignment device_clock signal, which is the rising edge of the LFMC when it detects a SYSREF change from 1 to 0. An external SYSREF signal provides a uniform edge alignment reference for each channel LMFC, and the rising edge of the SYSREF signal is collected by a Device Clock (Device Clock) to determine the alignment time of LMFC.

Step 4: the JESD204B link needs a plurality of clocks for establishment, and the GTH of the high-speed transceiver of the FPGA needs a reference clock, so that about ten clocks are needed, and a clock chip HMC7044 which provides 14 clocks at most is selected to provide clocks for the board, wherein the HMC7044 is a high-performance double-loop integer N frequency division jitter attenuator, can select the frequency for referencing and generating ultra-low phase noise, and supports a high-speed data converter with a parallel or serial (JESD 204B type) interface. HMC7044 has two integer mode PLLs selectable through SPI and overlapping on-chip VCOs, tuning ranges up to 2.5GHz and 3GHz, respectively, and simplifies the design of baseband and radio card clock trees through a variety of clock management and distribution features. The DCLK and SYSREF clock outputs of HMC7044 may be configured to support signal standards such as CML, LVDS, LVPECL and LVCMOS, and different bias settings may counteract the varying board insertion loss.

Meanwhile, LMK04828 is used as an alternative clock chip, and is a high-performance, low-jitter and low-phase-noise clock conversion chip, can support the generation of JESD204B clocks with deterministic delay, is mainly used for generating JESD204B synchronous clocks of an FPGA end, an ADC and a DAC, and simultaneously generates PLL reference clocks of a high-speed transceiver GTHbank of the FPGA, so that a plurality of clocks are reserved for providing clocks for a board chip, and when HMC7044 cannot work, the LMK0428 can be used for configuring a link, so that the board can work normally.

In addition, the low-jitter high-performance wideband synthesizer LMX2594 alone provides the sampling clock and the reference clock for the high-speed ADC, LMX2594 is a high-performance wideband synthesizer that operates at 7.5GHz with 45fs jitter, can generate any frequency in the range of 10MHz to 15GHz without using an internal doubler, and the high-performance PLL and high-phase detector frequency with a figure of merit of-236 dBc/Hz can achieve very low in-band noise and integrated jitter.

Step 5: a block diagram of specific clock parameters for each of the ADC and DAC operating at a 4.8G sampling rate is shown in fig. 6, and the clock generation and calculation process is briefly described below.

Step 5.1: according to the method for realizing the JESD204B link processed by the ADC by the circuit board, for the link, an ADC end is used as a transmitting end, an FPGA end is used as a receiving end, a high-speed transceiver GTH is needed in the process of receiving a data stream by the FPGA, when the GTH works, a reference clock Ref_CLK is needed to be provided externally, in addition, in order to make the link work normally, at least four clocks are needed to be provided externally, the reference clock Rx_Core_CLK of the FPGA, the Sysref_CLK of the FPGA end, the sampling clocks sample_CLK and Sysref_CLK of the ADC12DJ3200 are needed, wherein the two clocks of the FPGA are selected from an HMC7044 chip or an HMC7044 chip and an LMK04828 chip. Wherein the two clocks of ADC12DJ3200 originate from the low jitter phase locked loop LMX2594 chip.

For an ADC operating in a single channel JMODE0 mode at a sampling rate of 4.8Gsps, sample_clk is chosen to be half the sampling rate, i.e., 2.4Ghz, and the parameter R in this mode is 4, which is calculated to be 9.6Gbps according to the following equation (2).

Lane_Rate＝Sample_CLK×R (2)

The reference clock Rx_Core_CLK of the FPGA is 240Mhz as shown in equation (3) of the Siring handbook.

Rx_Core_CLK＝Lane_Rate÷40 (3)

According to the formula (4) described in the ADC manual, n is 4,F, 8,K is 32, lane_Rate is 9.6Gbps, and Sysref_CLK of the FPGA and ADC12DJ3200 is 0.9375Mhz.

Step 5.2: according to the method for realizing the JESD204B link processed by the DAC by the circuit board, for the link, a DAC end is used as a receiving end, an FPGA end is used as a transmitting end, and when the FPGA receives a data stream, a high-speed transceiver GTH is needed, and when the GTH works, a reference clock Ref_CLK is needed to be provided externally, and in addition, at least four clocks are needed to be provided externally for the link to work normally, the reference clock Tx_Core_CLK of the FPGA, the Sysref_CLK of the FPGA end and the sampling clock Fref_CLK of AD9172 are needed to be provided externally _DAC And Sysref CLK. Wherein the two clocks of the FPGA and the AD9172 are derived from HMC7044 chip or HMC7044 and LMK04828 chip selections.

For DAC at 4.8G sampling Rate, signal with symbol Rate 300M is sent, DAC is selected to work in single channel MODE9 MODE, first, four times interpolation filtering is carried out on 300Msps signal at FPGA end to obtain 1.2G sampling Rate signal, then, four times interpolation is carried out on signal at DA end to obtain 4.8G sampling Rate signal, according to the following formula (5), M is 2, L is 4, NP is 16, lane_Rate is calculated to be 12Gbps.

Lane_Rate＝(ML)×NP×(108)×Data_Rate (5)

The reference clock Tx_Core_CLK of the FPGA was 300Mhz as shown in equation (6) of the Siring handbook.

Tx_Core_CLK＝Lane_Rate÷40 (6)

According to the formula (7) described in the DAC manual, n is 16, F is 2,K, lane_Rate is 12Gbps, and Sysref_CLK of the FPGA and ADC12DJ3200 is 1.171875Mhz.

F is shown according to the formula (8) of DAC manual _DAC 4.8G, N configured as 5, M configured as 1, bits [1:0 ] of Regisiter0x094]Set to 0, thereby calculating Fref_CLK _DAC 120Mhz.

F _DAC ＝(8×N×Fref_CLK _DAC )/M(Register0x094，Bits[1:0]+1) (8)

While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be appreciated that the foregoing is merely illustrative of one embodiment of the invention and that no limitations are intended to the scope of the invention, except as may be modified or practiced in the spirit and principles of this application.

Note that all features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic set of equivalent or similar features. Where used, further, preferably, still further and preferably, the brief description of the other embodiment is provided on the basis of the foregoing embodiment, and further, preferably, further or more preferably, the combination of the contents of the rear band with the foregoing embodiment is provided as a complete construct of the other embodiment. A further embodiment is composed of several further, preferably, still further or preferably arrangements of the strips after the same embodiment, which may be combined arbitrarily.

Claims

1. An FPGA-based high sampling rate intermediate frequency transceiving communication system, comprising: the device comprises an FPGA processor, an ADC circuit, a DAC circuit, a memory circuit, a power supply circuit, a clock circuit, a connector module and a communication interface circuit; wherein,,

2. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

The clock circuit adopts a low-jitter high-performance broadband synthesizer LMX2594 to provide a sampling clock for the ADC circuit, adopts an HMC7044 capable of outputting 14 paths of clocks to provide clocks for the whole system board card, and reserves an LMK04828 clock chip capable of outputting 14 paths of clocks so as to improve the fault tolerance of a hardware system.

3. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the clock circuit input comprises a system board internal temperature compensation crystal oscillator providing clock or an external input homologous clock, the clock enters an ultralow jitter clock buffer LMK00304 chip capable of being used for 4-path output of synchronization of the internal clock or the external clock, the chip outputs three paths of clocks which are input reference clocks of HMC7044 and LMX2594 and LMK04828 respectively, the HMC7044 and the LMK04828 respectively output one path of output clock which is convenient to be homologous with the external system, and the clock is output to the FPGA processor, the ADC circuit and the DAC circuit.

4. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the power supply circuit adopts a two-stage power supply method of combining a DCDC switching power supply and an LDO linear regulated power supply, uses a high-efficiency switching converter to reduce voltage, and then carries out second-stage regulation to reduce switching noise and improve voltage precision.

5. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the board card of the FPGA-based high-sampling-rate intermediate-frequency receiving and transmitting communication system adopts sixteen laminated layer designs, wherein the laminated layers are TOP signal layers, a first ground plane, a first signal layer, a second ground plane, a second signal layer, a third ground plane, a first power plane, a second power plane, a fourth signal layer, a fourth ground plane, a fifth signal layer, a fifth ground plane and a BOTTOM signal layer, and the board card further comprises shielding layers and grounding heat dissipation layers for reducing distortion of circuit signals and reducing local overheating.

6. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the front end of the ADC circuit is connected with the analog signals to be collected by the TCM2-43X+ balun, and the front end of the DAC circuit is connected with the intermediate frequency signals of the SMA head of the TCM2-43X+ balun.

7. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the connector module is a VPX connector.

8. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

The communication interface circuit comprises a network interface circuit, an optical fiber interface circuit and/or an RS422 circuit.

9. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the interfaces of the communication interface circuit comprise 1 PCIE3.0×16 interface, 1 SFP optical fiber interface, 1 gigabit network interface, 1 channel 422 interface and/or two-to-two LVDS interface, the PHY chip RTL8211 is used for converting the RGMII interface into the gigabit network interface, and then the gigabit network interface is output through a physical interface RJ45 for interaction with an upper computer, and the RS422 interface is used for controlling external equipment.

10. The FPGA-based high sample rate intermediate frequency transceiver communication system of claim 1,

the board card of the FPGA-based high-sampling-rate intermediate-frequency transceiving communication system adopts an AD9172+ADC12DJ3200+XCKU115 architecture.