CN203644037U - System-level chip - Google Patents
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- CN203644037U CN203644037U CN201320890323.3U CN201320890323U CN203644037U CN 203644037 U CN203644037 U CN 203644037U CN 201320890323 U CN201320890323 U CN 201320890323U CN 203644037 U CN203644037 U CN 203644037U
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Abstract
The utility model provides a system-level chip. The system-level chip comprises a first part circuit and a second part circuit. The first part circuit comprises one or more SOC digital components, the second part circuit comprises one or more SOC analog components, and the first part circuit and the second part circuit are arranged on different domains or bare chips or chips or programmable devices. The first part circuit and the second part circuit are connected through a communication interface. By means of the system-level chip, an SOC is replied in the technological node upgrading process, design cost is lowered, the time to market of products is shortened, and the tape-out risk is lowered.
Description
Technical field
The utility model relates to SOC technology, relates in particular to a kind of system level chip.
Background technology
Existing system level chip (SOC, System on Chip) method for designing, is all integrated in various Digital Logic IP and various analogue unit IP on one chip, conventionally to improve to greatest extent integrated level.Wherein, Digital Logic IP can comprise the various issued transaction unit such as central processing unit (CPU), digital signal processor (DSP), counter (TIMER), house dog (WATCHDOG), the various computing units such as figure, video, audio frequency, encryption and decryption, the various digital interfaces such as SDMMC, universal asynchronous receiving-transmitting transmitter (UART), Serial Peripheral Interface (SPI) (SPI), the protocol layer of the various HSSI High-Speed Serial Interface such as USB (universal serial bus) (USB), PCIe, SATA, HDMI and connect the on-chip bus of each equipment, but be not limited to this; Analogue unit IP can comprise modulus walk around device (ADC), digital to analog converter (DAC), the Physical layer (PHY) of system, audio frequency and video phaselocked loop (PLL) and various HSSI High-Speed Serial Interface, but be not limited to this.Although all the above modules are all integrated on one chip and can improve integrated level, and problem is also following.
Along with the continuous lifting of main flow process node in recent years, chip companies is to catch up with main flow process node to reduce flow cost or in order to obtain higher system frequency, SOC product need to constantly be changed flow technique conventionally.In the process of replacing flow technique, the upgrading of Digital Logic part IP seldom brings increase and the potential risk of cost conventionally, but analogue unit IP need to redesign or obtain the authorization conventionally, often cause the R & D Cost of these analogue units IP or mandate expense high; And the upgrading of the chip Time To Market of flow meeting delay product again, once go wrong, loss is incited somebody to action and is serious.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of system level chip, can make SOC in process node escalation process, significantly reduce design cost, shortens time to market (TTM), reduce flow risk.
For solving the problems of the technologies described above, the utility model provides a kind of system level chip, comprises Part I circuit and Part II circuit, wherein,
Described Part I circuit comprises one or more SOC digital units;
Described Part II circuit comprises one or more SOC analog components;
Described Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device, between described Part I circuit and Part II circuit, connect by communication interface.
According to an embodiment of the present utility model, described Part I circuit and Part II circuit are shared same external memory storage.
According to an embodiment of the present utility model, described communication interface is SERDES interface, and described Part I circuit comprises:
The one SERDES interface;
The first general SERDES data link layer, is connected with a described SERDES interface;
Described Part II circuit comprises:
The 2nd SERDES interface, with a described SERDES interface physical connection;
The second general SERDES data link layer, is connected with described the 2nd SERDES interface;
Memory Controller Hub and Physical layer, be connected with described the second general SERDES data link layer, and described Part II circuit is connected with described external memory storage via rambus;
Wherein, described Part I circuit, by the right to use of the described rambus of application, is accessed described external memory storage via described the first general SERDES data link layer, a SERDES interface, the 2nd SERDES interface, the second general SERDES data link layer, Memory Controller Hub and Physical layer and rambus; Described Part II circuit, by the right to use of the described rambus of application, is accessed described external memory storage via described Memory Controller Hub and Physical layer and rambus.
According to an embodiment of the present utility model, described communication interface is SERDES interface, and described Part I circuit comprises:
The one SERDES interface;
The first general SERDES data link layer, is connected with a described SERDES interface;
Memory Controller Hub and Physical layer, be connected with described the first general SERDES data link layer, and described Part I circuit is connected with described external memory storage via rambus;
Described Part II circuit comprises:
The 2nd SERDES interface, with a described SERDES interface physical connection;
The second general SERDES data link layer, is connected with described the 2nd SERDES interface;
Wherein, described Part I circuit is accessed described external memory storage via described rambus; Described Part II circuit is accessed described external memory storage via described the second general SERDES data link layer, the 2nd SERDES interface, a SERDES interface, the first general SERDES data link layer and Memory Controller Hub and Physical layer and rambus.
According to an embodiment of the present utility model, described Part I circuit also comprises:
On-chip bus, is connected with described the first general SERDES data link layer;
Issued transaction unit and computing unit, be connected with described on-chip bus, and this issued transaction unit and computing unit are via Part II circuit described in described on-chip bus, the first general SERDES data link layer and a SERDES interface accessing.
According to an embodiment of the present utility model, described issued transaction unit comprises central processing unit, digital signal processor, counter and/or house dog, and described computing unit comprises: graphics calculations unit, video computing unit and/or encryption and decryption computing unit.
According to an embodiment of the present utility model, described Part I circuit also comprises one or more in following circuit module:
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer, is connected and is connected with on-chip bus with described the first general SERDES data link layer:
High-speed interface application layer, is connected with on-chip bus with described the first general SERDES data link layer;
Storing communication digital interface, is connected with described on-chip bus;
System phaselocked loop, produces the first Digital Logic and drives clock to use for other circuit modules in described Part I circuit.
According to an embodiment of the present utility model, described ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer comprises data processing module, the data processing module of video AD C and/or the data processing module of touch-screen of audio frequency DAC; Described high-speed interface application layer comprises USB interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI interface application layer; Described storing communication digital interface comprises SDMMC digital interface, UART digital interface and/or SPI digital interface.
According to an embodiment of the present utility model, described the first general SERDES data link layer is by the data stream of the data stream from described on-chip bus, described ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer and carry out data fusion from the data stream of described high-speed interface application layer, data stream after combination of management, and set up data stream transmission, reception and retransmission mechanism.
According to an embodiment of the present utility model, described Part II circuit also comprises one or more in following circuit module:
High-speed interface protocol layer, is connected with described the second general SERDES data link layer;
Digital interface, is connected with described the second general SERDES data link layer;
Association's processing unit, is connected with described the second general SERDES data link layer;
Physical layer, is connected with described high-speed interface protocol layer;
ADCs and DACs, be connected with described digital interface;
Audio frequency and video phaselocked loop, produces the second Digital Logic and drives clock to use for other circuit modules in described Part II circuit.
According to an embodiment of the present utility model, described high-speed interface protocol layer is packaged into the data stream packing from high-speed interface application layer to meet the protocol package of interface definition and be sent to described Physical layer; Described digital interface produces the sequential interface of described ADCs and DACs, and sends data to corresponding DACs or from corresponding ADCs, data read in; Described Physical layer comprises SATA Physical layer, USB Physical layer, PCIe Physical layer and/or HDMI Physical layer; Described association processing unit is controlled for operation initialization and the operation of described Part II circuit.
According to an embodiment of the present utility model, described the second general SERDES data link layer splits data stream or the encapsulation uplink data after being merged by described the first general SERDES data link layer, wherein, the data stream after fractionation is sent to respectively described high-speed interface protocol layer, ADCs and DACs or described association processing unit.
According to an embodiment of the present utility model, a described SERDES interface and the 2nd SERDES interface comprise string also/and go here and there device, transmitting-receiving FIFO, receive alignment of data parts, timer manager, transmitting-receiving line interface, line codec and/or passage binding parts.
According to an embodiment of the present utility model, described communication interface is ddr interface, and described Part I circuit comprises:
The one DDR master controller and Physical layer;
Described Part II circuit comprises:
DDR, from controller, is connected with a described DDR master controller and Physical layer;
The 2nd DDR master controller and Physical layer, is connected from controller with described DDR, and described DDR master controller and Physical layer are connected with external memory storage via rambus;
Wherein, described Part I circuit, by the right to use of the described rambus of application, is accessed described external memory storage via a described DDR master controller and Physical layer, DDR from controller, the 2nd DDR master controller and Physical layer and rambus; Described Part II circuit, by the right to use of the described rambus of application, is accessed described external memory storage via described the 2nd DDR master controller and Physical layer and rambus.
According to an embodiment of the present utility model, described Part I circuit also comprises:
On-chip bus, is connected with a described DDR master controller and Physical layer;
Issued transaction unit and computing unit, be connected with described on-chip bus, and this issued transaction unit and computing unit are accessed described Part II circuit via described on-chip bus and a DDR master controller and physical layer interface.
According to an embodiment of the present utility model, described issued transaction unit comprises central processing unit, digital signal processor, counter and/or house dog, and described computing unit comprises: graphics calculations unit, video computing unit and/or encryption and decryption computing unit.
According to an embodiment of the present utility model, described Part I circuit also comprises one or more in following circuit module:
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer, is connected with described on-chip bus and a DDR master controller and Physical layer:
High-speed interface application layer, is connected with described on-chip bus and a DDR master controller and Physical layer;
Storing communication digital interface, is connected with described on-chip bus;
System phaselocked loop, produces the first Digital Logic and drives clock to use for other circuit modules in described Part I circuit.
According to an embodiment of the present utility model, described ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer comprises data processing module, the data processing module of video AD C and/or the data processing module of touch-screen of audio frequency DAC; Described high-speed interface application layer comprises USB interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI interface application layer; Described storing communication digital interface comprises SDMMC digital interface, UART digital interface and/or SPI digital interface.
According to an embodiment of the present utility model, a described DDR master controller and Physical layer are by the data stream of the data stream from described on-chip bus, described ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer and carry out data fusion from the data stream of described high-speed interface application layer, data stream after combination of management, and set up data stream transmission, reception and retransmission mechanism.
According to an embodiment of the present utility model, described Part II circuit also comprises one or more in following circuit module:
High-speed interface protocol layer, is connected from controller with described DDR;
Digital interface, is connected from controller with described DDR;
Association's processing unit, is connected from controller with described DDR;
Physical layer, is connected with described high-speed interface protocol layer;
ADCs and DACs, be connected with described digital interface;
Audio frequency and video phaselocked loop, produces the second Digital Logic and drives clock to use for other circuit modules in described Part II circuit.
According to an embodiment of the present utility model, described high-speed interface protocol layer is packaged into the data stream packing from high-speed interface application layer to meet the protocol package of interface definition and be sent to described Physical layer; Described digital interface produces the sequential interface of described ADCs and DACs, and sends data to corresponding DACs or from corresponding ADCs, data read in; Described Physical layer comprises SATA Physical layer, USB Physical layer, PCIe Physical layer and/or HDMI Physical layer; Described association processing unit is controlled for operation initialization and the operation of described Part II circuit.
According to an embodiment of the present utility model, described DDR splits data stream or the encapsulation uplink data being merged by a described DDR master controller and Physical layer from controller, wherein, the data stream after fractionation is sent to respectively described the 2nd DDR master controller and Physical layer, high-speed interface protocol layer, ADCs and DACs or described association processing unit.
Compared with prior art, the utlity model has following advantage:
The system level chip of the utility model embodiment is divided into Part I circuit and Part II circuit, Part I circuit is lower to the dependency degree of technique, for example can comprise various SOC digital units, Part II circuit is to giving the dependency degree of lane individual higher, for example can comprise various SOC analog components, wherein Part I circuit and Part II circuit are arranged on different domains, nude film (die), chip (chip) or programming device, connect between the two by the communication interface of SERDES interface, ddr interface and so on.Need to reselect process node due to a variety of causes and again when flow, only need to redesign in Part I circuit and Part II circuit, need to upgrade, one of upgrading, and another in the two can still be continued to use original domain, nude film, chip or programming device, as long as still observing the communication interface specification of original definition between them connects, just can form complete SOC device, thereby significantly reduce design cost, shorten time to market (TTM), reduced flow risk.
Accompanying drawing explanation
Fig. 1 is the system level chip of the utility model the first embodiment and the structured flowchart of coupled external memory storage;
Fig. 2 is the system level chip of the utility model the second embodiment and the structured flowchart of coupled external memory storage;
Fig. 3 is the system level chip of the utility model the 3rd embodiment and the structured flowchart of coupled external memory storage.
Embodiment
In the utility model, each circuit module in traditional SOC chip is divided into two parts: Part I circuit and Part II circuit, two parts are separately positioned on different domains, nude film, chip or programming device, adopt communication interface to connect between the two, this communication interface can be serialization/de-serialization (SERDES) interface, Double Data Rate synchronous DRAM (DDR) interface, or other suitable high-speed interfaces.
Furthermore, the basic norm of dividing is the degree size that relies on manufacturing process, wherein Part I circuit do not rely on concrete manufacturing process or dependency degree lower, for example can comprise various SOC digital units, can also comprise in addition the partial simulation parts that this SOC digital unit relies in order to realize its function; And Part II circuit relies on to a great extent or rely on concrete manufacturing process completely, for example can comprise various SOC analog components, can also comprise in addition the part digital unit that this SOC analog component relies in order to realize its function.
The distribution of Part I circuit and Part II circuit for example can have following situation: Part I circuit and Part II circuit can be arranged on different domains, namely in the different layout area of same nude film (die); Part I circuit and Part II circuit can be arranged on different nude films, and the follow-up modes such as stacked package that can adopt are encapsulated in the two in same chip (chip); Part I circuit and Part II circuit can be arranged on different chips, and the follow-up modes such as printed circuit board (PCB) (PCB) that can adopt couple together the two; One of them is positioned at Part I circuit and Part II circuit on chip, and that another is positioned at programming device (for example FPGA, but be not limited to this) is upper, and the follow-up modes such as printed panel (PCB) that can adopt couple together the two.
It should be noted that no matter adopt above-mentioned any mode, between Part I circuit and Part II circuit, all connect by communication interface, to realize two data interactions between part.This communication interface is preferably SERDES interface and ddr interface, and because the data interaction amount of system level chip is larger, the transmission bandwidth needing is higher, and SERDES and ddr interface can meet the demand of data transfer bandwidth.
Below in conjunction with specific embodiments and the drawings, the utility model is described in further detail, but should not limit protection domain of the present utility model with this.
The first embodiment
With reference to figure 1, the system level chip (or being called system level devices) of the first embodiment is divided into two parts: Part I circuit 100 and Part II circuit 200, the two is arranged on different domains, nude film, chip or programming device, and connect by SERDES interface each other, SERDES correlation technique specification is followed in the data interaction between the two.Wherein, Part I circuit 100 mainly comprises general digital part, for example one or more SOC digital units; Part II circuit 200 mainly comprises SOC high-speed interface and simulation part, for example one or more SOC analog components.
As a preferred embodiment, Part I circuit 100 and Part II circuit 200 are shared same external memory storage 300.External memory storage 300 can be various suitable volatile memory, for example DDR1/2/3, LPDDR etc.
Furthermore, Part I circuit 100 comprises a SERDES interface 101 and the first general SERDES data link layer 102, Part II circuit 200 comprises the 2nd SERDES interface 201 and the second general SERDES data link layer 202, wherein, the first general SERDES data link layer 101 is connected with a SERDES interface 102, the 2nd SERDES interface 201 and SERDES interface 101 physical connections, the second general SERDES data link layer 202 is connected with the 2nd SERDES interface 201.The first general SERDES data link layer 102 and the second general SERDES data link layer 202 can realize the upper-layer protocol of SERDES interface.
Wherein, the one SERDES interface 101 and the 2nd SERDES interface 102 are realizations of high-speed serial I/O, generally include but be not limited to string also/and go here and there device, transmitting-receiving FIFO, receive alignment of data parts, timer manager, transmitting-receiving line interface, line codec and/or passage binding parts.Connection line 1 between the one SERDES interface 101 and the 2nd SERDES interface 201 can be followed LVDS standard, but is not limited to this.
Part II circuit 200 can also comprise Memory Controller Hub and Physical layer (PHY) 203, Memory Controller Hub and Physical layer 203 are connected with the second general SERDES data link layer 202, and Memory Controller Hub and Physical layer 203 can also be connected with external memory storage 300 by rambus 2.
Furthermore, Part I circuit 100 can also comprise on-chip bus 103, issued transaction unit 106, computing unit 107, ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 104, high-speed interface application layer 105, storing communication digital interface 108 and system phaselocked loop 109.It should be noted that, above-mentioned modules is generality signal, and a certain generic module like representative feature or property class, does not represent a certain concrete module or equipment, annexation between each module as shown in Figure 1, represents between described each generic module and has data stream relation.
Wherein, issued transaction unit 106 includes but not limited to central processing unit (CPU), digital signal processor (DSP), counter (TIMER), house dog (WATCHDOG) etc.
Storing communication digital interface 108 includes but not limited to SDMMC digital interface, UART digital interface, SPI digital interface.High-speed interface application layer 105 includes but not limited to USB interface application layer, PCIe interface application layer, SATA interface application layer, HDMI interface application layer, and it inputs or outputs and can be and the mutual application data stream of operating system (OS).
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 104 includes but not limited to the data processing module of audio frequency DAC, the data processing module of video AD C, the data processing module of touch-screen.The function of above-mentioned all kinds of processing modules implement can comprise: video go the functions such as interlacing, convergent-divergent, aftertreatment, the function such as encoding and decoding, aftertreatment of audio frequency, or the application data processing of touch-screen etc.For audio frequency and video, it inputs or outputs is generally more single data stream, can be directly by the next stage processing of data stream; And for other application or module, such as touch-screen etc., its data stream can directly be processed by operating system.
On-chip bus 103 is connected with modules such as the first general SERDES data link layer 102, ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 104, high-speed interface application layer 105, issued transaction unit 106, computing unit 107, storing communication digital interfaces 108.
The first general SERDES data link layer 102 in Part I circuit 100 is by the internal memory operation data stream (shown in line 16) from on-chip bus 103, for various DACs, ADCs data stream 18 used and carry out data fusion from the data stream 11 of high-speed interface application layer 105, data stream after combination of management simultaneously, and set up and guarantee data stream transmission, reception and retransmission mechanism; The first general SERDES data link layer 102 is exactly that the first general SERDES data link layer 102 is connected to a SERDES interface 101 by connecting path 10 for realizing this unified data stream mechanism.
Part II circuit 200 can also comprise: high-speed interface protocol layer 204, digital interface 205, association's processing unit 206, Physical layer (PHYs) 207, ADCs and DACs208, audio frequency and video phaselocked loop 209.Similarly, above-mentioned modules is generality signal, and a certain generic module like representative feature or property class, does not represent a certain concrete module or equipment, and the annexation between each module as shown in Figure 1, represents between described each generic module and has data stream relation.
Wherein, this digital interface 205 includes but not limited to various ADC, DAC and relevant digital interface thereof; Described Physical layer 207 comprises the Physical layer of various HSSI High-Speed Serial Interface and relevant protocol layer.
The second general SERDES data link layer 202 of Part II circuit 200 is connected with a SERDES interface 101 of Part I circuit 201 via the 2nd SERDES interface 201, the second general SERDES data link layer 202 splits the data stream after being merged by the first general SERDES data link layer 102 of Part I circuit 100, or encapsulation uplink data.Data after fractionation are sent to high-speed interface protocol layer 204 separately via data path 25 respectively, or are sent to ADCs and DACs208 via data path 24 and digital interface 205, or are sent to association's processing unit 206 via data path 23.
Wherein the first general SERDES data link layer 102 and the second general SERDES data link layer 103 are symmetrical: can be by decapsulation at Part II circuit 200 through the data stream of encapsulation at Part I circuit 100, and the data stream encapsulating in Part II circuit 200 processes can be by decapsulation at Part I circuit 100.
The system phaselocked loop 109 of Part I circuit 100 drives clock for generation of Digital Logic, and the audio frequency and video phaselocked loop 209 of Part II circuit 200 drives clock for generation of the second Digital Logic.
The digital interface 205 of Part II circuit 200 produces the sequential interface that various DAC/DAC require, and data is sent into corresponding DAC or from corresponding ADC, data are read in.The ADCs of Part II circuit 200 and DACs include but not limited to video DAC, audio ADC, touch-screen ADC etc.
The high-speed interface protocol layer 204 of Part II circuit 200 is packaged into the data stream packing from high-speed interface application layer 105 to meet the protocol package of interface definition separately, and sequential is as requested sent into corresponding Physical layer 207.Wherein, this high-speed interface includes but not limited to SATA, USB, PCIe interface etc.
The Physical layer 207 of Part II circuit 200 includes but not limited to SATA Physical layer, USB Physical layer, PCIe Physical layer, HDMI Physical layer etc.
The Memory Controller Hub of Part II circuit 200 and Physical layer 203 can be correlation control unit and the Physical layers of LPDDR, DDR1/2/3.
Association's processing unit 206 can be used as the interior simple issued transaction of Part II circuit 200 or computing unit, is responsible for operation initialization and the operation of whole Part II circuit 200 and controls.
More specifically, Part II circuit 200 can be applied for by request for arbitration path 3 right to use of rambus 2, by rambus 2 access external memory 300.And Part I circuit 100 can be accessed other all circuit modules except Memory Controller Hub and Physical layer 203 in (comprising reading and writing) Part II circuit 200 by connection line 1 unfetteredly.
In addition, Part I circuit 100 can come via the Memory Controller Hub in Part II circuit 200 and Physical layer 203 access external memory 300 by the right to use of application rambus 2.In Part I circuit 100 access external memory 300 processes, first accessing operation arrives Part II circuit 200 by connection line 1, then isolate the data stream of operational store by the second general SERDES data link layer 202, arrive Memory Controller Hub and Physical layer 203 via data path 21, then can pass through rambus 2 access external memory 300.
The second embodiment
With reference to figure 2, Fig. 2 shows the system level chip of the second embodiment or the structured flowchart of device, similar with the first embodiment, it is divided into two parts: Part I circuit 400 and Part II circuit 500, the two is arranged on different domains, nude film, chip or programming device, and connect by SERDES interface each other, SERDES correlation technique specification is followed in the data interaction between the two.Wherein, Part I circuit 400 mainly comprises general digital part, for example one or more SOC digital units; Part II circuit 500 mainly comprises SOC high-speed interface and simulation part, for example one or more SOC analog components.
As a preferred embodiment, Part I circuit 400 and Part II circuit 500 are shared same external memory storage 600.External memory storage 600 can be various volatile memory, for example DDR1/2/3, LPDDR etc.
Furthermore, Part I circuit 400 can comprise a SERDES interface 401, the first general SERDES data link layer 402 and Memory Controller Hub and Physical layer 410, Part II circuit 500 comprises the 2nd SERDES interface 501 and the second general SERDES data link layer 502, wherein, the first general SERDES data link layer 401 is connected with a SERDES interface 402, the 2nd SERDES interface 501 and SERDES interface 401 physical connections, the second general SERDES data link layer 502 is connected with the 2nd SERDES interface 501.The first general SERDES data link layer 402 and the second general SERDES data link layer 502 can realize the upper-layer protocol of SERDES interface.
Memory Controller Hub and Physical layer (PHY) 410, it is connected with the first general SERDES data link layer 402, and Memory Controller Hub and Physical layer 410 can also be connected with external memory storage 600 by rambus 2.
With the first embodiment similarly, Part I circuit 400 can also comprise on-chip bus 403, issued transaction unit 406, computing unit 407, ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 404, high-speed interface application layer 405, storing communication digital interface 408 and system phaselocked loop 409.
Part II circuit 500 can also comprise: high-speed interface protocol layer 504, digital interface 505, association's processing unit 506, Physical layer (PHYs) 507, ADCs and DACs508, audio frequency and video phaselocked loop 509.
The annexation of above-mentioned modules and function thereof refer to the associated description in the first embodiment, repeat no more here.
More specifically, Part I circuit 400 can pass through rambus 2 access external memory 300.In addition, Part I circuit 400 can be accessed all circuit modules in (comprising reading and writing) Part II circuit 500 by connection line 1 unfetteredly.
In addition, Part II circuit 500 can be via the Memory Controller Hub in Part I circuit 400 and Physical layer 410 access external memory 600.In Part II circuit 500 access external memory 600 processes, first accessing operation arrives Part I circuit 400 by connection line 1, then isolate the data stream of operational store by the first general SERDES data link layer 402, arrive Memory Controller Hub and Physical layer 410 via data path 19, then can pass through rambus 2 access external memory 600.
The 3rd embodiment
With reference to figure 3, Fig. 3 shows the 3rd system level chip of embodiment or the structured flowchart of device, similar with the first and second embodiment, it is divided into two parts: Part I circuit 700 and Part II circuit 800, the two is arranged on different domains, nude film, chip or programming device, and connect by ddr interface each other, DDR correlation technique specification is followed in the data interaction between the two.Wherein, Part I circuit 700 mainly comprises general digital part, for example one or more SOC digital units; Part II circuit 800 mainly comprises SOC high-speed interface and simulation part, for example one or more SOC analog components.
As a preferred embodiment, Part I circuit 700 and Part II circuit 800 are shared same external memory storage 900.External memory storage 900 can be various volatile memory, for example DDR1/2/3, LPDDR etc.
Furthermore, Part I circuit 700 can comprise a DDR master controller and Physical layer 701; Part II circuit 800 comprises: DDR is from controller 801, the 2nd DDR master controller and Physical layer 802.Wherein, DDR is connected with a DDR master controller and Physical layer 701 from controller 801, and the 2nd DDR master controller and Physical layer 802 are connected from controller 801 with DDR, and the 2nd DDR master controller and Physical layer 802 are connected with external memory storage 900 by rambus 2.
Furthermore, Part I circuit 700 can also comprise on-chip bus 703, issued transaction unit 706, computing unit 707, ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 704, high-speed interface application layer 705, storing communication digital interface 708, system phaselocked loop 709.It should be noted that, above-mentioned modules is generality signal, and a certain generic module like representative feature or property class, does not represent a certain concrete module or equipment, annexation between each module as shown in Figure 3, represents between described each generic module and has data stream relation.
Wherein, issued transaction unit 706 includes but not limited to central processing unit (CPU), digital signal processor (DSP), counter (TIMER), house dog (WATCHDOG) etc.Computing unit 707 includes but not limited to graphics calculations unit, video computing unit, encryption and decryption computing unit etc.Storing communication digital interface 708 includes but not limited to SDMMC digital interface, UART digital interface, SPI digital interface.High-speed interface application layer 705 includes but not limited to USB interface application layer, PCIe interface application layer, SATA interface application layer, HDMI interface application layer, and it inputs or outputs and can be and the mutual application data stream of operating system (OS).
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 704 includes but not limited to the data processing module of audio frequency DAC, the data processing module of video AD C, the data processing module of touch-screen.The function of above-mentioned all kinds of processing modules implement can comprise: video go the functions such as interlacing, convergent-divergent, aftertreatment, the function such as encoding and decoding, aftertreatment of audio frequency, or the application data processing of touch-screen etc.For audio frequency and video, it inputs or outputs is generally more single data stream, can be directly by the next stage processing of data stream; And for other application or module, such as touch-screen etc., its data stream can directly be processed by operating system.
On-chip bus 703 can be connected with a DDR master controller and Physical layer 701, issued transaction unit 706, computing unit 707, ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer 704, high-speed interface application layer 705 and storing communication digital interface 708.
Part II circuit 800 can also comprise: high-speed interface protocol layer 804, digital interface 805, association's processing unit 806, Physical layer 807, ADCs and DACs808, similarly, above-mentioned modules is generality signal, a certain generic module like representative feature or property class, do not represent a certain concrete module or equipment, annexation between each module as shown in Figure 3, represents between described each generic module and has data stream relation.
Wherein, high-speed interface protocol layer 804, digital interface 805, association's processing unit 806 are connected from controller 801 with DDR, association's processing unit 806 is also connected with the 2nd DDR master controller and Physical layer 802, Physical layer 807 is connected with high-speed interface protocol layer 804, and ADCs is connected with digital interface 805 with DACs808.
This digital interface 805 includes but not limited to various ADC, DAC and relevant digital interface thereof; Described Physical layer 207 comprises the Physical layer of various HSSI High-Speed Serial Interface and relevant protocol layer.
DDR splits the data stream being merged by a DDR master controller of Part I circuit 700 and Physical layer 701 from controller 801, or encapsulation uplink data.Data after fractionation are sent to high-speed interface protocol layer 804 separately via data path 25 respectively, or are sent to ADCs and DACs808 via data path 24 and digital interface 805, or are sent to association's processing unit 206 via data path 23.
The system phaselocked loop 709 of Part I circuit 700 drives clock for generation of Digital Logic, and the audio frequency and video phaselocked loop 809 of Part II circuit 800 drives clock for generation of the second Digital Logic.
The digital interface 805 of Part II circuit 800 produces the sequential interface that various DAC/DAC require, and data is sent into corresponding DAC or from corresponding ADC, data are read in.The ADCs of Part II circuit 800 and DACs include but not limited to video DAC, audio ADC, touch-screen ADC etc.
The high-speed interface protocol layer 804 of Part II circuit 800 is packaged into the data stream packing from high-speed interface application layer 805 to meet the protocol package of interface definition separately, and sequential is as requested sent into corresponding Physical layer 807.Wherein, this high-speed interface includes but not limited to SATA, USB, PCIe interface etc.
The Physical layer 807 of Part II circuit 800 includes but not limited to SATA Physical layer, USB Physical layer, PCIe Physical layer, HDMI Physical layer etc.
Association's processing unit 806 can be used as the interior simple issued transaction of Part II circuit 800 or computing unit, is responsible for operation initialization and the operation of whole Part II circuit 800 and controls.
More specifically, Part I circuit 700 can be applied for by request for arbitration path 3 right to use of rambus 2, by rambus 2 access external memory 900.In addition, Part I circuit 700 can be accessed all circuit modules in (comprising reading and writing) Part II circuit 800 by connecting path 1 unfetteredly.
In addition, Part I circuit 700 can visit external memory storage 900 via the DDR in Part II circuit 800 from controller 801 and the 2nd DDR master controller and Physical layer 802 by the right to use of application rambus 2.In Part II circuit 800 access external memory 900 processes, first accessing operation arrives Part II circuit 800 by connecting path 1, then arrive the 2nd DDR master controller and Physical layer 802 by DDR from controller 801, then can pass through rambus 2 access external memory 900.
In addition, the present embodiment also provides a kind of system-Level IC Design method, comprise the steps: each circuit module to be divided into Part I circuit and Part II circuit, described Part I circuit comprises one or more SOC digital units, and described Part II circuit comprises one or more SOC analog components; Described Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device, between described Part I circuit and Part II circuit, connect by communication interface, this communication interface is preferably the high-speed interfaces such as SERDES interface, ddr interface.
Wherein, Part I circuit definitely depends on manufacturing process or dependency degree is higher comparatively speaking, and Part II circuit is relatively lower to the dependency degree of manufacturing process.Part I main circuit will comprise various digital units, but also the analog component that depends on the digital unit in Part I circuit can be arranged in Part I circuit simultaneously; Part II main circuit will comprise various analog components, but also the digital unit that depends on the analog component in Part II circuit can be arranged in Part II circuit simultaneously.
Above-mentioned SOC method for designing mainly consider the upgrading that is a little chip time low-risk, low cost, and considering of traditional SOC is a little integrated level.Above-mentioned SOC method for designing is two parts by the modules of SOC or equipment according to the different demarcation of the degree that depends on manufacturing process: Part I circuit and Part II circuit.
Wherein Part I circuit does not rely on concrete manufacturing process conventionally to a certain extent, conventionally can occur with the form of descriptive language (as RTL), through forming the domain of manufacturing after comprehensive, placement-and-routing, change, the upgrading of technique are little on its design impact; And authorize IP for third party, can not produce extra-pay yet.
Part II circuit depends on concrete manufacturing process conventionally to a great extent, conventionally can directly provide design with the form of domain, and the change of technique, upgrading, be all huge on the impact of its design; Authorize IP for third party, need to regain mandate, these designs or mandate expense are huge, also bring in addition flow risk thereupon.
It should be noted that, the division of Part I circuit and second circuit can be finely tuned according to the realization of function, for example, in Part I circuit, also can comprise necessary analog module, drive the system PLL of clock as produced the first Digital Logic, connect the general SERDES data link layer of Part I circuit and Part II circuit, and in Part II circuit, also can have the digital module of various necessity.Be present in the analog component in Part I circuit and be present in the digital unit in Part II circuit, its objective is that the function in order to make the part at place is separately more independent, but not making the function of place part separately more comprehensive.
To sum up, adopt system level chip of the present utility model or device and method for designing tool thereof to have the following advantages: by traditional SOC chip is divided into Part I circuit and Part II circuit, make cost and the flow risk of two parts circuit controlled, while making SOC change, upgrade at process node, can exchange time to market (TTM) fast for very little cost and risk cost.
What should be understood that is that above-described embodiment is just to explanation of the present utility model; rather than to restriction of the present utility model; any utility model not exceeding within the scope of the utility model connotation is created; include but not limited to the change to local structure, the type to components and parts or the replacement of model; and the replacement of other unsubstantialities or modification, within all falling into the utility model protection domain.
Claims (16)
1. a system level chip, is characterized in that, comprises Part I circuit and Part II circuit, wherein,
Described Part I circuit comprises one or more SOC digital units;
Described Part II circuit comprises one or more SOC analog components;
Described Part I circuit and Part II circuit are arranged on different domains, nude film, chip or programming device, between described Part I circuit and Part II circuit, connect by communication interface.
2. system level chip according to claim 1, is characterized in that, described Part I circuit and Part II circuit are shared same external memory storage.
3. system level chip according to claim 2, is characterized in that, described communication interface is SERDES interface,
Described Part I circuit comprises:
The one SERDES interface;
The first general SERDES data link layer, is connected with a described SERDES interface;
Described Part II circuit comprises:
The 2nd SERDES interface, with a described SERDES interface physical connection;
The second general SERDES data link layer, is connected with described the 2nd SERDES interface;
Memory Controller Hub and Physical layer, be connected with described the second general SERDES data link layer, and described Part II circuit is connected with described external memory storage via rambus;
Wherein, described Part I circuit, by the right to use of the described rambus of application, is accessed described external memory storage via described the first general SERDES data link layer, a SERDES interface, the 2nd SERDES interface, the second general SERDES data link layer, Memory Controller Hub and Physical layer and rambus; Described Part II circuit, by the right to use of the described rambus of application, is accessed described external memory storage via described Memory Controller Hub and Physical layer and rambus.
4. system level chip according to claim 2, is characterized in that, described communication interface is SERDES interface,
Described Part I circuit comprises:
The one SERDES interface;
The first general SERDES data link layer, is connected with a described SERDES interface;
Memory Controller Hub and Physical layer, be connected with described the first general SERDES data link layer, and described Part I circuit is connected with described external memory storage via rambus;
Described Part II circuit comprises:
The 2nd SERDES interface, with a described SERDES interface physical connection;
The second general SERDES data link layer, is connected with described the 2nd SERDES interface;
Wherein, described Part I circuit is accessed described external memory storage via described rambus; Described Part II circuit is accessed described external memory storage via described the second general SERDES data link layer, the 2nd SERDES interface, a SERDES interface, the first general SERDES data link layer and Memory Controller Hub and Physical layer and rambus.
5. according to the system level chip described in claim 3 or 4, it is characterized in that, described Part I circuit also comprises:
On-chip bus, is connected with described the first general SERDES data link layer;
Issued transaction unit and computing unit, be connected with described on-chip bus, and this issued transaction unit and computing unit are via Part II circuit described in described on-chip bus, the first general SERDES data link layer and a SERDES interface accessing.
6. system level chip according to claim 5, it is characterized in that, described issued transaction unit comprises central processing unit, digital signal processor, counter and/or house dog, and described computing unit comprises: graphics calculations unit, video computing unit and/or encryption and decryption computing unit.
7. system level chip according to claim 5, is characterized in that, described Part I circuit also comprises one or more in following circuit module:
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer, is connected and is connected with on-chip bus with described the first general SERDES data link layer:
High-speed interface application layer, is connected with on-chip bus with described the first general SERDES data link layer;
Storing communication digital interface, is connected with described on-chip bus;
System phaselocked loop, produces the first Digital Logic and drives clock to use for other circuit modules in described Part I circuit.
8. system level chip according to claim 7, is characterized in that, described ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer comprises data processing module, the data processing module of video AD C and/or the data processing module of touch-screen of audio frequency DAC; Described high-speed interface application layer comprises USB interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI interface application layer; Described storing communication digital interface comprises SDMMC digital interface, UART digital interface and/or SPI digital interface.
9. according to the system level chip described in claim 3 or 4, it is characterized in that, described Part II circuit also comprises one or more in following circuit module:
High-speed interface protocol layer, is connected with described the second general SERDES data link layer;
Digital interface, is connected with described the second general SERDES data link layer;
Association's processing unit, is connected with described the second general SERDES data link layer;
Physical layer, is connected with described high-speed interface protocol layer;
ADCs and DACs, be connected with described digital interface;
Audio frequency and video phaselocked loop, produces the second Digital Logic and drives clock to use for other circuit modules in described Part II circuit.
10. according to the system level chip described in claim 3 or 4, it is characterized in that, a described SERDES interface and the 2nd SERDES interface comprise string also/and go here and there device, transmitting-receiving FIFO, receive alignment of data parts, timer manager, transmitting-receiving line interface, line codec and/or passage binding parts.
11. system level chips according to claim 2, is characterized in that, described communication interface is ddr interface, and described Part I circuit comprises:
The one DDR master controller and Physical layer;
Described Part II circuit comprises:
DDR, from controller, is connected with a described DDR master controller and Physical layer;
The 2nd DDR master controller and Physical layer, is connected from controller with described DDR, and described DDR master controller and Physical layer are connected with external memory storage via rambus;
Wherein, described Part I circuit, by the right to use of the described rambus of application, is accessed described external memory storage via a described DDR master controller and Physical layer, DDR from controller, the 2nd DDR master controller and Physical layer and rambus; Described Part II circuit, by the right to use of the described rambus of application, is accessed described external memory storage via described the 2nd DDR master controller and Physical layer and rambus.
12. system level chips according to claim 11, is characterized in that, described Part I circuit also comprises:
On-chip bus, is connected with a described DDR master controller and Physical layer;
Issued transaction unit and computing unit, be connected with described on-chip bus, and this issued transaction unit and computing unit are accessed described Part II circuit via described on-chip bus and a DDR master controller and physical layer interface.
13. system level chips according to claim 12, it is characterized in that, described issued transaction unit comprises central processing unit, digital signal processor, counter and/or house dog, and described computing unit comprises: graphics calculations unit, video computing unit and/or encryption and decryption computing unit.
14. system level chips according to claim 12, is characterized in that, described Part I circuit also comprises one or more in following circuit module:
ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer, is connected with described on-chip bus and a DDR master controller and Physical layer:
High-speed interface application layer, is connected with described on-chip bus and a DDR master controller and Physical layer;
Storing communication digital interface, is connected with described on-chip bus;
System phaselocked loop, produces the first Digital Logic and drives clock to use for other circuit modules in described Part I circuit.
15. system level chips according to claim 14, is characterized in that, described ADCs/DACs Apple talk Data Stream Protocol Apple Ta layer comprises data processing module, the data processing module of video AD C and/or the data processing module of touch-screen of audio frequency DAC; Described high-speed interface application layer comprises USB interface application layer, PCIe interface application layer, SATA interface application layer and/or HDMI interface application layer; Described storing communication digital interface comprises SDMMC digital interface, UART digital interface and/or SPI digital interface.
16. system level chips according to claim 11, is characterized in that, described Part II circuit also comprises one or more in following circuit module:
High-speed interface protocol layer, is connected from controller with described DDR;
Digital interface, is connected from controller with described DDR;
Association's processing unit, is connected from controller with described DDR;
Physical layer, is connected with described high-speed interface protocol layer;
ADCs and DACs, be connected with described digital interface;
Audio frequency and video phaselocked loop, produces the second Digital Logic and drives clock to use for other circuit modules in described Part II circuit.
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| CN201320890323.3U CN203644037U (en) | 2013-12-31 | 2013-12-31 | System-level chip |
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| CN201320890323.3U CN203644037U (en) | 2013-12-31 | 2013-12-31 | System-level chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678250A (en) * | 2013-12-31 | 2014-03-26 | 苏州君嬴电子科技有限公司 | SOC (system on chip) and design method for same |
| CN108736911A (en) * | 2017-04-25 | 2018-11-02 | 扬智科技股份有限公司 | Multi-chip connects circuit |
-
2013
- 2013-12-31 CN CN201320890323.3U patent/CN203644037U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678250A (en) * | 2013-12-31 | 2014-03-26 | 苏州君嬴电子科技有限公司 | SOC (system on chip) and design method for same |
| CN103678250B (en) * | 2013-12-31 | 2017-04-05 | 赵建东 | System level chip and its method for designing |
| CN108736911A (en) * | 2017-04-25 | 2018-11-02 | 扬智科技股份有限公司 | Multi-chip connects circuit |
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Effective date of registration: 20160912 Address after: Hangzhou City, Zhejiang Province, the 310000 Academy Xihu District Tsui village two district Chunxiao Garden Room 1201 8 Patentee after: Zhao Jiandong Address before: Suzhou City, Jiangsu Province, Suzhou Industrial Park 215124 Xinghu Street No. 328 Creative Industry Park 1-B602 unit Patentee before: Suzhou Junying Electronic Technology Co., Ltd. |
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