CN103678210A - High-speed interface control device capable of improving efficiency and data transmission method - Google Patents
High-speed interface control device capable of improving efficiency and data transmission method Download PDFInfo
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- CN103678210A CN103678210A CN201210364235.XA CN201210364235A CN103678210A CN 103678210 A CN103678210 A CN 103678210A CN 201210364235 A CN201210364235 A CN 201210364235A CN 103678210 A CN103678210 A CN 103678210A
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Abstract
The invention discloses a high-speed interface control device capable of improving efficiency and a data transmission method. The method mainly comprises the steps that connection is established between a high-speed interface of a first host and a high-speed interface of a second host, a first transmission mode and a second transmission mode are executed synchronously, the first transmission mode and the second transmission mode respectively receive instructions and judge whether the first (second) host sends the instructions for data transmission, if yes, two transmission channels are provided, one transmission channel transmits a chip control instruction to the second (first ) host, and the other transmission channel is used for transmitting data to the second (first) host. According to the technology, data can be transmitted and received between the two hosts in a full duplex mode, and therefore the data transmission efficiency is greatly improved.
Description
Technical field
The present invention relates to a kind of high-speed interface control device and data transmission method, espespecially a kind of high-speed communication interface that makes is realized full duplex transmission data, with the correlation technique of effective promoting data transmission efficiency.
Background technology
Along with scientific and technological progress, the transmission interface of many high speeds comes out successively.With universal serial bus (Universal Serial Bus, hereinafter to be referred as USB) development course can reflect on market the demand for communication interface transmission speed, the USB 1.0 that USB comes out is the earliest low-speed interfaces, its transmitting bandwidth only has 1.5Mbps, then the USB 1.1 coming out, maximum transmitted frequency range rises to 12Mbps, has arrived USB 2.0, and its maximum transmitted frequency range is 480Mbps.In USB 2.0 epoch prevailing, be further promoting data transmission efficiency, be someone proposes to utilize USB2.0 to make two main frames (Host) can transmit mutually the technology of data.But along with high-speed transmission interface and the arriving in Large Volume Data transmission epoch, utilize USB2.0 to carry out two-way data transmission and between two main frames, transmit the technology of data transmission, do not met the market demand.And up-to-date USB 3.0 versions have risen to 5Gbps by transmitting bandwidth by 480Mbps significantly, its pin position sequence number and signal definition are as following:
1?VBUS
2?D-
3?D+
4?GND
5?StdA_SSRX-
6?StdA_SSRX+
7?GND_DRAIN
8?StdA_SSTX-
9?StdA_SSTX+
From the above, USB 3.0 has retained outside downward compatible pin position (VBUS, D-, D+, GND), further expands one group and receives at a high speed pin position (StdA_SSRX-, StdA_SSRX+) and one group of high-speed transfer pin position (StdA_SSTX-, StdA_SSTX+).Its meaning can be transmitted data on USB 3.0, also can receive data, but in fact the data-transmission mode of USB 3.0 only terminates in half-duplex.Though being USB 3.0, meaning configured receiving cable and Transfer pipe simultaneously, this receiving cable and Transfer pipe can not receive and send data simultaneously, when receiving cable receives data, by the time after receiving cable receives data, could transmit data by Transfer pipe, therefore in fact only have half-duplex.Identical situation also occurs on other high-speed transmission interface, for example eSATA, PCI-Express.
From the above, though existing high-speed transmission interface significantly promotes in transmitting bandwidth and speed, precisely because receiving cable and Transfer pipe still cannot be realized real full duplex, with regard to the transfer efficiency of data, have the space further promoting by oneself.
Summary of the invention
In view of existing high-speed transmission interface still cannot be realized full duplex, so that affect its data transmission efficiency, therefore fundamental purpose of the present invention is providing a kind of high-speed interface control device and data transmission method that promotes usefulness, it can make existing high-speed transmission interface realize full duplex, with effective improving data transmission efficiency.
For reaching the technical way that aforementioned object takes, be to make the aforementioned high-speed interface data transmission method that promotes usefulness, be mainly to set up line between the high-speed interface of one first main frame and one second main frame, and synchronously carry out one first transmission mode and one second transmission mode: wherein:
The first transmission mode comprises:
Receive and judge whether the first main frame sends the order that transmits data;
If so, two Transfer pipes are provided, and wherein a Transfer pipe transmits a chip controls order (Vendor Command) to the second main frame, and another Transfer pipe is in order to transmit data to the second main frame;
The second transmission mode comprises:
Receive and judge whether the second main frame sends the order that transmits data;
If so, two Transfer pipes are provided, and wherein a Transfer pipe transmits a chip controls order (Vendor Command) to the first main frame, and another Transfer pipe is in order to transmit data to the first main frame.
For reaching the another technical way that aforementioned object takes, be to make the aforementioned high-speed interface control device that promotes usefulness comprise:
One first host interface port, has one first receiving port and one first delivery port;
One second host interface port, has one second receiving port and one second delivery port;
One control module, a built-in transfer protocol control program, and there is one first main frame connectivity port and one second main frame connectivity port;
One first main frame buffer cell, is connected between the first main frame connectivity port and the first host interface port of control module; This first main frame buffer cell comprises one first instruction buffer, one first data output buffer, the first Input Data Buffer and the first controller buffer; Wherein, the first instruction buffer, the first data output buffer are connected with the first delivery port respectively; The first Input Data Buffer, the first controller buffer are connected with the first receiving port respectively;
One second main frame buffer cell, is connected between the second main frame connectivity port and the second host interface port of control module; This second main frame buffer cell comprises one second instruction buffer, one second data output buffer, the second Input Data Buffer, the second controller buffer; Wherein, the second instruction buffer, the second data output buffer are connected with the second delivery port respectively; The second Input Data Buffer, the second controller buffer are connected with the second receiving port respectively.
Aforementioned control device is connected with one first main frame and one second main frame respectively with first, second host interface port, uses and supports the first main frame and the second main frame while and reciprocally transmit and receive data, this control device will be by first, first of the second main frame buffer cell, the second instruction buffer receives first, the transfer data command that the second main frame is sent, and confirmed by control module judgement, if the first main frame is sent transfer data command, by the first instruction buffer, the second controller buffer provides a Transfer pipe, to transmit a chip controls instruction, to the second host notification, it receives data, simultaneously by the first data output buffer, the second Input Data Buffer provides another Transfer pipe, the data that the first main frame is sent send data to second main frame through the second receiving port, the same time, if the second main frame is also sent transfer data command, by the second instruction buffer, the first controller buffer, provide a Transfer pipe, it receives data to the first host notification through the first receiving port, to transmit chip controls instruction, simultaneously by the second data output buffer, the first Input Data Buffer, provide another Transfer pipe, through the first receiving port of the first host interface port, send data to first main frame, utilize above-mentioned technology can make first, second main frame transmit simultaneously and receive data via high-speed interface, the improving data transmission efficiency to realize full duplex.
Below in conjunction with the drawings and specific embodiments, describe the present invention, but not as a limitation of the invention.
Accompanying drawing explanation
The circuit block diagram of Fig. 1 the present invention the first preferred embodiment;
The schematic diagram that Fig. 2 the present invention the first preferred embodiment is connected with main frame;
The circuit block diagram of Fig. 3 the present invention the second preferred embodiment.
Wherein, Reference numeral
10 first host interface port 11 first delivery port
12 first receiving ports
20 second host interface port 21 second delivery port
22 second receiving ports
30 control module 31 ~ 38 chip controllers
40 first main frame buffer cells
41 first instruction buffers
42 first data output buffers
43 first Input Data Buffers
44 first controller buffers
45 the 3rd instruction buffers
46 the 3rd data output buffers
47 the 3rd Input Data Buffers
48 the 3rd controller buffers
50 second main frame buffer cells
51 second instruction buffers
52 second data output buffers
53 second Input Data Buffers
54 second controller buffers
55 the 4th instruction buffers
56 the 4th data output buffers
57 the 4th Input Data Buffers
58 the 4th controller buffers
60 the 3rd host interface port 61 the 3rd delivery port
62 the 3rd receiving ports
70 the 4th host interface port 71 the 4th delivery port
72 the 4th receiving ports
Embodiment
Concrete structure about a preferred embodiment of the present invention, refers to shown in Fig. 1, and it comprises one first host interface port 10, one second host interface port 20, a control module 30, one first main frame buffer cell 40 and one second main frame buffer cell 50; Wherein:
This first host interface port 10 has one first receiving port 12 and one first delivery port 11, in order to be connected with one first main frame (this is not shown in the figures) by a high-speed communication interface agreement (hereinafter to be referred as high-speed interface), this the second host interface port 20 has one second receiving port 22 and one second delivery port 21, in order to the high-speed interface by identical, is connected with one second main frame (also not showing in this figure); Alleged high-speed interface refers to the high-speed serial bus with independent transmission end, receiving end, it includes but not limited to: USB 3.0, eSATA, PCI-Express etc., for convenience of description, below will take USB 3.0 as example, aforementioned first, second receiving port 12,22 refer to receiving end StdA_SSRX-, the StdA_SSRX+ of USB 3.0, and aforementioned first, second delivery port 11,21 refers to transmission end StdA_SSTX-, the StdA_SSTX+ of USB 3.0.
The built-in transfer protocol control program of this control module 30, and there is one first main frame connectivity port and one second main frame connectivity port, this the first main frame connectivity port is in order to connect the first host interface port 10, the second main frame connectivity ports in order to connect the second main frame connectivity port 20; This control module 30 can be single microprocessor, also can be comprised of a plurality of interconnective chip controller, and in the present embodiment, this control module 30 is comprised of 31 ~ 34 of a plurality of chip controllers.
This first main frame buffer cell 40 comprises one first instruction buffer 41, one first data output buffer 42, the first Input Data Buffer 43 and the first controller buffer 44; Wherein, the input end of the first instruction buffer 41, the first data output buffer 42 is connected with the first delivery port 11 respectively, and its output terminal is connected to respectively the chip controller 33,34 of control module 30; The output terminal of the first Input Data Buffer 43, the first controller buffer 44 is connected with the first receiving port 12 respectively, and its input end is connected to the chip controller 31,32 of control module 30.
This second main frame buffer cell 50 comprises one second instruction buffer 51, one second data output buffer 52, the second Input Data Buffer 53, the second controller buffer 54; Wherein, the input end of the second instruction buffer 51, the second data output buffer 52 is connected with the second delivery port 21 respectively, and its output terminal connects with the chip controller 31,32 of control module 30; The input end of the second Input Data Buffer 53, the second controller buffer 54 connects with the chip controller 33,34 of control module 30 respectively, and its output terminal is connected with the second receiving port 22 respectively.
Refer to shown in Fig. 2, after aforementioned means is connected with USB 3.0 interface ports of one first main frame Host 1, one second main frame Host 2 respectively with the first host interface port 10, the second host interface port 20, control module 30 utilizes the first instruction buffer 41 to receive instruction or order that the first main frame Host 1 sends according to built-in transfer protocol control program, and by the second controller buffer 54, transmits a chip controls order (Vendor Command) and give the second main frame Host 2 through the second receiving port 22; Utilize again the first data output buffer 42 to receive from the first delivery port 11 data that the first main frame Host 1 sends, then through the second receiving port 22, give the second main frame Host 2 via the second Input Data Buffer 53.In other words, when control module 30 is received the transfer data command that the first main frame Host 1 sends, to provide a Transfer pipe by the first instruction buffer 41, the second controller buffer 54, with the instruction of transmission chip controls, give the second main frame Host 2 to notify it to receive data, by the first data output buffer 42, the second Input Data Buffer 53, provide another Transfer pipe, the data that the first main frame Host 1 is sent via the first delivery port 11 send the second main frame Host 2 to through the second receiving port 22 simultaneously.
And control module 30 also judges whether the second main frame Host 2 sends transfer data command simultaneously, if the second main frame Host 2 also sends transfer data command, by the second instruction buffer 51, the first controller buffer 44, provide a Transfer pipe, through the first receiving port 12, transmitting chip controls instruction notifies it to receive data to the first main frame Host 1, simultaneously by the second data output buffer 52, the first Input Data Buffer 43, form another Transfer pipe, through the first receiving port 12 of the first host interface port 10, send data to first main frame Host 1.
Therefore from the above, under the controlling of control module 30, the first main frame Host 1 and the second main frame Host 2 can be side by side sending and receiving data mutually, and realize full-duplex mode, by this effective improving data transmission efficiency.
By above-mentioned explanation, can be understood concrete technical characterictic and the principle of work thereof of a preferred embodiment of the present invention, for affiliated technical field, have and conventionally know that the knowledgeable is understandable that: the high-speed interface control device that above-described embodiment discloses is a least unit, it is connected between two main frames, make two main frames can full duplex ground sending and receiving data mutually at the same time.According to above-mentioned framework, described high-speed interface control device can be expanded depending on actual needs, at the impact damper that increases in couples host interface port and first, second main frame buffer cell 40,50, and expand control module 30 (for example increasing chip controller quantity), can increase the quantity that connects main frame.As shown in Figure 3, be that host interface port, the impact damper of first, second main frame buffer cell 40,50 and the chip controller of control module 30 according to previous embodiment respectively expands one times, wherein
This first main frame buffer cell 40 is except original the first instruction buffer 41, the first data output buffer 42, the first Input Data Buffer 43 and the first controller buffer 44; Expanding in addition one group comprises: the 3rd instruction buffer 45, the 3rd data output buffer 46 the 3rd Input Data Buffer 47 and the 3rd controller buffer 48, the chip controller 35 ~ 38 that its respectively with three host interface port 60 and control module 30 expand is connected.
This second main frame buffer cell 50 is except original the second instruction buffer 51, the second data output buffer 52, the second Input Data Buffer 53 and the second controller buffer 54; Expanding in addition one group comprises: the 4th instruction buffer 55, the 4th data output buffer 56, the 4th Input Data Buffer 57 and the 4th controller buffer 58, the chip controller 35 ~ 38 that its respectively with four host interface port 70 and control module 30 expand is connected.
After expanding, except supporting the first main frame Host 1 and the second main frame Host 2 full duplexs ground mutually sending and receiving data, also support simultaneously the 3rd main frame Host 3 and the 4th main frame Host 4 with full duplex mode to biography data.
Certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (8)
1. the high-speed interface control device that can promote usefulness, is characterized in that, comprising:
One first host interface port, has one first receiving port and one first delivery port;
One second host interface port, has one second receiving port and one second delivery port;
One control module, has one first main frame connectivity port and one second main frame connectivity port;
One first main frame buffer cell, is connected between the first main frame connectivity port and the first host interface port of control module; This first main frame buffer cell comprises one first instruction buffer, one first data output buffer, the first Input Data Buffer and the first controller buffer; Wherein, the first instruction buffer, the first data output buffer are connected with the first delivery port respectively; The first Input Data Buffer, the first controller buffer are connected with the first receiving port respectively;
One second main frame buffer cell, is connected between the second main frame connectivity port and the second host interface port of control module; This second main frame buffer cell comprises one second instruction buffer, one second data output buffer, the second Input Data Buffer, the second controller buffer; Wherein, the second instruction buffer, the second data output buffer are connected with the second delivery port respectively; The second Input Data Buffer, the second controller buffer are connected with the second receiving port respectively;
By this, this control module will be controlled first, second main frame buffer cell, make first, second host interface port by side by side sending and receiving data of first, second main frame buffer cell.
2. the high-speed interface control device that can promote according to claim 1 usefulness, is characterized in that, this first, second host interface port is a high-speed serial bus.
3. the high-speed interface control device that can promote according to claim 2 usefulness, is characterized in that, this first, second host interface port is PCI-Express.
4. the high-speed interface control device that can promote according to claim 2 usefulness, is characterized in that, this first, second host interface port is eSATA.
5. the high-speed interface control device that can promote according to claim 2 usefulness, is characterized in that, this first, second host interface port is USB 3.0.
6. according to the high-speed interface control device that can promote usefulness described in any one in claim 1 to 5, it is characterized in that, this control module is consisted of a microprocessor.
7. according to the high-speed interface control device that can promote usefulness described in any one in claim 1 to 5, it is characterized in that, this control module is mainly comprised of a plurality of chip controllers, each chip controller interconnecting line and being connected with the second instruction buffer, one second data output buffer, the second Input Data Buffer, second controller buffer of the first instruction buffer, one first data output buffer, the first Input Data Buffer, the first controller buffer and the second main frame buffer cell of the first main frame buffer cell respectively.
8. can promote a high-speed interface data transmission method for usefulness, be mainly to set up line between the high-speed interface of one first main frame and one second main frame, and synchronously carry out one first transmission mode and one second transmission mode: it is characterized in that,
The first transmission mode comprises:
Receive and judge whether the first main frame sends the order that transmits data;
If so, two Transfer pipes are provided, and wherein a Transfer pipe transmits a chip controls order to the second main frame, and another Transfer pipe is in order to transmit data to the second main frame;
The second transmission mode comprises:
Receive and judge whether the second main frame sends the order that transmits data;
If so, two Transfer pipes are provided, and wherein a Transfer pipe transmits a chip controls order to the first main frame, and another Transfer pipe is in order to transmit data to the first main frame.
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| CN201210364235.XA CN103678210A (en) | 2012-09-26 | 2012-09-26 | High-speed interface control device capable of improving efficiency and data transmission method |
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| CN201210364235.XA CN103678210A (en) | 2012-09-26 | 2012-09-26 | High-speed interface control device capable of improving efficiency and data transmission method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110967929A (en) * | 2018-09-30 | 2020-04-07 | 深圳市印之明科技有限公司 | System and method for adjusting light spot dislocation scanning time sequence of photoetching machine |
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| US7162566B2 (en) * | 2003-08-07 | 2007-01-09 | Ali Corporation | USB-based host-to-host networking method |
| US7921252B1 (en) * | 2007-07-26 | 2011-04-05 | Akros Silicon Inc. | USB integrated bidirectional digital isolator channel across an interface between two USB devices |
| US8090894B1 (en) * | 2007-09-21 | 2012-01-03 | Cypress Semiconductor Corporation | Architectures for supporting communication and access between multiple host devices and one or more common functions |
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- 2012-09-26 CN CN201210364235.XA patent/CN103678210A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7162566B2 (en) * | 2003-08-07 | 2007-01-09 | Ali Corporation | USB-based host-to-host networking method |
| US7921252B1 (en) * | 2007-07-26 | 2011-04-05 | Akros Silicon Inc. | USB integrated bidirectional digital isolator channel across an interface between two USB devices |
| US8090894B1 (en) * | 2007-09-21 | 2012-01-03 | Cypress Semiconductor Corporation | Architectures for supporting communication and access between multiple host devices and one or more common functions |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110967929A (en) * | 2018-09-30 | 2020-04-07 | 深圳市印之明科技有限公司 | System and method for adjusting light spot dislocation scanning time sequence of photoetching machine |
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Application publication date: 20140326 |