CN103675531B - Circuit for recognizing classes of devices, circuit board, terminal equipment and signal controller - Google Patents
Circuit for recognizing classes of devices, circuit board, terminal equipment and signal controller Download PDFInfo
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- CN103675531B CN103675531B CN201310617062.2A CN201310617062A CN103675531B CN 103675531 B CN103675531 B CN 103675531B CN 201310617062 A CN201310617062 A CN 201310617062A CN 103675531 B CN103675531 B CN 103675531B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
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- G06F21/44—Program or device authentication
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Abstract
The invention discloses a circuit for recognizing classes of devices, a circuit board, terminal equipment and a signal controller. The classes of the devices are recognized by measuring resistors, recognizing resistors and the signal controller. The recognizing resistors are connected to one another in series, and values of the resistances of the recognizing resistors which are connected to one another in series are determined by using analog-to-digital detection signals inputted by an analog-to-digital detecting signal port in the signal controller, universal input and output signals outputted by a universal input and output signal port and the measuring resistors, so that the classes of the devices are recognized. The number of elements used for the circuit for recognizing the classes of the devices is small, the line of the circuit is simple, the circuit is easy to measure, the classes of the recognized devices are increased, the complexity of the circuit for recognizing the classes of the device is reduced, and the recognizing cost is reduced.
Description
Technical field
The present invention relates to type identifier technical field, particularly to a kind of circuit of recognition means classification, circuit board, terminal
Equipment and signal controller.
Background technology
In current software generic platform compounds, need the environment that automatic recognition software is run, for example: product type,
Lcd(liquid crystal display, liquid crystal display) device model, frequency range of radio frequency etc., so that in running software
Do different disposal for hardware.
The resistance of multiple difference resistances, at present when distinguishing veneer or device model, is generally welded on different veneers, leads to
Cross using corresponding on gpio signal (universal input output signal, general purpose input output) measurement veneer
Resistance, and then obtain the resistance of the plurality of difference resistance.Different resistances according to resistance corresponding on veneer and sequential combination, with
And cooperation software carrys out the model of distinguishing tests veneer or device.Below by Fig. 1 its implementation is described:
According to device element list to the first identification resistance 101, second identification resistance 102, the 3rd identification resistance 103, the
Four identification resistance 104 and the first measurement resistance 105, second measurement resistance the 106, the 3rd measurement resistance the 107, the 4th measurement resistance
108 two kinds of resistance are welded.This kind of mode is by applying to the corresponding measurement port on signal controller 120
Gpio signal realizes the measurement to identification resistance.After start, gpio signal, gpio signal packet are applied on corresponding measurement port
Include 1(high level signal), 0(low level signal) or high resistant three state, (4 interface totally 34 kinds) plant combination to be capable of identify that 81.
The shortcoming of the method is: when carrying out model measurement for large-tonnage product, what the method needed is welded on veneer
Resistance and signal lines quantity many, cause that identification circuit is complicated, the problem of identification high cost.
Content of the invention
Embodiments provide a kind of circuit of recognition means classification, circuit board, terminal unit and signal controller,
To solve the problems, such as that in existing identification circuit technology, identification circuit is complicated, identify high cost.
In order to solve above-mentioned technical problem, the embodiment of the invention discloses following technical scheme:
In a first aspect, the embodiment of the present invention provides a kind of circuit of recognition means classification it is characterised in that this circuit bag
Include:
Measurement resistance, one end of described measurement resistance is connected with power supply；
N identification resistance being cascaded, described one end of n identification resistance being cascaded and described measurement electricity
The other end of resistance is connected in series, the other end ground connection of described n identification resistance being cascaded；Described n is the nature more than 1
Number；
Signal controller, it is defeated that signal controller includes at least one modulus detection signal port, at least n-1 universal input
Go out signal port, wherein, modulus detection signal port by modulus signal lines be connected to described measurement resistance and with
Between the identification resistance that described measurement resistance is joined directly together, n-1 universal input output signal port is exported by universal input
Holding wire is connected between the identification resistance that each two is cascaded；
Described signal controller passes through modulus detection signal and the universal input output letter of modulus detection signal port input
The universal input output signal of number port output and described measurement resistance determine described in the n resistance identifying resistance being cascaded
Value, and according to the resistance of described n identification resistance being cascaded, the classification of described device is identified.
In the first possible implementation of first aspect, described signal controller passes through modulus detection signal port
The universal input output signal of the modulus detection signal of input and the output of universal input output signal port and described measurement resistance
The resistance of n identification resistance being cascaded described in determination, specifically includes:
All universal input output signal port set are high resistant, modulus detection signal port obtains described measurement resistance
And and the described magnitude of voltage measuring between the identification resistance that resistance is joined directly together；
According to the direction of ground side to mains side, one by one the port set of universal input output signal is low level, obtains
The magnitude of voltage of n-1 modulus detection signal port；
According to described measurement resistance and and described measurement resistance be joined directly together identification resistance between magnitude of voltage, obtain
The magnitude of voltage of described n-1 modulus detection signal port, and the output valve of all universal input output signal ports, determine every
The resistance of one identification resistance.
In conjunction with the first possible implementation of described first aspect, in the possible realization side of the second of first aspect
In formula, described according to described measurement resistance and and described measurement resistance be joined directly together identification resistance between magnitude of voltage, acquisition
Described n-1 modulus detection signal port magnitude of voltage, and the output valve of all universal input output signal ports, determine
The resistance of each identification resistance, specifically includes:
According to described measurement resistance and and described measurement resistance be joined directly together identification resistance between magnitude of voltage, obtain
The magnitude of voltage of described n-1 modulus detection signal port, the output valve of all universal input output signal ports, and measurement electricity
Resistance and supply voltage, determine that being not set low level universal input output signal port leads to setting in low level one by one
With the identification resistance between input/output signal port, resistance of connecting between the identification resistance being connected with measurement resistance it
With, and the resistance of each identification resistance is determined according to this series connection resistance sum determining one by one.
In the third possible implementation of first aspect, described signal controller is cascaded according to described
The resistance of n identification resistance is identified to the classification of described device, specifically includes:
The resistance of n identification resistance being cascaded described in acquisition and the corresponding relation of device model, according to described right
Should be related to and the resistance of described n identification resistance being cascaded is identified to the classification of described device.
Second aspect, the embodiment of the present invention provides a kind of circuit board, including the circuit of above-mentioned recognition means classification,
Wherein, described signal controller is the processor chips on described circuit board.
The third aspect, the embodiment of the present invention provides a kind of terminal unit, including above-mentioned circuit board.
Fourth aspect, the embodiment of the present invention provides a kind of signal controller, for the classification of recognition means, on described device
Including:
Measurement resistance, one end of described measurement resistance is connected with power supply；
N identification resistance being cascaded, described one end of n identification resistance being cascaded and described measurement electricity
The other end of resistance is connected in series, the other end ground connection of described n identification resistance being cascaded；Described n is the nature more than 1
Number；
Described signal controller includes at least one modulus detection signal port, at least n-1 universal input output signal
Port, wherein, modulus detection signal port be suitable to by modulus signal lines be connected to described measurement resistance and with institute
State between the measurement identification resistance that is joined directly together of resistance, n-1 universal input output signal port is suitable to defeated by universal input
Go out holding wire to be connected between the identification resistance that each two is cascaded；
Described signal controller passes through modulus detection signal and the universal input output letter of modulus detection signal port input
The universal input output signal of number port output and described measurement resistance determine described in the n resistance identifying resistance being cascaded
Value, and according to the resistance of described n identification resistance being cascaded, the classification of described device is identified.
In the embodiment of the present invention, by identification resistance is connected, and using the modulus detection letter in signal controller
The modulus detection signal of number port input, the universal input output signal of universal input output signal port output and measurement electricity
Resistance, to determine the resistance of each identification resistance being cascaded, thus being identified, this recognition means class to the classification of device
Other circuit uses that components and parts are few, circuit simple, easily measures, and not only increases the species of recognition means classification, and reduces
The complexity of the circuit of recognition means classifications, reduces identification cost.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description are these
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also root
Obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is identification circuit structure chart of the prior art；
Fig. 2 is the electrical block diagram that the embodiment of the present invention 1 provides；
Fig. 3 is the method flow diagram that the embodiment of the present invention 1 provides；
Fig. 4 is the corresponding equivalent circuit diagram of step 301 that the embodiment of the present invention 1 provides；
Fig. 5 is the corresponding equivalent circuit diagram of step 302 that the embodiment of the present invention 1 provides；
Fig. 6 is the corresponding equivalent circuit diagram of step 303 that the embodiment of the present invention 1 provides；
Fig. 7 is 2 identification resistance circuit structural representations that the embodiment of the present invention 1 provides；
Fig. 8 is the electrical block diagram that the embodiment of the present invention 2 provides；
Fig. 9 is the method flow diagram that the embodiment of the present invention 2 provides.
Specific embodiment
Purpose, technical scheme and advantage for making the embodiment of the present invention are clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is explicitly described it is clear that described embodiment is the present invention
A part of embodiment, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
The every other embodiment being obtained under the premise of making creative work, broadly falls into the scope of protection of the invention.
In order to solve prior art identification circuit use components and parts many, identification species lack etc. deficiency, the invention provides
A kind of circuit of recognition means classification, circuit board, terminal unit and signal controller.
Embodiment 1
First embodiment of the invention provides a kind of circuit of recognition means classification, for veneer or need identification type
Number device be identified.For needing to identify device or the veneer of model, the embodiment of the present invention needs to go here and there on different veneers
The resistance combination of connection welding multiple difference resistance, thus be identified to the classification of device or veneer.The embodiment of the present invention is to go here and there
As a example the identification resistance being linked togather is 3, this circuit diagram is as shown in Fig. 2 this circuit includes: measures resistance, is cascaded
3 identification resistance and signal controller；Wherein, described measurement resistance one end be connected with power supply, described measure resistance another
One end is connected with the one end of 3 identification resistance being cascaded, another termination of this 3 identification resistance being cascaded
Ground, in embodiments of the present invention, from mains side to the direction of ground side, defines 3 identification resistance being cascaded and is respectively
Identification resistance r1, identification resistance r2 and identification resistance r3；Described signal controller includes at least one modulus detection ad signal end
Mouthful, at least 2 universal inputs export gpio signal ports, wherein, ad signal port passes through described in ad holding wire is connected to
Between measurement resistance and identification resistance r1, gpio1 signal port is connected to identification resistance r1 and identification electricity by gpio1 holding wire
Between resistance r2, gpio2 signal port is connected between identification resistance r2 and identification resistance r3 by gpio2 holding wire.
Wherein, when the resistance identifying resistance is 0, measurement resistance can play a protective role to circuit.This measurement resistance
Resistance be known resistance, this resistance needs to be limited in suitable region, and needs to be set according to supply voltage.
In embodiments of the present invention, signal controller can be peripheral control unit；Can also be the process on measurement veneer
Device chip, such as high pass chip.
Ad signal that signal controller is inputted by ad port and the gpio1 that gpio1 port, gpio2 port export respectively
Signal and gpio2 signal, determine identification resistance r1, identification resistance r2 and the resistance of identification resistance r3, as shown in figure 3, concrete wrap
Include:
Step 301: by the output valve set of gpio1 port and gpio2 port be high resistant, ad port obtain ad signal electricity
Pressure value 1；
Wherein, the output valve set of gpio1 port and gpio2 port is included for high resistant: by gpio1 holding wire and
Gpio2 holding wire is hanging.
In embodiments of the present invention, after the output valve set of gpio1 port and gpio2 port being high resistant, corresponding to Fig. 2
Equivalent circuit as shown in figure 4, ad port obtain ad signal magnitude of voltage 1 be r1+r2+r3 magnitude of voltage.
Step 302: by the output valve set of gpio1 port be high resistant, by the output valve set of gpio2 port be low electricity
Flat, ad port obtains the magnitude of voltage 2 of ad signal；
Wherein, the output valve set of gpio2 port is shown for low level, this gpio2 holding wire will identify that resistance r3 is short
Road.
In embodiments of the present invention, this step 302 correspond to Fig. 2 equivalent circuit as shown in figure 5, ad port obtain ad
The magnitude of voltage 2 of signal is the magnitude of voltage of r1+r2.
Step 303: by equal for the output valve of gpio1 port and gpio2 port set be low level, ad port obtain ad signal
Magnitude of voltage 3；
In embodiments of the present invention, this step 303 correspond to Fig. 2 equivalent circuit as shown in fig. 6, ad port obtain ad
The magnitude of voltage 3 of signal is the magnitude of voltage of r1.
Step 304: the magnitude of voltage 1 of the ad signal being obtained according to ad port, magnitude of voltage 2 and magnitude of voltage 3, and according to power supply
Voltage and the resistance of measurement resistance, are calculated the electric current of measurement resistance respectively, and are calculated r1+r2+ respectively according to electric current
The resistance of r3, r1+r2, r1；
The resistance of electric current=(magnitude of voltage of supply voltage-ad the signal)/measurement resistance of measurement resistance；
The magnitude of voltage 1/ of r1+r2+r3=ad signal measures the electric current of resistance；
The magnitude of voltage 2/ of r1+r2=ad signal measures the electric current of resistance；
The magnitude of voltage 3/ of r1=ad signal measures the electric current of resistance.
Step 305: according to above-mentioned result of calculation, be calculated the resistance of each identification resistance in this three identification resistance respectively
Value；
Wherein, according to the above-mentioned resistance that can obtain r1, then r2 is the difference of r1+r2 and r1, and r3 is r1+r2+r3 and r1+
The difference of r2.
Step 306: the ratio of the resistance of each identification resistance and the resistance of reference resistance r is rounded up so that identifying
The integral multiple of resistance r on the basis of the resistance of resistance；
Due in above-mentioned calculating process, the resistance of calculated identification resistance may not be integer it is therefore desirable to by
Reference resistance r turns to integer to the resistance of identification resistance, thus determining evaluator according to the resistance combination of the identification resistance obtaining
The classification of part.
Step 307: according to the combination of identification resistance r1, identification resistance r2 and the resistance of identification resistance r3, and obtain in advance
The resistance combination of the identification resistance taking and the corresponding relation of the classification of identification circuit, obtain the model of the classification of this circuit.
Measurement range in conjunction with ad signal and resistance border Fault-Tolerant Problems, if resistance measurement minimum precision for r(be r be base
Quasi- resistance), measurement can only distinguish the integral multiple of r, and resistance rank so that r1+r2+r3 is as 8r as a example, is tentatively counted for 1r to 8r.
Calculate getable valued combinations as shown in table 1 below:
Table 1
The restrictive condition of this method is: each resistance has 0r-8r totally 9 kinds of values, but single resistance, two resistance strings
Connection, three resistant series value also must be between 0r-8r.
Amount to total: the combination of 9+8+7+6+5+4+3+2+1=45 kind, if removing 0r, Conservative estimation also has 36 kinds of combinations.
In the case of cannot get through except 0r, can be had according to order using 3 identification resistance and 1 measurement resistance: 45+36+28+21+
15+10+6+3+1=165 kind compound mode, that is, can be by being welded on this 4 resistance according to the order of resistance successively
In 165 kinds of various boards, and then distinguish the model of this 165 kinds of circuit boards.
Wherein, scheme provided in an embodiment of the present invention is as shown in table 2 with the comparative result of prior art, as follows:
Table 2
| Relatively species | Existing scheme | This programme |
| Ad number of pins | 0 | 1 |
| Gpio number of pins | 4 | 2 |
| Distinguish signal number | 81 | 165 |
| Device count (resistance) | 8 | 4 |
As shown in Table 2, the embodiment of the present invention, by 3 identification resistant series link together, utilizes signal control simultaneously
The ad signal of ad port input in device processed and the gpio signal of gpio signal port output, determine 3 knowledges being cascaded
The resistance of other resistance, wherein in terms of existing technologies, the component number of use is few, circuit simple, easily measurement, identification
Low cost；By resistant series will be identified together, substantially increase the accuracy of identification of resistance and recognition means species
Quantity.
In embodiments of the present invention, can also be by gpio1 signal port, gpio2 signal port be set to input mould
Block, reads level, as shown in fig. 7, using the input value of gpio1 signal port and gpio2 signal port, judging the class of device
Not.Wherein, under the pattern for 3.3v for the supply voltage, low level is 0-0.8v, and 2.7-3.3v is high level, when gpio1 signal
When port or gpio2 signal port measured value are in low level, then input value is 0；When gpio1 signal port or gpio2 signal
When port measured value is in high level, then input value is 1.Input value according to gpio1 signal port or gpio2 signal port
Combination judges identification circuit model.4 kinds of models can be combined according to two identification resistance in Fig. 7.
With the lifting of chip technology level, the lifting of ad sampling precision, under the premise of circuit is immovable, can reach more
Many sampling combinations.
Embodiment 2
According in first embodiment, 3 identification resistance are elaborated, second embodiment of the invention provides one
Plant the circuit of recognition means classification, be specifically described and using n identification resistance, circuit be identified, as shown in figure 8, this circuit bag
Include:
Measurement resistance 801, one end of described measurement resistance is connected with power supply；
N identification resistance 802 being cascaded, described one end of n identification resistance being cascaded and described survey
The other end of amount resistance is connected in series, the other end ground connection of described n identification resistance being cascaded；Described n is more than 1
Natural number；
Signal controller 803, it is general defeated that signal controller includes at least one modulus detection signal port, at least n-1
Enter output signal port, wherein, a modulus detection signal port is connected to described measurement resistance by modulus signal lines
With and the described measurement identification resistance that is joined directly together of resistance between, n-1 universal input output signal port is by universal input
Output signal line is connected between the identification resistance that each two is cascaded；Described signal controller is used for by modulus
Detection signal port input modulus detection signal and universal input output signal port output universal input output signal and
The resistance of n identification resistance being cascaded described in described measurement resistance determination, and according to described n knowledge being cascaded
The resistance of other resistance is identified to described device classification.
In embodiments of the present invention, described signal controller be used for determining described in be cascaded n identify resistance
Resistance, this determines method as shown in figure 9, specifically including:
Step 901: all universal input output signal port set are high resistant, modulus detection signal port obtains described
Measurement resistance and and the described magnitude of voltage measuring between the identification resistance that resistance is joined directly together；
Wherein, by all gpio signal port set be high resistant, then ad signal port measurement magnitude of voltage be r1+r2
+ ... the magnitude of voltage n of+rn.
Step 902: according to the direction of ground side to mains side, be low electricity by the port set of universal input output signal one by one
Flat, obtain the magnitude of voltage of n-1 modulus detection signal port；
Wherein, the magnitude of voltage of n-1 ad signal port of acquisition includes: magnitude of voltage n-1, r1+ of r1+r2+ ...+rn-1
The magnitude of voltage n-2 of r2+ ...+rn-2 ..., the magnitude of voltage 1 of the magnitude of voltage 2 of r1+r2, r1.
Step 903: according to described measurement resistance and and the described voltage measuring between the identification resistance that resistance is joined directly together
Value, the magnitude of voltage of described n-1 modulus detection signal port obtaining, the output valve of all universal input output signal ports,
And measurement resistance and supply voltage, determine one by one be not set low level universal input output signal port with setting in
Identification resistance between low level universal input output signal port, is gone here and there between the identification resistance being connected with measurement resistance
Connection resistance sum.
According to the resistance of formula r '=(magnitude of voltage of supply voltage-ad signal port)/measurement resistance, by r1+r2+ ...+
The magnitude of voltage n-2 of magnitude of voltage n-1, r1+r2+ ...+rn-2 of magnitude of voltage n, r1+r2+ ...+rn-1 of rn ..., r1+r2
Magnitude of voltage 2, the magnitude of voltage 1 of r1 substitute into one by one ,+the rn that obtains r1+r2+ ..., r1+r2+ ...+rn-1, r1+r2+ ...+
The resistance of rn-2, r1+r2, r1.
Step 904: this series connection resistance sum according to determining determines the resistance of each identification resistance；
Due to obtaining the resistance of r1 in step 803, therefore, r2=(r1+r2)-r1, r3=(r1+r2+r3)-(r1+
R2) ... ..., rn=(r1+r2+ ...+rn)-(r1+r2+ ...+rn-1), thus obtain the resistance of each identification resistance.
Step 905: the resistance of n identification resistance being cascaded described in acquisition and the corresponding relation of device model, root
Resistance according to described corresponding relation and described n identification resistance being cascaded is identified to the classification of device.
The embodiment of the present invention is by being connected identification resistance, and utilizes the modulus detection signal end in signal controller
The modulus detection signal of mouth input, the universal input output signal of universal input output signal port output and measurement resistance, come
Determine the resistance of each identification resistance being cascaded, thus being identified, this recognition means classification to the classification of device
Circuit uses that components and parts are few, circuit simple, easily measures, and not only increases the species of recognition means classification, and decreases knowledge
The complexity of the circuit of other device classification, reduces identification cost.
Embodiment 3
Third embodiment of the invention additionally provides a kind of circuit board, including any one reality in such as embodiment 1～embodiment 2
Apply the circuit of the recognition means classification described in example.
Wherein, described signal controller is the processor chips on described circuit board.
Embodiment 4
Four embodiment of the invention additionally provides a kind of terminal unit, including circuit board as described in Example 3.Described
Terminal unit can be mobile terminal, such as mobile phone, panel computer, notebook computer, and e-book etc. is it is also possible to be that other are whole
End, such as desktop computer, Set Top Box etc.
Embodiment 5
Fifth embodiment of the invention additionally provides a kind of signal controller, for the classification of recognition means, described device
Upper inclusion:
Measurement resistance, one end of described measurement resistance is connected with power supply；
N identification resistance being cascaded, described one end of n identification resistance being cascaded and described measurement electricity
The other end of resistance is connected in series, the other end ground connection of described n identification resistance being cascaded；Described n is the nature more than 1
Number；
Described signal controller includes at least one modulus detection signal port, at least n-1 universal input output signal
Port, wherein, modulus detection signal port be suitable to by modulus signal lines be connected to described measurement resistance and with institute
State between the measurement identification resistance that is joined directly together of resistance, n-1 universal input output signal port is suitable to defeated by universal input
Go out holding wire to be connected between the identification resistance that each two is cascaded；
Described signal controller passes through modulus detection signal and the universal input output letter of modulus detection signal port input
The universal input output signal of number port output and described measurement resistance determine described in the n resistance identifying resistance being cascaded
Value, and according to the resistance of described n identification resistance being cascaded, the classification of described device is identified.
Wherein, this signal controller can be a kind of processor chips it is also possible to be a single part, and here is not done
Limit.
It will be apparent that the present embodiment may be referred to the content of previous embodiment, its related content repeats no more.
It will be recognized by those of ordinary skill in the art that the possible implementation of various aspects of the invention or various aspects
System, method or computer program can be embodied as.Therefore, each aspect of the present invention or various aspects
Possible implementation can adopt complete hardware embodiment, complete software embodiment (including firmware, resident software etc.), or
The form of the embodiment of integration software and hardware aspect, collectively referred to herein as " circuit ", " module " or " system ".Additionally,
The possible implementation of each aspect of the present invention or various aspects can be with the form of computer program, computer journey
Sequence product refers to the computer readable program code being stored in computer-readable medium.
Computer-readable medium can be computer-readable signal media or computer-readable recording medium.Computer can
Read storage medium including but not limited to electronics, magnetic, optics, electromagnetism, infrared or semiconductor system, equipment or device, or
Aforesaid arbitrarily appropriately combined, such as random access memory (ram), read only memory (rom), the read-only storage of erasable programmable
Device (eprom or flash memory), optical fiber, portable read only memory (cd-rom).
Processor in computer reads the computer readable program code being stored in computer-readable medium so that locating
Reason device is able to carry out function action specified in the combination of each step or each step in flow charts；Generation is implemented in block diagram
Each piece or each piece of function action specified in combination device.
Computer readable program code can execute completely on the computer of user, partly hold on the computer of user
Row, as single software kit, partly on the computer of user and part on the remote computer, or completely long-range
Execute on computer or server.It is also noted that in some alternate embodiment, each step or frame in flow charts
Each piece of function of being indicated of in figure may not be occurred by the order that in figure indicates.For example, depend on involved function, show in succession
Two steps going out or two blocks actually may be executed substantially concurrently, or these blocks sometimes may be by with suitable on the contrary
Sequence executes.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (7)
1. a kind of circuit of recognition means classification is it is characterised in that this circuit includes:
Measurement resistance, one end of described measurement resistance is connected with power supply；
N identification resistance being cascaded, described one end of n identification resistance being cascaded and described measurement resistance
The other end is connected in series, the other end ground connection of described n identification resistance being cascaded；Described n is the natural number more than 1；
Signal controller, signal controller includes at least one modulus detection signal port, at least n-1 universal input output letter
Number port, wherein, modulus detection signal port by modulus signal lines be connected to described measurement resistance and with described
Between the identification resistance that measurement resistance is joined directly together, universal input output signal is passed through in n-1 universal input output signal port
Line is connected between the identification resistance that each two is cascaded；
Described signal controller passes through the modulus detection signal of modulus detection signal port input, universal input output signal port
The resistance of n identification resistance being cascaded described in the universal input output signal of output and the determination of described measurement resistance, and
According to the resistance of described n identification resistance being cascaded, the classification of described device is identified.
2. the circuit of recognition means classification as claimed in claim 1 is it is characterised in that described signal controller is examined by modulus
Survey modulus detection signal, the universal input output signal and described of universal input output signal port output of signal port input
The resistance of n identification resistance being cascaded described in measurement resistance determination, specifically includes:
By all universal input output signal port set be high resistant, modulus detection signal port obtain described measurement resistance and with
Magnitude of voltage between the identification resistance that described measurement resistance is joined directly together；
According to the direction of ground side to mains side, one by one the port set of universal input output signal is low level, modulus detects
Signal port obtains n-1 magnitude of voltage；
According to described measurement resistance and and described measurement resistance be joined directly together identification resistance between magnitude of voltage, obtain described in
N-1 magnitude of voltage, and the output valve of all universal input output signal ports, determine the resistance of each identification resistance.
3. recognition means classification as claimed in claim 2 circuit it is characterised in that described according to described measurement resistance and with
Magnitude of voltage between the identification resistance that described measurement resistance is joined directly together, the described n-1 magnitude of voltage obtaining, and all general
The output valve of input/output signal port, determines the resistance of each identification resistance, specifically includes:
According to described measurement resistance and and described measurement resistance be joined directly together identification resistance between magnitude of voltage, obtain described in
N-1 magnitude of voltage, the output valve of all universal input output signal ports, and measurement resistance and supply voltage, determine one by one
Be not set low level universal input output signal port with setting in low level universal input output signal port it
Between identification resistance, to measurement resistance be connected identification resistance between connect resistance sum, and according to determine one by one this
Series connection resistance sum determines the resistance of each identification resistance.
4. the circuit of recognition means classification as claimed in claim 1 is it is characterised in that described signal controller is according to described string
The resistance of n identification resistance being linked togather is identified to the classification of described device, specifically includes:
The resistance of n identification resistance being cascaded described in acquisition and the corresponding relation of device model, close according to described correspondence
The resistance of system and described n identification resistance being cascaded is identified to the classification of described device.
5. a kind of circuit board is it is characterised in that include the electricity of the recognition means classification as any one of Claims 1 to 4
Road,
Wherein, described signal controller is the processor chips on described circuit board.
6. a kind of terminal unit is it is characterised in that include circuit board as claimed in claim 5.
7. a kind of signal controller, for the classification of recognition means, described device includes:
Measurement resistance, one end of described measurement resistance is connected with power supply；
N identification resistance being cascaded, described one end of n identification resistance being cascaded and described measurement resistance
The other end is connected in series, the other end ground connection of described n identification resistance being cascaded；Described n is the natural number more than 1；
It is characterized in that:
Described signal controller includes at least one modulus detection signal port, at least n-1 universal input output signal port,
Wherein, modulus detection signal port be suitable to by modulus signal lines be connected to described measurement resistance and with described measurement
Between the identification resistance that resistance is joined directly together, n-1 universal input output signal port is suitable to by universal input output signal
Line is connected between the identification resistance that each two is cascaded；
Described signal controller passes through the modulus detection signal of modulus detection signal port input, universal input output signal port
The resistance of n identification resistance being cascaded described in the universal input output signal of output and the determination of described measurement resistance, and
According to the resistance of described n identification resistance being cascaded, the classification of described device is identified.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310617062.2A CN103675531B (en) | 2013-11-27 | 2013-11-27 | Circuit for recognizing classes of devices, circuit board, terminal equipment and signal controller |
| PCT/CN2014/092123 WO2015078351A1 (en) | 2013-11-27 | 2014-11-25 | Circuit for recognizing device category, circuit board, terminal device and signal controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310617062.2A CN103675531B (en) | 2013-11-27 | 2013-11-27 | Circuit for recognizing classes of devices, circuit board, terminal equipment and signal controller |
Publications (2)
| Publication Number | Publication Date |
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| CN103675531A CN103675531A (en) | 2014-03-26 |
| CN103675531B true CN103675531B (en) | 2017-01-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310617062.2A Active CN103675531B (en) | 2013-11-27 | 2013-11-27 | Circuit for recognizing classes of devices, circuit board, terminal equipment and signal controller |
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| Country | Link |
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| CN (1) | CN103675531B (en) |
| WO (1) | WO2015078351A1 (en) |
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| CN103675531B (en) * | 2013-11-27 | 2017-01-25 | 华为终端有限公司 | Circuit for recognizing classes of devices, circuit board, terminal equipment and signal controller |
| CN106033116A (en) * | 2015-03-13 | 2016-10-19 | 乐星产电(无锡)有限公司 | Frequency converter capacity identification device and identification method |
| CN106556752A (en) * | 2015-09-25 | 2017-04-05 | 鸿富锦精密工业(武汉)有限公司 | GPIO interface circuit for detecting |
| CN105653288B (en) * | 2015-12-31 | 2019-06-21 | 高新兴物联科技有限公司 | A kind of method and apparatus of module product software automatic identification hardware |
| CN108091349B (en) * | 2016-11-23 | 2021-05-11 | 成都鼎桥通信技术有限公司 | Voice quality detection system and method and PESQ control terminal |
| CN108809159B (en) * | 2017-05-01 | 2022-01-04 | 日本电产株式会社 | Brushless DC motor, and identification method and identification device for identifying type thereof |
| CN109946520A (en) * | 2017-12-20 | 2019-06-28 | 展讯通信（上海）有限公司 | Products configuration identifying system and method |
| CN108551346B (en) * | 2018-04-17 | 2020-08-18 | 深圳市沃特沃德股份有限公司 | Method and device for controlling frequency band in communication terminal |
| CN110123140A (en) * | 2019-05-28 | 2019-08-16 | 九阳股份有限公司 | A kind of electric heating pot |
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| CN113932938A (en) * | 2020-06-29 | 2022-01-14 | 广东美的厨房电器制造有限公司 | Detection circuit, control method, cooking appliance, and computer-readable storage medium |
| CN113220619A (en) * | 2021-04-30 | 2021-08-06 | 山东英信计算机技术有限公司 | Method, system and medium for distributing PCIE channel bandwidth |
| CN113933558A (en) * | 2021-10-13 | 2022-01-14 | 江苏斯菲尔电气股份有限公司 | Instrument capable of automatically identifying specification of current transformer and setting transformation ratio |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2015078351A1 (en) | 2015-06-04 |
| CN103675531A (en) | 2014-03-26 |
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