CN103646881A - 晶圆封装方法 - Google Patents

晶圆封装方法 Download PDF

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CN103646881A
CN103646881A CN201310462970.9A CN201310462970A CN103646881A CN 103646881 A CN103646881 A CN 103646881A CN 201310462970 A CN201310462970 A CN 201310462970A CN 103646881 A CN103646881 A CN 103646881A
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丁万春
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to PCT/CN2014/087488 priority patent/WO2015043495A1/zh
Priority to US14/764,151 priority patent/US20150380369A1/en
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    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

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Abstract

本发明涉及一种晶圆封装方法,包括:提供基板,并在基板的一面上形成沟槽,将芯片贴于所述沟槽内;在基板上形成封料层,并裸露出芯片的连接部件;在所述封料层上形成与所述连接部件电连接的布线层;在所述布线层上形成保护膜层,并形成露出布线层的开口;在所述开口内形成与布线层连接的球下金属层,并在球下金属层上形成金属球;本发明提供的晶圆封装方法可对多个芯片进行封装,具有较高的集成度和整合度。

Description

晶圆封装方法
技术领域
本发明涉及半导体技术领域,尤其涉及一种晶圆封装方法。 
背景技术
随着集成电路技术的不断发展,电子产品越来越向小型化、智能化以及高可靠性方向发展,而集成电路封装直接影响着集成电路、电子模块乃至整机性能,在集成电路晶片尺寸逐步缩小、集成度不断提高的情况下,电子工业对集成电路封装结束提出了越来越高的要求。 
随着半导体产品轻薄短小的趋势以及产品系统功能需求的不断提高,如何进一步提高系统级封装的整合度成为本领域技术人员亟需解决的问题。 
发明内容
本发明解决的技术问题是:如何进一步提高系统级封装的整合度。 
为解决上述技术问题,本发明提供了一种晶圆封装方法,包括: 
提供基板,并在基板的一面上形成沟槽,将芯片贴于所述沟槽内; 
在基板上形成封料层,并裸露出芯片的连接部件; 
在所述封料层上形成与所述连接部件电连接的布线层; 
在所述布线层上形成保护膜层,并形成露出布线层的开口; 
在所述开口内形成与布线层连接的球下金属层,并在球下金属层上形成金属球。 
本发明提供的晶圆封装方法可将多个不同的芯片进行封装,具有较高的集成度和整合度。 
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。 
图1为本发明提供的晶圆封装结构一种实施例的结构示意图。 
图2为本发明提供的晶圆封装方法一种实施例的流程图。 
图3a—图3f为本发明提供的晶圆封装方法一种实施例各步骤中封装方法的结构示意图。 
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。 
参考图1,本实施例提供一种晶圆封装结构,包括: 
基板101,基板101的一面上设有沟槽102,沟槽102内设有芯片103; 
形成于基板101上的的封料层104,封料层104表面裸露出芯片103的连接部件; 
形成于封料层104上的与连接部件电连接的布线层; 
形成与布线层上的保护膜层105,保护膜层105具有露出布线层的开口106; 
形成于开口106内与布线层连接的球下金属层107; 
形成于球下金属层107上的金属球108。 
本实施例提供的晶圆封装结构,可对多个不同的芯片进行封装,具有较 高的集成度和整合度。 
在本实施例中,基板101优选采用硅晶片,硅晶片具有较好的硬度和平整度,可有效降低封装器件的失效比例;在基板101上形成沟槽的方法具体包括:在基板101的一面通过激光形成对准标记,在对准标记处进行刻蚀形成沟槽102。 
将芯片103贴于沟槽102内,并在基板101上形成封料层104。 
作为一种可选的实施方式,封料层104填充于沟槽102内以及各芯片103之间,部分封料层104还覆盖于芯片103表面,封料层104的上表面与芯片103的连接部件顶部齐平。 
由于芯片103贴于沟槽102内,且沟槽102内填充有封料层,因此使得芯片103更加牢固的固定在基板101上,有效避免芯片103脱落的情况发生。 
作为一种可选的实施方式,布线层包括金属层109以及金属再布线层110,金属层109形成于封料层之上并与芯片103的连接部件电连接,金属再布线层110形成于金属层109上。 
金属层109的材料为钛或铜,采用物理气相沉积涂层技术(PVD,Physical Vapor Deposition)在封料层表面形成金属层109,金属层109作为种子层,在金属层109上形成金属再布线层110,金属层109和金属再布线层110形成布线层,实现各芯片103之间功能性系统互联和走线。 
由于部分封料层104覆盖于芯片103表面,封料层104的上表面与芯片103的连接部件顶部齐平,布线层设置于封料层上,因此,布线层只与芯片103的连接部件接触而不会与芯片的其他部分接触,有效降低各芯片之间的干扰,提高芯片之间的绝缘性。 
布线层上形成有保护膜层105,在保护膜层105上相应的位置形成开口106,在开口内形成球下金属层107,球下金属层107上形成金属球108。 
作为一种可选的实施方式,基板的另一面,即未贴有芯片的一面上,形成有底部封装层,一方面能对封装方法进行保护,另一方面有利于封装方法进行散热,此外,还可在底部封装层上标记出产品型号等信息。 
作为一种可选的实施方式,形成封料层104的材料为环氧树脂,这种材料的密封性能较好,塑封容易,是形成封料层104的较佳材料。 
作为一种可选的实施方式,连接部件为芯片的焊盘。 
以下结合具体的封装方法实施例对本发明作进一步介绍。 
如图2所示为本发明中一个实施例的晶圆封装方法流程图,包括: 
步骤S201,提供基板,并在基板的一面上形成沟槽,将芯片贴于所述沟槽内; 
步骤S202,在基板上形成封料层,并裸露出芯片的连接部件; 
步骤S203,在所述封料层上形成与所述连接部件电连接的布线层; 
步骤S204,在所述布线层上形成保护膜层,并形成露出布线层的开口; 
步骤S205,在所述开口内形成与布线层连接的球下金属层,并在球下金属层上形成金属球。 
首先执行步骤S201,参考图3,提供基板101,并在基板101的一面用激光形成对准标记,在对准标记的位置上刻蚀出沟槽102,将芯片103贴于沟槽102内并暴露出芯片102的功能面。 
芯片102的功能面为连接部件所在的表面。 
基板101优选为硅晶片。 
接下来执行步骤S202,在基板101上形成封料层104,具体方法包括:将封料层填充于沟槽102内以及各芯片103之间,且还覆盖于芯片103表面;之后对封料层104进行打磨暴露出芯片103上的连接部件,使得封料层的上表面与芯片的连接部件的顶部齐平。 
由于芯片103贴于沟槽102内,且沟槽102内填充有封料层,因此使得芯片103更加牢固的固定在基板101上,有效避免芯片103脱落的情况发生。 
此外,通过打磨封料层使得封料层104的上表面与芯片的连接部件的顶部齐平,刚好露出芯片的连接部件,能够保证各个芯片连接部件共面,提高封装方法的可靠性。 
执行步骤S203,在封料层104上形成与连接部件电连接的布线层,具体方法包括:在封料层上104上形成金属层109,形成金属层109的工艺采用物理气相沉积涂层技术(PVD,Physical Vapor Deposition)。 
物理气相沉积涂层技术室指利用物理过程实现物质转移,将原子或分子由源转移到基材表面上的过程。它可以将某些有特殊性能例如强度 高、耐磨性、散热性、耐腐性等的微粒喷涂在性能较低的母体上,使得母体具有更好的性能。物理气相沉积涂层技术基本方法与:真空蒸发、溅射、离子镀。该技术提高了涂层材料与所提供基体材料的结合强度,并且适合多种材质,涂层多样化,减少工艺时间,提高生产率,操作该涂层技术的温度较低,零件尺寸变形小,对工艺环境无污染,并且所述涂层材料也有很多的选择,本实施例优选的金属层材料为钛或者铜。 
金属层109作为种子层,在金属层109上形成金属再布线层110,对金属层109和金属再布线层进行刻蚀,实现各芯片103之间功能性系统互联和走线。 
由于部分封料层104覆盖于芯片103表面,封料层104的上表面与芯片103的连接部件顶部齐平,布线层设置于封料层上,因此,布线层只与芯片103的连接部件接触而不会与芯片的其他部分接触,有效降低各芯片之间的干扰,提高芯片之间的绝缘性。 
执行步骤S204和步骤205,在金属再布线层110上形成保护膜层105,在保护膜层105上形成暴露金属再布线层110的开口106,在开口106内形成与金属再布线层105连接的球下金属层107。 
此外,形成球下金属层107之后还包括:对基板未贴芯片的一侧进行打磨,并形成底部封装层111。 
对基板101进行打磨可以使整体的封装方法的厚度变薄,顺应半导体封装轻薄短小的趋势要求,打磨的厚度根据实际应用的需要决定。 
底部封装层111一方面能对封装方法进行保护,另一方面有利于封装方法进行散热. 
对所述底部封装层111进行激光标记,标记出产品型号等信息,以便于以后的应用需求。 
最后,在球下金属层107上形成金属球108。 
本发明提供的晶圆封装方法,可对多个不同的芯片进行封装,具有较高的集成度和整合度,此外,符合半导体封装轻薄短小的趋势要求,可靠性高。 
最后应说明的是:虽然以上已经详细说明了本发明及其优点,但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且,本发明的范围不仅限于 说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解,根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此,所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。 

Claims (10)

1.一种晶圆封装方法,其特征在于,包括:
提供基板,并在基板的一面上形成沟槽,将芯片贴于所述沟槽内;
在基板上形成封料层,并裸露出芯片的连接部件;
在所述封料层上形成与所述连接部件电连接的布线层;
在所述布线层上形成保护膜层,并形成露出布线层的开口;
在所述开口内形成与布线层连接的球下金属层,并在球下金属层上形成金属球。
2.根据权利要求1所述的晶圆封装方法,其特征在于,所述在基板的一面形成沟槽,包括:在基板的一面用激光形成对准标记,并在所述对准标记的位置上刻蚀出沟槽。
3.根据权利要求1所述的晶圆封装方法,其特征在于,在芯片上覆盖封料层,并裸露出芯片的连接部件包括:将封料层填充于沟槽内以及各所述芯片表面,打磨所述封料层使所述封料层的上表面与所述芯片的连接部件顶部齐平。
4.根据权利要求1所述的晶圆封装方法,其特征在于,在所述封料层上形成与所述连接部件电连接的布线层,包括:在所述封料层上依次形成金属层和金属再布线层,对所述金属层和金属再布线层进行刻蚀实现各芯片之间的互联。
5.根据权利要求4所述的晶圆封装方法,其特征在于,所述金属层的材料为钛或铜。
6.根据权利要求1所述的晶圆封装方法,其特征在于,所述基板为硅晶片。
7.根据权利要求1所述的晶圆封装方法,其特征在于,所述方法还包括:对所述基板未贴有芯片的一面进行打磨。
8.根据权利要求1或7所述的晶圆封装方法,其特征在于,在所述基板的未贴有芯片的一面形成底部封装层。
9.根据权利要求1所述的晶圆封装方法,其特征在于,所述形成所述封料层的材料为环氧树脂。
10.根据权利要求1所述的晶圆封装方法,其特征在于,所述连接部件为芯片的焊盘。
CN201310462970.9A 2013-09-30 2013-09-30 晶圆封装方法 Pending CN103646881A (zh)

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WO2015043495A1 (zh) * 2013-09-30 2015-04-02 南通富士通微电子股份有限公司 晶圆封装结构和封装方法
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