CN103634003B - OSC frequency automatic calibration circuit and automatic calibrating method - Google Patents
OSC frequency automatic calibration circuit and automatic calibrating method Download PDFInfo
- Publication number
- CN103634003B CN103634003B CN201210289181.5A CN201210289181A CN103634003B CN 103634003 B CN103634003 B CN 103634003B CN 201210289181 A CN201210289181 A CN 201210289181A CN 103634003 B CN103634003 B CN 103634003B
- Authority
- CN
- China
- Prior art keywords
- frequency
- clock signal
- signal
- time window
- reference time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Measuring Frequencies, Analyzing Spectra (AREA)
Abstract
The invention discloses a kind of OSC frequency automatic calibration circuit, comprising: parametric generator, OSC circuit, frequency error detection circuit, calibration terminates decision circuitry, parameter add-subtract control circuit.Frequency error detection circuit is connected with reference time window signal and centre frequency index signal, and carries out frequency error detection according to reference time window signal and centre frequency index signal to clock signal and calculate frequency error value.Whether calibration terminates decision circuitry determination frequency automatic calibration and terminates and success or failure.At the end of calibration is not, parameter add-subtract control circuit exports a parameter add-subtract control signal to parametric generator and regulates controling parameters, and amplitude and the frequency error value of adjustment are directly proportional.The invention discloses a kind of automatic calibrating method of OSC frequency automatic calibration circuit.Electric circuit inspection principle of the present invention is simple, and circuit area is little.Adjustment and the frequency error value of parameter of the present invention are directly proportional, and can accelerate calibration speed.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of OSC(oscillator) frequency automatic calibration circuit; The invention still further relates to a kind of automatic calibrating method of OSC frequency automatic calibration circuit.
Background technology
The method of existing OSC automatic calibration counts the clock signal that OSC circuit exports in length in a preset time, the count value of standard frequency clock signal is deducted and the absolute value of trying to achieve both differences is used as frequency error, in order to judge whether the clock signal frequency that OSC circuit exports reaches calibration by the size of this count value.
As shown in Figure 1, be existing OSC frequency automatic calibration circuit structure diagram.Existing OSC frequency automatic calibration circuit comprises: OSC circuit 101, timer counter circuit 102, absolute error counting circuit 103, minimal error and parameter post device 104, calibration terminates decision circuitry 105, single step parameter regulating circuit 106 etc.The concrete automatic calibration flow process of existing OSC frequency automatic calibration circuit is:
1, a preset initial value is to the adjustment parameter PARAM of OSC circuit 101, and the value presetting the minimal error register that minimal error and parameter are posted in device 104 is a register maximum.
2, time delay certain hour is after the clock signal OSCOUT that OSC circuit 101 exports stablizes, and the clock signal OSCOUT that the OSC circuit 101 of timer counter circuit 102 couples of set time T1 exports counts.
3, absolute error counting circuit 103 count results of timer counter circuit 102 deducts the count value of standard frequency clock signal within the T1 time, and asks absolute value, in this, as frequency error.
4, the value of comparison frequency error and minimal error register, if frequency error is less than the value of minimal error register, then the value of minimal error register is rewritten as this frequency error value, simultaneously parameter value PARAM is now recorded to minimal error and parameter is posted in the minimal error parameter register of device 104.
5, calibration end decision circuitry 105 judges whether calibration completes, and namely judges that whether parameter value PARAM is unidirectional and adjusts to maximum or minimum value.If completed, then adjustment parameter PARAM is arranged to the value of minimal error parameter register, OSC circuit 101 exports the most accurate frequency, completes automatic calibration; Otherwise, perform the 6th step.
6, the single step of single step parameter regulating circuit 106 changes regulating parameter PARAM, re-executes step 2.
Existing OSC frequency automatic calibration method has following shortcoming:
Owing to counting certain hour total length, because output frequency size is uncertain, counting circuit is larger.
The parameter adjustment step pitch of parameter scanning is little, completes the testing time carried out required for automatic calibration many.The alignment time needed is long.
Error needs to take absolute value, and needs extra absolute value counting circuit.
Special register record minimum frequency error amount and the parameter value of correspondence thereof is needed in parameter scanning process.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of OSC frequency automatic calibration circuit, can accelerate calibration process and reduce circuit area.For this reason, the present invention also provides a kind of automatic calibrating method using OSC frequency automatic calibration circuit.
For solving the problems of the technologies described above, OSC frequency automatic calibration circuit provided by the invention, is characterized in that, comprising: parametric generator, OSC circuit, frequency error detection circuit, and calibration terminates decision circuitry, parameter add-subtract control circuit.
The output of described parametric generator exports controling parameters to described OSC circuit.
The output of described OSC circuit exports a clock signal to described frequency error detection circuit, the frequency size of described clock signal is regulated by described controling parameters, the frequency of larger, the described clock signal of described controling parameters is larger, and the frequency of less, the described clock signal of described controling parameters is less.
The input of described frequency error detection circuit connects a reference time window signal and a centre frequency index signal, described frequency error detection circuit carries out frequency error detection according to described reference time window signal and centre frequency index signal to described clock signal, and whether the end that detects the clock signal that described OSC circuit exports calculates described frequency error value within described reference time window signal; Described reference time window signal defines the frequency valid value range of described clock signal, and described centre frequency index signal defines the size of center frequency value; Described frequency error value is larger, the frequency of described clock signal and the difference of described centre frequency larger.
Described calibration terminates decision circuitry and judges whether the frequency automatic calibration of described OSC circuit terminates and the success of determination frequency automatic calibration or failure according to described controling parameters and described frequency error value; When described controling parameters is maximum or minimum value or described frequency error value is zero, described calibration terminates decision circuitry and judges that the frequency automatic calibration of described OSC circuit terminates; When the frequency automatic calibration of described OSC circuit terminates, and when the end of described clock signal is positioned within described reference time window signal, described calibration terminates the frequency automatic calibration success that decision circuitry judges described OSC circuit.
The frequency automatic calibration of described OSC circuit not at the end of, described parameter add-subtract control circuit exports a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export adds a value be directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export deducts a value be directly proportional with described frequency error value by currency.
Further improvement is, the clock signal counting that described OSC circuit exports N time, and N is more than or equal to 2; Described reference time window signal be the maximum effective frequency in N number of cycle clock signal end to the minimum effective frequency in N number of cycle clock signal end between signal; Described centre frequency index signal is the rising edge signal of the clock signal end of the centre frequency being positioned at N number of cycle.
Further improvement is, if the end of the clock signal that described OSC circuit exports is within described reference time window signal, described frequency error value is adopt centre frequency to carry out the periodicity counted between the end of the clock signal that described OSC circuit exports and described centre frequency index signal.If the end of the clock signal that described OSC circuit exports does not arrive the front end of described reference time window signal, or beyond the end of described reference time window signal, then described frequency error value is excessive, the frequency of the clock signal exported is beyond effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal that described OSC circuit exports exceeds the rear end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the rear end of described reference time window signal and described centre frequency index signal.
For solving the problems of the technologies described above, the automatic calibrating method of use OSC frequency automatic calibration circuit provided by the invention comprises the steps:
Described controling parameters is set to parameter median by step one, described parametric generator.
The output of step 2, described OSC circuit exports the frequency clock signal corresponding with described controling parameters.
Step 3, described frequency error detection circuit carry out frequency error detection to the clock signal that described OSC circuit exports, and whether the end that detects the clock signal that described OSC circuit exports calculates described frequency error value within described reference time window signal.
Step 4, judge that whether the frequency of the clock signal that described OSC circuit exports is identical with described centre frequency according to described frequency error value, if identical, described calibration terminates decision circuitry and judges the frequency automatic calibration success of described OSC circuit and terminate calibration; If the frequency of the clock signal that described OSC circuit exports is not identical with described centre frequency, then carry out step 5.
Step 5, judge whether described controling parameters is maximum or minimum value; If described controling parameters is maximum or minimum value, described calibration terminates decision circuitry and judges that the frequency automatic calibration of described OSC circuit terminates, if the end of the clock signal that described OSC circuit exports is within described reference time window signal, calibrate successfully, if the end of the clock signal of described OSC circuit output is not within described reference time window signal, calibrate failure; If described controling parameters is not maximum or minimum value, then carry out step 6.
Step 6, described parameter add-subtract control circuit export a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export adds a value be directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export deducts a value be directly proportional with described frequency error value by currency; After described controling parameters adjustment, jump to step 2 and proceed calibration.
Further improvement is, the median of parameter described in step one is the controling parameters value that the clock signal that described OSC circuit is exported equals center frequency value maximum probability again and again.
Further improvement is, the clock signal counting that described OSC circuit exports N time, and N is more than or equal to 2; Described reference time window signal be the maximum effective frequency in N number of cycle clock signal end to the minimum effective frequency in N number of cycle clock signal end between signal; Described centre frequency index signal is the rising edge signal of the clock signal end of the centre frequency being positioned at N number of cycle.
Further improvement is, if the end of the clock signal that described OSC circuit exports is within described reference time window signal in step 3, described frequency error value is adopt centre frequency to carry out the periodicity counted between the end of the clock signal that described OSC circuit exports and described centre frequency index signal.If the end of the clock signal that described OSC circuit exports does not arrive the front end of described reference time window signal, or beyond the end of described reference time window signal, then described frequency error value is excessive, the frequency of the clock signal exported is beyond effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal that described OSC circuit exports exceeds the rear end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the rear end of described reference time window signal and described centre frequency index signal.
Beneficial effect of the present invention is:
1, frequency error detection electric circuit inspection principle of the present invention is simple, frequency error value maximum count scope of the present invention is the counting in the front end of reference time window signal or time span between rear end and centre frequency index signal, compared to the prior art, the present invention does not need to count the time total length of clock signal, therefore counting circuit is less; The present invention does not need extra absolute value counting circuit yet, therefore circuit area of the present invention is little.
2, during calibration of the present invention, adjustment and the frequency error value of the controling parameters of OSC circuit are directly proportional, and when namely frequency error value is large, the adjusting range of controling parameters more greatly; And frequency error value hour, the adjusting range of controling parameters is less.Carry out parameter adjustment with in prior art by parameter scanning mode, the step pitch of controling parameters adjustment of the present invention is large, can greatly reduce the testing time carried out required for automatic calibration, reduce the alignment time, accelerate calibration speed.
3, the present invention is except calibrating unsuccessfully, and at the end of calibration, the clock signal frequency of output is minimal error frequency, does not need special register to record the parameter value of minimum frequency error amount and correspondence thereof.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing OSC frequency automatic calibration circuit structure diagram;
Fig. 2 is embodiment of the present invention OSC frequency automatic calibration circuit structure diagram;
Fig. 3 is the automatic calibrating method flow chart of embodiment of the present invention OSC frequency automatic calibration circuit;
Fig. 4 is the detection sequential chart in embodiment of the present invention method when the clock signal frequency of OSC circuit output is greater than centre frequency;
Fig. 5 is the detection sequential chart in embodiment of the present invention method when the clock signal frequency of OSC circuit output is less than centre frequency.
Embodiment
As shown in Figure 2, be embodiment of the present invention OSC frequency automatic calibration circuit structure diagram; Embodiment of the present invention OSC frequency automatic calibration circuit comprises: parametric generator 1, OSC circuit 2, frequency error detection circuit 3, and calibration terminates decision circuitry 4, parameter add-subtract control circuit 5.
The output of described parametric generator 1 exports controling parameters PARAM to described OSC circuit 2.
The output of described OSC circuit 2 exports a clock signal OSCOUT to described frequency error detection circuit 3, the frequency size of described clock signal OSCOUT is regulated by described controling parameters PARAM, the frequency of larger, the described clock signal OSCOUT of described controling parameters PARAM is larger, and the frequency of less, the described clock signal OSCOUT of described controling parameters PARAM is less.
The input of described frequency error detection circuit 3 also connects a reference time window signal PWIN and centre frequency index signal PCENT, described frequency error detection circuit 3 carries out frequency error detection according to described reference time window signal PWIN and centre frequency index signal PCENT to described clock signal OSCOUT, and whether the end that detects the clock signal OSCOUT that described OSC circuit 2 exports calculates described frequency error value within described reference time window signal PWIN; Described reference time window signal PWIN defines the frequency valid value range of described clock signal, and described centre frequency index signal PCENT defines the size of center frequency value; Described frequency error value is larger, the frequency of described clock signal OSCOUT and the difference of described centre frequency larger.
As shown in Figure 4, be the detection sequential chart of the clock signal frequency exported when OSC circuit in embodiment of the present invention method when being greater than centre frequency; As shown in Figure 5, be the detection sequential chart of the clock signal frequency exported when OSC circuit in embodiment of the present invention method when being less than centre frequency.The clock signal OSCOUT counting that described OSC circuit 2 exports N time, it is pnclk that N is more than or equal to curve corresponding in 2, Fig. 4 and Fig. 5; Described reference time window signal PWIN be the maximum effective frequency in N number of cycle clock signal end to the minimum effective frequency in N number of cycle clock signal end between signal, curve corresponding in Fig. 4 and Fig. 5 is pwin; Described centre frequency index signal PCENT is the rising edge signal of the clock signal end of the centre frequency being positioned at N number of cycle, and curve corresponding in Fig. 4 and Fig. 5 is pcent.The curve that described frequency error value is corresponding is the curve pcnt in Fig. 4 and Fig. 5.
If the end of the clock signal that described OSC circuit 2 exports is within described reference time window signal PWIN, described frequency error value is adopt centre frequency to carry out the periodicity counted between the end of the clock signal that described OSC circuit 2 exports and described centre frequency index signal PCENT.As shown in Figure 4, the clock signal frequency that OSC circuit exports is greater than centre frequency, the end of the clock signal that described OSC circuit 2 exports is positioned at the rising edge front end corresponding to centre frequency of described centre frequency index signal PCENT, and the curve pcnt that described frequency error value is corresponding is also positioned at the rising edge front end corresponding to centre frequency of described centre frequency index signal PCENT.As shown in Figure 5, the clock signal frequency that OSC circuit exports is less than centre frequency, and the curve pcnt that described frequency error value is corresponding is positioned at the rising edge rear end corresponding to centre frequency of described centre frequency index signal PCENT.
If the end of the clock signal that described OSC circuit 2 exports does not arrive the front end of described reference time window signal PWIN, or beyond the end of described reference time window signal PWIN, then described frequency error value is excessive, the frequency of the clock signal exported is beyond effective range, now the computational methods of described frequency error value are: if the frequency that the end of the clock signal OSCOUT of described OSC circuit 2 output does not arrive the front end of described reference time window signal PWIN and the clock signal OSCOUT of described OSC circuit 2 output is greater than maximum effective frequency, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the front end of described reference time window signal PWIN and described centre frequency index signal PCENT, also namely described frequency error value is calculated with the clock signal OSCOUT that frequency is maximum effective frequency, if the frequency that the end of the clock signal OSCOUT that described OSC circuit 2 exports exceeds the rear end of described reference time window signal PWIN and the clock signal OSCOUT of described OSC circuit 2 output is less than minimum effective frequency, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the rear end of described reference time window signal PWIN and described centre frequency index signal PCENT, also namely calculates described frequency error value with the clock signal OSCOUT that frequency is minimum effective frequency.Can find out, the frequency error value maximum count scope of the embodiment of the present invention is the counting in the front end of reference time window signal PWIN or time span between rear end and centre frequency index signal PCENT.
Described calibration terminates decision circuitry 4 and judges whether the frequency automatic calibration of described OSC circuit 2 terminates and the success of determination frequency automatic calibration or failure according to described controling parameters PARAM and described frequency error value; When described controling parameters PARAM is maximum or minimum value or described frequency error value is zero, described calibration terminates decision circuitry 4 and judges that the frequency automatic calibration of described OSC circuit 2 terminates; When the frequency automatic calibration of described OSC circuit 2 terminates, and the end of described clock signal is when being positioned within described reference time window signal PWIN, described calibration terminates the frequency automatic calibration success that decision circuitry 4 judges described OSC circuit 2, when described frequency error value is less, the frequency of the output of described OSC circuit 2 more close to centre frequency, frequency calibration more accurate.When the frequency automatic calibration of described OSC circuit 2 terminates, and when the end of described clock signal is positioned at outside described reference time window signal PWIN, calibrate unsuccessfully.
Described calibration terminate frequency automatic calibration that decision circuitry 4 judges described OSC circuit 2 not at the end of, described parameter add-subtract control circuit 5 exports a parameter add-subtract control signal to described parametric generator 1, when the frequency of described clock signal OSCOUT is less than described centre frequency, the controling parameters PARAM that described parameter add-subtract control signal makes described parametric generator 1 export adds a value be directly proportional with described frequency error value by currency; When the frequency of described clock signal OSCOUT is greater than described centre frequency, the controling parameters PARAM that described parameter add-subtract control signal makes described parametric generator 1 export deducts a value be directly proportional with described frequency error value by currency.
As shown in Figure 3, be the automatic calibrating method flow chart of embodiment of the present invention OSC frequency automatic calibration circuit.The embodiment of the present invention uses the automatic calibrating method of OSC frequency automatic calibration circuit to comprise the steps:
Described controling parameters PARAM is set to parameter median by step one, described parametric generator 1 circuit 1.Described parameter median is the controling parameters PARAM value that the clock signal OSCOUT frequency that described OSC circuit 2 is exported equals center frequency value maximum probability.
The output of step 2, described OSC circuit 2 exports the frequency clock signal OSCOUT corresponding with described controling parameters PARAM.
Step 3, described frequency error detection circuit 3 carry out frequency error detection to the clock signal that described OSC circuit 2 exports, and whether the end that detects the clock signal OSCOUT that described OSC circuit 2 exports calculates described frequency error value within described reference time window signal PWIN.The concrete calculating of described frequency error value can refer to Fig. 4 and Fig. 5.
The clock signal OSCOUT counting that described OSC circuit 2 exports N time, it is pnclk that N is more than or equal to curve corresponding in 2, Fig. 4 and Fig. 5; Described reference time window signal PWIN be the maximum effective frequency in N number of cycle clock signal end to the minimum effective frequency in N number of cycle clock signal end between signal, curve corresponding in Fig. 4 and Fig. 5 is pwin; Described centre frequency index signal PCENT is the rising edge signal of the clock signal end of the centre frequency being positioned at N number of cycle, and curve corresponding in Fig. 4 and Fig. 5 is pcent.The curve that described frequency error value is corresponding is the curve pcnt in Fig. 4 and Fig. 5.
If the end of the clock signal that described OSC circuit 2 exports is within described reference time window signal PWIN, described frequency error value is adopt centre frequency to carry out the periodicity counted between the end of the clock signal that described OSC circuit 2 exports and described centre frequency index signal PCENT.As shown in Figure 4, the clock signal frequency that OSC circuit exports is greater than centre frequency, the counting end of the clock signal that described OSC circuit 2 exports be positioned at the rising edge corresponding to centre frequency of described centre frequency index signal PCENT before front end, the curve signal pcnt that described frequency error value is corresponding is also positioned at the rising edge front end corresponding to centre frequency of described centre frequency index signal PCENT.As shown in Figure 5, the clock signal frequency that OSC circuit exports is less than centre frequency, and the curve pcnt that described frequency error value is corresponding is positioned at the rising edge rear end corresponding to centre frequency of described centre frequency index signal PCENT.
If the end of the clock signal that described OSC circuit 2 exports does not arrive the front end of described reference time window signal PWIN or the end beyond described reference time window signal PWIN when the end of the clock signal that described OSC circuit 2 exports is outside described reference time window signal PWIN, then described frequency error value is excessive, the frequency of the clock signal exported is beyond effective range, now the computational methods of described frequency error value are: if the frequency that the end of the clock signal OSCOUT of described OSC circuit 2 output does not arrive the front end of described reference time window signal PWIN and the clock signal OSCOUT of described OSC circuit 2 output is greater than maximum effective frequency, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the front end of described reference time window signal PWIN and described centre frequency index signal PCENT, also namely described frequency error value is calculated with the clock signal OSCOUT that frequency is maximum effective frequency, if the frequency that the end of the clock signal OSCOUT that described OSC circuit 2 exports exceeds the rear end of described reference time window signal PWIN and the clock signal OSCOUT of described OSC circuit 2 output is less than minimum effective frequency, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the rear end of described reference time window signal PWIN and described centre frequency index signal PCENT, also namely calculates described frequency error value with the clock signal OSCOUT that frequency is minimum effective frequency.Can find out, the frequency error value maximum count scope of the embodiment of the present invention is the counting in the front end of reference time window signal PWIN or time span between rear end and centre frequency index signal PCENT.
Step 4, judge that whether the frequency of the clock signal OSCOUT that described OSC circuit 2 exports is identical with described centre frequency according to described frequency error value, if identical i.e. described frequency error value is zero, described calibration terminates decision circuitry 4 and judges the frequency automatic calibration success of described OSC circuit 2 and terminate calibration; If the frequency of the clock signal OSCOUT that described OSC circuit 2 exports is not identical with described centre frequency, then carry out step 5.
Step 5, judge whether described controling parameters PARAM is maximum or minimum value; If described controling parameters PARAM is maximum or minimum value, described calibration terminates decision circuitry 4 and judges that the frequency automatic calibration of described OSC circuit 2 terminates, if the end of the clock signal that described OSC circuit 2 exports is within described reference time window signal PWIN, calibrate successfully, if the end of the clock signal of described OSC circuit 2 output is not within described reference time window signal PWIN, calibrate failure; If described controling parameters PARAM is not maximum or minimum value, then carry out step 6.
Step 6, described parameter add-subtract control circuit 5 export a parameter add-subtract control signal to described parametric generator 1, when the frequency of described clock signal OSCOUT is less than described centre frequency, the controling parameters PARAM that described parameter add-subtract control signal makes described parametric generator 1 export adds a value be directly proportional with described frequency error value by currency; When the frequency of described clock signal OSCOUT is greater than described centre frequency, the controling parameters PARAM that described parameter add-subtract control signal makes described parametric generator 1 export deducts a value be directly proportional with described frequency error value by currency; After described controling parameters PARAM adjusts, jump to step 2 and proceed calibration.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. an oscillator frequency auto-calibration circuits, is characterized in that, comprising: parametric generator, pierce circuit, frequency error detection circuit, and calibration terminates decision circuitry, parameter add-subtract control circuit;
The output of described parametric generator exports controling parameters to described pierce circuit;
The output of described pierce circuit exports a clock signal to described frequency error detection circuit, the frequency size of described clock signal is regulated by described controling parameters, the frequency of larger, the described clock signal of described controling parameters is larger, and the frequency of less, the described clock signal of described controling parameters is less;
The input of described frequency error detection circuit connects a reference time window signal and a centre frequency index signal, described frequency error detection circuit carries out frequency error detection according to described reference time window signal and centre frequency index signal to described clock signal, and whether the end that detects the clock signal that described pierce circuit exports calculates described frequency error value within described reference time window signal; Described reference time window signal defines the frequency valid value range of described clock signal, and described centre frequency index signal defines the size of center frequency value; Described frequency error value is larger, the frequency of described clock signal and the difference of described centre frequency larger;
Described calibration terminates decision circuitry and judges whether the frequency automatic calibration of described pierce circuit terminates and the success of determination frequency automatic calibration or failure according to described controling parameters and described frequency error value; When described controling parameters is maximum or minimum value or described frequency error value is zero, described calibration terminates decision circuitry and judges that the frequency automatic calibration of described pierce circuit terminates; When the frequency automatic calibration of described pierce circuit terminates, and when the end of described clock signal is positioned within described reference time window signal, described calibration terminates the frequency automatic calibration success that decision circuitry judges described pierce circuit;
The frequency automatic calibration of described pierce circuit not at the end of, described parameter add-subtract control circuit exports a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export adds a value be directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export deducts a value be directly proportional with described frequency error value by currency;
If the end of the clock signal that described pierce circuit exports is within described reference time window signal, described frequency error value is adopt centre frequency to carry out the periodicity counted between the end of the clock signal that described pierce circuit exports and described centre frequency index signal;
If the end of the clock signal that described pierce circuit exports does not arrive the front end of described reference time window signal, or beyond the end of described reference time window signal, then described frequency error value is excessive, the frequency of the clock signal exported is beyond effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described pierce circuit output does not arrive the front end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal that described pierce circuit exports exceeds the rear end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the rear end of described reference time window signal and described centre frequency index signal.
2. oscillator frequency auto-calibration circuits as claimed in claim 1, is characterized in that: the clock signal counting that described pierce circuit exports N time, and N is more than or equal to 2; Described reference time window signal be the maximum effective frequency in N number of cycle clock signal end to the minimum effective frequency in N number of cycle clock signal end between signal; Described centre frequency index signal is the rising edge signal of the clock signal end of the centre frequency being positioned at N number of cycle.
3. an oscillator frequency automatic calibrating method, is characterized in that, uses oscillator frequency auto-calibration circuits as claimed in claim 1, and comprises the steps:
Described controling parameters is set to parameter median by step one, described parametric generator;
The output of step 2, described pierce circuit exports the frequency clock signal corresponding with described controling parameters;
Step 3, described frequency error detection circuit carry out frequency error detection to the clock signal that described pierce circuit exports, and whether the end that detects the clock signal that described pierce circuit exports calculates described frequency error value within described reference time window signal;
Step 4, judge that whether the frequency of the clock signal that described pierce circuit exports is identical with described centre frequency according to described frequency error value, if identical, described calibration terminates decision circuitry and judges the frequency automatic calibration success of described pierce circuit and terminate calibration; If the frequency of the clock signal that described pierce circuit exports is not identical with described centre frequency, then carry out step 5;
Step 5, judge whether described controling parameters is maximum or minimum value; If described controling parameters is maximum or minimum value, described calibration terminates decision circuitry and judges that the frequency automatic calibration of described pierce circuit terminates, if the end of the clock signal that described pierce circuit exports is within described reference time window signal, calibrate successfully, if the end of the clock signal of described pierce circuit output is not within described reference time window signal, calibrate failure; If described controling parameters is not maximum or minimum value, then carry out step 6;
Step 6, described parameter add-subtract control circuit export a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export adds a value be directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, the controling parameters that described parameter add-subtract control signal makes described parametric generator export deducts a value be directly proportional with described frequency error value by currency; After described controling parameters adjustment, jump to step 2 and proceed calibration.
4. oscillator frequency automatic calibrating method as claimed in claim 3, is characterized in that: the median of parameter described in step one is the controling parameters value that the clock signal that described pierce circuit is exported equals center frequency value maximum probability again and again.
5. oscillator frequency automatic calibrating method as claimed in claim 3, is characterized in that: the clock signal counting that described pierce circuit exports N time, and N is more than or equal to 2; Described reference time window signal be the maximum effective frequency in N number of cycle clock signal end to the minimum effective frequency in N number of cycle clock signal end between signal; Described centre frequency index signal is the rising edge signal of the clock signal end of the centre frequency being positioned at N number of cycle.
6. the oscillator frequency automatic calibrating method as described in claim 3 or 5, it is characterized in that: if the end of the clock signal that described pierce circuit exports is within described reference time window signal in step 3, described frequency error value is adopt centre frequency to carry out the periodicity counted between the end of the clock signal that described pierce circuit exports and described centre frequency index signal;
If the end of the clock signal that described pierce circuit exports does not arrive the front end of described reference time window signal, or beyond the end of described reference time window signal, then described frequency error value is excessive, the frequency of the clock signal exported is beyond effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described pierce circuit output does not arrive the front end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal that described pierce circuit exports exceeds the rear end of described reference time window signal, then described frequency error value is adopt centre frequency to carry out the periodicity counted between the rear end of described reference time window signal and described centre frequency index signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210289181.5A CN103634003B (en) | 2012-08-14 | 2012-08-14 | OSC frequency automatic calibration circuit and automatic calibrating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210289181.5A CN103634003B (en) | 2012-08-14 | 2012-08-14 | OSC frequency automatic calibration circuit and automatic calibrating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103634003A CN103634003A (en) | 2014-03-12 |
| CN103634003B true CN103634003B (en) | 2016-02-10 |
Family
ID=50214693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210289181.5A Active CN103634003B (en) | 2012-08-14 | 2012-08-14 | OSC frequency automatic calibration circuit and automatic calibrating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103634003B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103634003B (en) * | 2012-08-14 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibrating method |
| CN105577185B (en) * | 2014-10-09 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibrations circuit and automatic calibrating method |
| CN106059579B (en) * | 2016-06-28 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | A kind of OSC frequency automatic calibration and the circuit structure and method of test |
| CN107196649A (en) * | 2017-05-30 | 2017-09-22 | 长沙方星腾电子科技有限公司 | A kind of oscillator with frequency self-calibration function |
| CN109976955B (en) * | 2017-12-28 | 2023-02-21 | 上海坚芯电子科技有限公司 | Clock frequency test circuit and measuring and calculating method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1134921A2 (en) * | 2000-03-17 | 2001-09-19 | Nokia Corporation | Adjustment of oscillator |
| CN1338150A (en) * | 1999-01-22 | 2002-02-27 | 艾利森电话股份有限公司 | Oscillator using calibration means |
| CN1388903A (en) * | 2000-06-23 | 2003-01-01 | 密克罗奇普技术公司 | Method, system and apparatus for calibrating a pulse position modulation (PPM) decoder to a PPM signal |
| EP1551102A1 (en) * | 2003-12-29 | 2005-07-06 | STMicroelectronics S.r.l. | Device for calibrating the frequency of an oscillator, phase looked loop circuit comprising said calibration device and related frequency calibration method. |
| CN101257302A (en) * | 2007-02-27 | 2008-09-03 | 北京朗波芯微技术有限公司 | Frequency adjusting method of oscillator and decimal fraction frequency dividing phase-locked loop frequency synthesizer |
| CN102291130A (en) * | 2011-04-02 | 2011-12-21 | 长沙景嘉微电子有限公司 | Locking detection circuit with programmable locking accuracy and locking frequency |
| CN103634003A (en) * | 2012-08-14 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibration method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100847686B1 (en) * | 2006-10-12 | 2008-07-23 | (주)에프씨아이 | Phase Locked Loop having continuous bank calibration unit and method to prevent unlocking PLL |
-
2012
- 2012-08-14 CN CN201210289181.5A patent/CN103634003B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1338150A (en) * | 1999-01-22 | 2002-02-27 | 艾利森电话股份有限公司 | Oscillator using calibration means |
| EP1134921A2 (en) * | 2000-03-17 | 2001-09-19 | Nokia Corporation | Adjustment of oscillator |
| CN1388903A (en) * | 2000-06-23 | 2003-01-01 | 密克罗奇普技术公司 | Method, system and apparatus for calibrating a pulse position modulation (PPM) decoder to a PPM signal |
| EP1551102A1 (en) * | 2003-12-29 | 2005-07-06 | STMicroelectronics S.r.l. | Device for calibrating the frequency of an oscillator, phase looked loop circuit comprising said calibration device and related frequency calibration method. |
| CN101257302A (en) * | 2007-02-27 | 2008-09-03 | 北京朗波芯微技术有限公司 | Frequency adjusting method of oscillator and decimal fraction frequency dividing phase-locked loop frequency synthesizer |
| CN102291130A (en) * | 2011-04-02 | 2011-12-21 | 长沙景嘉微电子有限公司 | Locking detection circuit with programmable locking accuracy and locking frequency |
| CN103634003A (en) * | 2012-08-14 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibration method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103634003A (en) | 2014-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103634003B (en) | OSC frequency automatic calibration circuit and automatic calibrating method | |
| CN103248356B (en) | A kind of counter and implementation method based on adopting phase-locked loop pulse interpolation technology | |
| CN101026781B (en) | Quasi full-synchronous high-precision rapid frequency measuring device and method | |
| CN104901687B (en) | Clock frequency calibration method and system | |
| CN103616814A (en) | Synchronous sampling clock closed loop correcting method and system based on FPGA | |
| CN105790756B (en) | A kind of method and device communicating calibration clock using UART | |
| CN103048538A (en) | Method for testing collective frequency of radio frequency card and tester for realizing method | |
| CN104407510B (en) | A kind of method and apparatus of time service | |
| CN204214984U (en) | The proving installation of touch screen function sheet | |
| TW201303315A (en) | Method and system for measuring frequency | |
| CN103728553A (en) | Method for verifying electric energy measuring chip | |
| CN103487649A (en) | Method and device capable of measuring both frequency of continuous waves and frequency of pulse modulation carrier waves | |
| CN105790736A (en) | Trimming device for frequency signal generation chip | |
| CN106645952A (en) | Signal phase difference detection method and system | |
| CN104679375A (en) | Method and device for optimizing signal-to-noise ratio parameter | |
| CN102739085B (en) | Inverter phase sequence detection phase locking device and phase locking and phase sequence identifying method | |
| CN104330644B (en) | The method and system of sine wave signal amplitude in detection power system | |
| CN107678333B (en) | Step length time correction method and device based on equivalent time sequence sampling | |
| CN109188077A (en) | A kind of signal frequency measuring method, system, device and readable storage medium storing program for executing | |
| CN102457268B (en) | Implementation method for 32-bit capture register | |
| CN104382611A (en) | Correction method and device of output energy of photomultiplier | |
| CN105577185B (en) | OSC frequency automatic calibrations circuit and automatic calibrating method | |
| CN202393904U (en) | Error verifying device used for electric energy metering device | |
| CN109617528A (en) | It is a kind of for correcting the method and its system of active oscillator frequency | |
| CN111830349B (en) | Power grid event detection method and device and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |