CN103634003A - OSC frequency automatic calibration circuit and automatic calibration method - Google Patents
OSC frequency automatic calibration circuit and automatic calibration method Download PDFInfo
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- CN103634003A CN103634003A CN201210289181.5A CN201210289181A CN103634003A CN 103634003 A CN103634003 A CN 103634003A CN 201210289181 A CN201210289181 A CN 201210289181A CN 103634003 A CN103634003 A CN 103634003A
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Abstract
The invention discloses an OSC frequency automatic calibration circuit comprising a parameter generator, an OSC circuit, a frequency error detection circuit, a calibration ending judgment circuit and a parameter adding and subtracting control circuit. The frequency error detection circuit is connected with a reference time window signal and a center frequency indication signal, and frequency error detection is performed on a clock signal according to the reference time window signal and the center frequency indication signal, and a frequency error value is calculated. The calibration ending judgment circuit judges whether frequency automatic calibration is ended or not and whether frequency automatic calibration is successful or failed. When calibration is not ended, the parameter adding and subtracting control circuit outputs a parameter adding and subtracting control signal to the parameter generator and adjusts a control parameter, wherein the adjusting amplitude is directly proportional to the frequency error value. The invention discloses an automatic calibration method of the OSC frequency automatic calibration circuit. The circuit is simple in detection principle and small in circuit area. Parameter adjustment is directly proportional to the frequency error value so that calibration speed can be enhanced.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of OSC(oscillator) frequency automatic calibration circuit; The invention still further relates to a kind of automatic calibrating method of OSC frequency automatic calibration circuit.
Background technology
The method of existing OSC automatic calibration is the clock signal of OSC circuit output to be counted in length in a preset time, the absolute value that size by this count value deducts the count value of standard frequency clock signal and tries to achieve both differences is used as frequency error, in order to judge whether the clock signal frequency of OSC circuit output reaches calibration.
As shown in Figure 1, be existing OSC frequency automatic calibration circuit structure diagram.Existing OSC frequency automatic calibration circuit comprises: OSC circuit 101, timer counter circuit 102, absolute error counting circuit 103, minimal error and parameter are posted device 104, calibration finishes decision circuitry 105, single step parameter regulating circuit 106 etc.The concrete automatic calibration flow process of existing OSC frequency automatic calibration circuit is:
1, a preset initial value is to the adjustment parameter PARAM of OSC circuit 101, and the value that default minimal error and parameter are posted the minimal error register in device 104 is a register maximum.
2, time delay certain hour is after the clock signal OSCOUT of OSC circuit 101 outputs stablizes, and the clock signal OSCOUT of OSC circuit 101 outputs of 102 couples of set time T1 of timer counter circuit counts.
3, the count results of absolute error counting circuit 103 use timer counter circuit 102 deduct standard frequency clock signal at T1 the count value in the time, and ask absolute value, using this as frequency error.
4, the value of comparison frequency error and minimal error register, if frequency error is less than the value of minimal error register, the value of minimal error register is rewritten as to this frequency error value, simultaneously parameter value PARAM is now recorded to minimal error and parameter is posted in the minimal error parameter register of device 104.
5, whether the 105 judgement calibrations of calibration end decision circuitry complete, and judge whether unidirectional maximum or the minimum value adjusted to of parameter value PARAM.If completed, adjustment parameter PARAM is arranged to the value of minimal error parameter register, the most accurate frequency of OSC circuit 101 output, completes automatic calibration; Otherwise, carry out the 6th step.
6,106 single steps of single step parameter regulating circuit change adjusting parameter PARAM, re-execute step 2.
Existing OSC frequency automatic calibration method has following shortcoming:
Due to certain hour total length is counted, because output frequency size is uncertain, counting circuit is larger.
The parameter adjustment step pitch of parameter scanning is little, completes the required testing time carrying out of automatic calibration many.The alignment time needing is long.
Error need to take absolute value, and needs extra absolute value counting circuit.
In parameter scanning process, need special register to record minimum frequency error amount and corresponding parameter value thereof.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of OSC frequency automatic calibration circuit, can accelerate calibration process and reduce circuit area.For this reason, the present invention also provides a kind of automatic calibrating method of the OSC of use frequency automatic calibration circuit.
For solving the problems of the technologies described above, OSC frequency automatic calibration circuit provided by the invention, is characterized in that, comprising: parametric generator, and OSC circuit, frequency error detection circuit, calibration finishes decision circuitry, parameter add-subtract control circuit.
The output output of described parametric generator is controlled parameter to described OSC circuit.
The output of described OSC circuit is exported a clock signal to described frequency error detection circuit, the frequency size of described clock signal is regulated by described control parameter, described control parameter frequency larger, described clock signal is larger, and described control parameter frequency less, described clock signal is less.
The input of described frequency error detection circuit connects a reference time window signal and a centre frequency index signal, described frequency error detection circuit carries out frequency error detection according to described reference time window signal and centre frequency index signal to described clock signal, detects the end of clock signal of described OSC circuit output whether within described reference time window signal and calculate described frequency error value; Described reference time window signal defines the frequency valid value range of described clock signal, and described centre frequency index signal defines the size of center frequency value; Described frequency error value is larger, and the frequency of described clock signal and the difference of described centre frequency are larger.
Described calibration finishes decision circuitry and judges according to described control parameter and described frequency error value whether the frequency automatic calibration of described OSC circuit finishes and the success of determination frequency automatic calibration or failure; When described control parameter is maximum or minimum value or described frequency error value while being zero, described calibration finishes the frequency automatic calibration that decision circuitry judges described OSC circuit and finishes; When the frequency automatic calibration of described OSC circuit finishes, and the end of described clock signal is while being positioned within described reference time window signal, and described calibration finishes the frequency automatic calibration success that decision circuitry judges described OSC circuit.
When the frequency automatic calibration of described OSC circuit does not finish, described parameter add-subtract control circuit is exported a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output add a value being directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output deduct a value being directly proportional with described frequency error value by currency.
Further improvement is, the clock signal counting of described OSC circuit output N time, and N is more than or equal to 2; Described reference time window signal is that clock signal end at the maximum effective frequency in N cycle is to the signal between the clock signal end of the minimum effective frequency in N cycle; Described centre frequency index signal is the rising edge signal of clock signal end that is positioned at the centre frequency in N cycle.
Further improve and be, if the end of the clock signal of described OSC circuit output is within described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the end of clock signal of described OSC circuit output and described centre frequency index signal.If the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, or exceeded the end of described reference time window signal, described frequency error value is excessive, the frequency of the clock signal of output has exceeded effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal of described OSC circuit output exceeds the rear end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the rear end of described reference time window signal and described centre frequency index signal.
For solving the problems of the technologies described above, the automatic calibrating method of use OSC frequency automatic calibration circuit provided by the invention comprises the steps:
Step 1, the described control parameter of described parametric generator are set to parameter median.
The output of step 2, described OSC circuit is exported a frequency and the corresponding clock signal of described control parameter.
Step 5, judge whether described control parameter is maximum or minimum value; If described control parameter is maximum or minimum value, described calibration finishes the frequency automatic calibration that decision circuitry judges described OSC circuit and finishes, if the end of the clock signal of described OSC circuit output, within described reference time window signal, is calibrated successfully, if the end of the clock signal of described OSC circuit output is not within described reference time window signal, calibrate unsuccessfully; If described control parameter is not maximum or minimum value, carry out step 6.
Step 6, described parameter add-subtract control circuit are exported a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output add a value being directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output deduct a value being directly proportional with described frequency error value by currency; After described control parameter adjustment, jump to step 2 and proceed calibration.
Further improve and be, the median of parameter described in step 1 is to make the clock signal of described OSC circuit output again and again equal the control parameter value of center frequency value maximum probability.
Further improvement is, the clock signal counting of described OSC circuit output N time, and N is more than or equal to 2; Described reference time window signal is that clock signal end at the maximum effective frequency in N cycle is to the signal between the clock signal end of the minimum effective frequency in N cycle; Described centre frequency index signal is the rising edge signal of clock signal end that is positioned at the centre frequency in N cycle.
Further improve and be, if the end of the clock signal of described OSC circuit output is within described reference time window signal in step 3, described frequency error value is the periodicity that adopts centre frequency to count between the end of clock signal of described OSC circuit output and described centre frequency index signal.If the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, or exceeded the end of described reference time window signal, described frequency error value is excessive, the frequency of the clock signal of output has exceeded effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal of described OSC circuit output exceeds the rear end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the rear end of described reference time window signal and described centre frequency index signal.
Beneficial effect of the present invention is:
1, frequency error detection electric circuit inspection principle of the present invention is simple, counting in the front end that frequency error value maximum count scope of the present invention is reference time window signal or the time span between rear end and centre frequency index signal, compared to the prior art, the present invention does not need the time total length of clock signal to count, therefore counting circuit is less; The present invention does not need extra absolute value counting circuit yet, therefore circuit area of the present invention is little.
2, during calibration of the present invention, adjustment and the frequency error value of the control parameter of OSC circuit are directly proportional, and when frequency error value is large, control the adjusting range of parameter more greatly; And frequency error value hour, the adjusting range of controlling parameter is less.With in prior art, by parameter scanning mode, carry out parameter adjustment, the step pitch of control parameter adjustment of the present invention is large, can greatly reduce the required testing time carrying out of automatic calibration, reduces the alignment time, accelerates calibration speed.
3, the present invention is except calibrating unsuccessfully, and when calibration finishes, the clock signal frequency of output is minimal error frequency, does not need special register to record minimum frequency error amount and corresponding parameter value thereof.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing OSC frequency automatic calibration circuit structure diagram;
Fig. 2 is embodiment of the present invention OSC frequency automatic calibration circuit structure diagram;
Fig. 3 is the automatic calibrating method flow chart of embodiment of the present invention OSC frequency automatic calibration circuit;
Fig. 4 is the detection sequential chart when the clock signal frequency of OSC circuit output is greater than centre frequency in embodiment of the present invention method;
Fig. 5 is the detection sequential chart when the clock signal frequency of OSC circuit output is less than centre frequency in embodiment of the present invention method.
Embodiment
As shown in Figure 2, be embodiment of the present invention OSC frequency automatic calibration circuit structure diagram; Embodiment of the present invention OSC frequency automatic calibration circuit comprises: parametric generator 1, and OSC circuit 2, frequency error detection circuit 3, calibration finishes decision circuitry 4, parameter add-subtract control circuit 5.
The output output of described parametric generator 1 is controlled parameter PARAM to described OSC circuit 2.
The output of described OSC circuit 2 is exported a clock signal OSCOUT to described frequency error detection circuit 3, the frequency size of described clock signal OSCOUT is regulated by described control parameter PARAM, described control parameter PARAM is larger, described clock signal OSCOUT, and frequency is larger, and described control parameter PARAM frequency less, described clock signal OSCOUT is less.
The input of described frequency error detection circuit 3 also connects a reference time window signal PWIN and a centre frequency index signal PCENT, described frequency error detection circuit 3 carries out frequency error detection according to described reference time window signal PWIN and centre frequency index signal PCENT to described clock signal OSCOUT, detects the end of clock signal OSCOUT of described OSC circuit 2 outputs whether within described reference time window signal PWIN and calculate described frequency error value; Described reference time window signal PWIN defines the frequency valid value range of described clock signal, and described centre frequency index signal PCENT defines the size of center frequency value; Described frequency error value is larger, and the frequency of described clock signal OSCOUT and the difference of described centre frequency are larger.
As shown in Figure 4, be the detection sequential chart when the clock signal frequency of OSC circuit output is greater than centre frequency in embodiment of the present invention method; As shown in Figure 5, be the detection sequential chart when the clock signal frequency of OSC circuit output is less than centre frequency in embodiment of the present invention method.The clock signal OSCOUT counting of described OSC circuit 2 outputs N time, it is pnclk that N is more than or equal to curve corresponding in 2, Fig. 4 and Fig. 5; Described reference time window signal PWIN be clock signal end at the maximum effective frequency in N cycle to the signal between the clock signal end of the minimum effective frequency in N cycle, curve corresponding in Fig. 4 and Fig. 5 is pwin; Described centre frequency index signal PCENT is the rising edge signal of clock signal end that is positioned at the centre frequency in N cycle, and curve corresponding in Fig. 4 and Fig. 5 is pcent.The curve that described frequency error value is corresponding is the curve pcnt in Fig. 4 and Fig. 5.
If the end of the clock signal of described OSC circuit 2 outputs is within described reference time window signal PWIN, described frequency error value is the periodicity that adopts centre frequency to count between the end of clock signal of described OSC circuit 2 outputs and described centre frequency index signal PCENT.As shown in Figure 4, the clock signal frequency of OSC circuit output is greater than centre frequency, the end of the clock signal of described OSC circuit 2 outputs is positioned at the corresponding rising edge front end of centre frequency of described centre frequency index signal PCENT, and the curve pcnt that described frequency error value is corresponding is also positioned at the corresponding rising edge front end of centre frequency of described centre frequency index signal PCENT.As shown in Figure 5, the clock signal frequency of OSC circuit output is less than centre frequency, and the curve pcnt that described frequency error value is corresponding is positioned at the corresponding rising edge of the centre frequency rear end of described centre frequency index signal PCENT.
If the end of the clock signal of described OSC circuit 2 outputs does not arrive the front end of described reference time window signal PWIN, or exceeded the end of described reference time window signal PWIN, described frequency error value is excessive, the frequency of the clock signal of output has exceeded effective range, now the computational methods of described frequency error value are: if the end of the clock signal OSCOUT of described OSC circuit 2 output does not arrive the front end of described reference time window signal PWIN, be that the frequency of the clock signal OSCOUT of described OSC circuit 2 outputs is greater than maximum effective frequency, described frequency error value is the periodicity that adopts centre frequency to count between the front end of described reference time window signal PWIN and described centre frequency index signal PCENT, also with the clock signal OSCOUT that frequency is maximum effective frequency, calculate described frequency error value, if it is that the frequency of the clock signal OSCOUT of described OSC circuit 2 outputs is less than minimum effective frequency that the end of the clock signal OSCOUT of described OSC circuit 2 outputs exceeds the rear end of described reference time window signal PWIN, described frequency error value is the periodicity that adopts centre frequency to count between the rear end of described reference time window signal PWIN and described centre frequency index signal PCENT, also with the clock signal OSCOUT that frequency is minimum effective frequency, calculates described frequency error value.Can find out, the frequency error value maximum count scope of the embodiment of the present invention is the front end of reference time window signal PWIN or the counting in the time span between rear end and centre frequency index signal PCENT.
Described calibration finishes decision circuitry 4 and judges according to described control parameter PARAM and described frequency error value whether the frequency automatic calibration of described OSC circuit 2 finishes and the success of determination frequency automatic calibration or failure; When described control parameter PARAM is maximum or minimum value or described frequency error value while being zero, the frequency automatic calibration that described calibration finishes the described OSC circuit 2 of decision circuitry 4 judgement finishes; When the frequency automatic calibration of described OSC circuit 2 finishes, and when the end of described clock signal is positioned within described reference time window signal PWIN, described calibration finishes the frequency automatic calibration success of the described OSC circuit 2 of decision circuitry 4 judgement, when described frequency error value less, the frequency of the output of described OSC circuit 2 more approaches centre frequency, frequency calibration more accurate.When the frequency automatic calibration of described OSC circuit 2 finishes, and the end of described clock signal is while being positioned at outside described reference time window signal PWIN, calibrates unsuccessfully.
When the frequency automatic calibration that described calibration finishes the described OSC circuit 2 of decision circuitry 4 judgement does not finish, described parameter add-subtract control circuit 5 output one parameter add-subtract control signals are to described parametric generator 1, when the frequency of described clock signal OSCOUT is less than described centre frequency, described parameter add-subtract control signal makes the control parameter PARAM of described parametric generator 1 output add a value being directly proportional with described frequency error value by currency; When the frequency of described clock signal OSCOUT is greater than described centre frequency, described parameter add-subtract control signal makes the control parameter PARAM of described parametric generator 1 output deduct a value being directly proportional with described frequency error value by currency.
As shown in Figure 3, be the automatic calibrating method flow chart of embodiment of the present invention OSC frequency automatic calibration circuit.The embodiment of the present invention is used the automatic calibrating method of OSC frequency automatic calibration circuit to comprise the steps:
Step 1, the described control parameter of described parametric generator 1 circuit 1 PARAM are set to parameter median.Described parameter median is to make the clock signal OSCOUT frequency of described OSC circuit 2 outputs equal the control parameter PARAM value of center frequency value maximum probability.
The output of step 2, described OSC circuit 2 is exported a frequency and the corresponding clock signal OSCOUT of described control parameter PARAM.
The clock signal of 3 pairs of described OSC circuit 2 outputs of step 3, described frequency error detection circuit is carried out frequency error detection, detects the end of clock signal OSCOUT of described OSC circuit 2 outputs whether within described reference time window signal PWIN and calculate described frequency error value.The concrete calculating of described frequency error value can be with reference to Fig. 4 and Fig. 5.
The clock signal OSCOUT counting of described OSC circuit 2 outputs N time, it is pnclk that N is more than or equal to curve corresponding in 2, Fig. 4 and Fig. 5; Described reference time window signal PWIN be clock signal end at the maximum effective frequency in N cycle to the signal between the clock signal end of the minimum effective frequency in N cycle, curve corresponding in Fig. 4 and Fig. 5 is pwin; Described centre frequency index signal PCENT is the rising edge signal of clock signal end that is positioned at the centre frequency in N cycle, and curve corresponding in Fig. 4 and Fig. 5 is pcent.The curve that described frequency error value is corresponding is the curve pcnt in Fig. 4 and Fig. 5.
If the end of the clock signal of described OSC circuit 2 outputs is within described reference time window signal PWIN, described frequency error value is the periodicity that adopts centre frequency to count between the end of clock signal of described OSC circuit 2 outputs and described centre frequency index signal PCENT.As shown in Figure 4, the clock signal frequency of OSC circuit output is greater than centre frequency, the counting end of the clock signal of described OSC circuit 2 outputs is positioned at front end before the corresponding rising edge of centre frequency of described centre frequency index signal PCENT, and the curve signal pcnt that described frequency error value is corresponding is also positioned at the corresponding rising edge front end of centre frequency of described centre frequency index signal PCENT.As shown in Figure 5, the clock signal frequency of OSC circuit output is less than centre frequency, and the curve pcnt that described frequency error value is corresponding is positioned at the corresponding rising edge of the centre frequency rear end of described centre frequency index signal PCENT.
If the end of the end of the clock signal of the described OSC circuit 2 outputs clock signal that described OSC circuit 2 is exported outside described reference time window signal PWIN time does not arrive the front end of described reference time window signal PWIN or has exceeded the end of described reference time window signal PWIN, described frequency error value is excessive, the frequency of the clock signal of output has exceeded effective range, now the computational methods of described frequency error value are: if the end of the clock signal OSCOUT of described OSC circuit 2 output does not arrive the front end of described reference time window signal PWIN, be that the frequency of the clock signal OSCOUT of described OSC circuit 2 outputs is greater than maximum effective frequency, described frequency error value is the periodicity that adopts centre frequency to count between the front end of described reference time window signal PWIN and described centre frequency index signal PCENT, also with the clock signal OSCOUT that frequency is maximum effective frequency, calculate described frequency error value, if it is that the frequency of the clock signal OSCOUT of described OSC circuit 2 outputs is less than minimum effective frequency that the end of the clock signal OSCOUT of described OSC circuit 2 outputs exceeds the rear end of described reference time window signal PWIN, described frequency error value is the periodicity that adopts centre frequency to count between the rear end of described reference time window signal PWIN and described centre frequency index signal PCENT, also with the clock signal OSCOUT that frequency is minimum effective frequency, calculates described frequency error value.Can find out, the frequency error value maximum count scope of the embodiment of the present invention is the front end of reference time window signal PWIN or the counting in the time span between rear end and centre frequency index signal PCENT.
Step 5, judge whether described control parameter PARAM is maximum or minimum value; If described control parameter PARAM is maximum or minimum value, the frequency automatic calibration that described calibration finishes the described OSC circuit 2 of decision circuitry 4 judgement finishes, if the end of the clock signal of described OSC circuit 2 outputs, within described reference time window signal PWIN, is calibrated successfully, if the end of the clock signal of described OSC circuit 2 outputs is not within described reference time window signal PWIN, calibrate unsuccessfully; If described control parameter PARAM is not maximum or minimum value, carry out step 6.
Step 6, described parameter add-subtract control circuit 5 output one parameter add-subtract control signals are to described parametric generator 1, when the frequency of described clock signal OSCOUT is less than described centre frequency, described parameter add-subtract control signal makes the control parameter PARAM of described parametric generator 1 output add a value being directly proportional with described frequency error value by currency; When the frequency of described clock signal OSCOUT is greater than described centre frequency, described parameter add-subtract control signal makes the control parameter PARAM of described parametric generator 1 output deduct a value being directly proportional with described frequency error value by currency; After described control parameter PARAM adjusts, jump to step 2 and proceed calibration.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. an OSC frequency automatic calibration circuit, is characterized in that, comprising: parametric generator, and OSC circuit, frequency error detection circuit, calibration finishes decision circuitry, parameter add-subtract control circuit;
The output output of described parametric generator is controlled parameter to described OSC circuit;
The output of described OSC circuit is exported a clock signal to described frequency error detection circuit, the frequency size of described clock signal is regulated by described control parameter, described control parameter frequency larger, described clock signal is larger, and described control parameter frequency less, described clock signal is less;
The input of described frequency error detection circuit connects a reference time window signal and a centre frequency index signal, described frequency error detection circuit carries out frequency error detection according to described reference time window signal and centre frequency index signal to described clock signal, detects the end of clock signal of described OSC circuit output whether within described reference time window signal and calculate described frequency error value; Described reference time window signal defines the frequency valid value range of described clock signal, and described centre frequency index signal defines the size of center frequency value; Described frequency error value is larger, and the frequency of described clock signal and the difference of described centre frequency are larger;
Described calibration finishes decision circuitry and judges according to described control parameter and described frequency error value whether the frequency automatic calibration of described OSC circuit finishes and the success of determination frequency automatic calibration or failure; When described control parameter is maximum or minimum value or described frequency error value while being zero, described calibration finishes the frequency automatic calibration that decision circuitry judges described OSC circuit and finishes; When the frequency automatic calibration of described OSC circuit finishes, and the end of described clock signal is while being positioned within described reference time window signal, and described calibration finishes the frequency automatic calibration success that decision circuitry judges described OSC circuit;
When the frequency automatic calibration of described OSC circuit does not finish, described parameter add-subtract control circuit is exported a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output add a value being directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output deduct a value being directly proportional with described frequency error value by currency.
2. OSC frequency automatic calibration circuit as claimed in claim 1, is characterized in that: the clock signal of described OSC circuit output is counted N time, and N is more than or equal to 2; Described reference time window signal is that clock signal end at the maximum effective frequency in N cycle is to the signal between the clock signal end of the minimum effective frequency in N cycle; Described centre frequency index signal is the rising edge signal of clock signal end that is positioned at the centre frequency in N cycle.
3. OSC frequency automatic calibration circuit as claimed in claim 1 or 2, it is characterized in that: if the end of the clock signal of described OSC circuit output within described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the end of clock signal of described OSC circuit output and described centre frequency index signal;
If the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, or exceeded the end of described reference time window signal, described frequency error value is excessive, the frequency of the clock signal of output has exceeded effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal of described OSC circuit output exceeds the rear end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the rear end of described reference time window signal and described centre frequency index signal.
4. the automatic calibrating method of OSC frequency automatic calibration circuit as claimed in claim 1, is characterized in that, comprises the steps:
Step 1, the described control parameter of described parametric generator are set to parameter median;
The output of step 2, described OSC circuit is exported a frequency and the corresponding clock signal of described control parameter;
Step 3, described frequency error detection circuit are carried out frequency error detection to the clock signal of described OSC circuit output, detect the end of clock signal of described OSC circuit output whether within described reference time window signal and calculate described frequency error value;
Step 4, according to described frequency error value, judge that whether frequency and the described centre frequency of clock signal of described OSC circuit output be identical, if identical, described calibration finishes decision circuitry and judges the frequency automatic calibration success of described OSC circuit and finish calibration; If frequency and the described centre frequency of the clock signal of described OSC circuit output are not identical, carry out step 5;
Step 5, judge whether described control parameter is maximum or minimum value; If described control parameter is maximum or minimum value, described calibration finishes the frequency automatic calibration that decision circuitry judges described OSC circuit and finishes, if the end of the clock signal of described OSC circuit output, within described reference time window signal, is calibrated successfully, if the end of the clock signal of described OSC circuit output is not within described reference time window signal, calibrate unsuccessfully; If described control parameter is not maximum or minimum value, carry out step 6;
Step 6, described parameter add-subtract control circuit are exported a parameter add-subtract control signal to described parametric generator, when the frequency of described clock signal is less than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output add a value being directly proportional with described frequency error value by currency; When the frequency of described clock signal is greater than described centre frequency, described parameter add-subtract control signal makes the control parameter of described parametric generator output deduct a value being directly proportional with described frequency error value by currency; After described control parameter adjustment, jump to step 2 and proceed calibration.
5. method as claimed in claim 4, is characterized in that: the median of parameter described in step 1 is to make the clock signal of described OSC circuit output again and again equal the control parameter value of center frequency value maximum probability.
6. method as claimed in claim 4, is characterized in that: the clock signal of described OSC circuit output is counted N time, and N is more than or equal to 2; Described reference time window signal is that clock signal end at the maximum effective frequency in N cycle is to the signal between the clock signal end of the minimum effective frequency in N cycle; Described centre frequency index signal is the rising edge signal of clock signal end that is positioned at the centre frequency in N cycle.
7. the method as described in claim 4 or 6, it is characterized in that: if the end of the clock signal of described OSC circuit output is within described reference time window signal in step 3, described frequency error value is the periodicity that adopts centre frequency to count between the end of clock signal of described OSC circuit output and described centre frequency index signal;
If the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, or exceeded the end of described reference time window signal, described frequency error value is excessive, the frequency of the clock signal of output has exceeded effective range, now the computational methods of described frequency error value are: if the end of the clock signal of described OSC circuit output does not arrive the front end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the front end of described reference time window signal and described centre frequency index signal, if the end of the clock signal of described OSC circuit output exceeds the rear end of described reference time window signal, described frequency error value is the periodicity that adopts centre frequency to count between the rear end of described reference time window signal and described centre frequency index signal.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103634003B (en) * | 2012-08-14 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibrating method |
| CN105577185A (en) * | 2014-10-09 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibration method |
| CN106059579A (en) * | 2016-06-28 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Circuit structure and method for automatically calibrating and testing frequency of OSC |
| CN107196649A (en) * | 2017-05-30 | 2017-09-22 | 长沙方星腾电子科技有限公司 | A kind of oscillator with frequency self-calibration function |
| CN109976955A (en) * | 2017-12-28 | 2019-07-05 | 上海坚芯电子科技有限公司 | A kind of clock rate testing circuit and measuring method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103634003B (en) * | 2012-08-14 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibrating method |
| CN105577185A (en) * | 2014-10-09 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibration circuit and automatic calibration method |
| CN105577185B (en) * | 2014-10-09 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | OSC frequency automatic calibrations circuit and automatic calibrating method |
| CN106059579A (en) * | 2016-06-28 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Circuit structure and method for automatically calibrating and testing frequency of OSC |
| CN106059579B (en) * | 2016-06-28 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | A kind of OSC frequency automatic calibration and the circuit structure and method of test |
| CN107196649A (en) * | 2017-05-30 | 2017-09-22 | 长沙方星腾电子科技有限公司 | A kind of oscillator with frequency self-calibration function |
| CN109976955A (en) * | 2017-12-28 | 2019-07-05 | 上海坚芯电子科技有限公司 | A kind of clock rate testing circuit and measuring method |
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