CN103632960A - RB-IGBT (reverse blocking-insulated gate bipolar transistor) preparation method - Google Patents
RB-IGBT (reverse blocking-insulated gate bipolar transistor) preparation method Download PDFInfo
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- CN103632960A CN103632960A CN201310618201.3A CN201310618201A CN103632960A CN 103632960 A CN103632960 A CN 103632960A CN 201310618201 A CN201310618201 A CN 201310618201A CN 103632960 A CN103632960 A CN 103632960A
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- isolated area
- igbt
- preparation
- type epitaxial
- epitaxial loayer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 abstract 1
- 238000001802 infusion Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention discloses an RB-IGBT (reverse blocking-insulated gate bipolar transistor) preparation method, which comprises the steps: growing an N-type epitaxial layer on a substrate; performing P+ infusion in an area to be isolated; then annealing, and pushing the isolated area deep at the same time. Thus, the isolated area with certain thickness is formed. Then, according the required thickness of an isolated area, the steps are repeated, so the isolated area with required thickness is formed. According to the RB-IGBT preparation method provided by the invention, epitaxy and doping are carried out step by step, a deeper isolated area can be obtained, and the preparation of RB-IGBTs can be realized.
Description
Technical field
The present invention relates to the technical field of IGBT, particularly the preparation method of RB-IGBT.
Background technology
Vocabulary of terms is explained:
IGBT: the initial of insulated gate bipolar transistor is called for short, and a kind of voltage-controlled type power device, is generally applied as high-voltage switch gear;
RB-IGBT: reverse blocking IGBT, can bear collector electrode-emitter reverse biased.
The structure of conventional I GBT includes source region and termination environment.The effect of termination environment is that raising forward is withstand voltage, can bear the voltage of requirement when forward turn-offs.Conventional I GBT is only operated in forward conduction and forward turn-offs two states.
Yet some application scenario needs IGBT can be operated in the state of reverse shutoff, and conventional I GBT does not have reverse terminal structure, oppositely withstand voltage very little.RB-IGBT increases isolated area on the basis of conventional I GBT, and reverse terminal structure, makes device can bear the voltage of requirement when oppositely turn-offing.
Existing RB-IGBT manufacturing technology, immediate with the present invention is positive thermal diffusion isolation technology.Concrete grammar is: before conventional I GBT processing step starts, by long thermal diffusion, at the formation P of surrounding of chip moldeed depth diffusion zone.Then start to do the Facad structure of chip, include source region and termination environment.Do again afterwards structure, form the collector electrode being communicated with P moldeed depth diffusion zone.Fig. 1 has provided the structural representation that forms the RB-IGBT of isolated area by positive thermal diffusion.Wherein, effective district refers to have the region of chip structure cell and front terminal structure.P+ region around forms by long thermal diffusion, is isolated area (every chip is kept apart), and isolated area connects front and the back side of chip, in the central authorities of isolated area, carries out scribing.
The long thermal diffusion process of above Technology Need, not only length consuming time, and pyroprocess causes heat budget high, and the isolated area of formation is because the area that the reason of horizontal proliferation accounts for is also very large.Form enough dark isolated area cost larger, range of application is also difficult to extend to high tension apparatus, because the thickness of high tension apparatus is difficult to adulterate by the method for thermal diffusion.
Summary of the invention
Technical problem to be solved by this invention is to provide the preparation method of a kind of RB-IGBT, solves the problem that is difficult to obtain darker isolated area that existing RB-IGBT preparation method exists.
For solving the problems of the technologies described above, the invention provides the preparation method of a kind of RB-IGBT, comprise:
Step 1: at IGBT Grown one deck N-type epitaxial loayer;
Step 2: to needing the region of isolation to adulterate in described N-type epitaxial loayer, form isolated area, then annealing pushes away described isolated area deeply simultaneously;
Step 3: superficial growth one deck N-type epitaxial loayer of the N-type epitaxial loayer forming in previous step;
Step 4: need the region of isolation to adulterate in the described N-type epitaxial loayer that previous step is formed, form isolated area;
Isolated area thickness as required, repeating said steps three and step 4.
Further, described doping comprises P+ injects, and after forming described isolated area, when annealing, and described isolated area is pushed away deeply.
Further, described doping is included in N-type epitaxial loayer by grooving and fills the P type polysilicon adulterating, and carries out thermal diffusion.
The preparation method of RB-IGBT provided by the invention, the method that substep carries out extension and doping, can obtain darker isolated area, realizes the preparation of RB-IGBT.
Accompanying drawing explanation
Fig. 1 is for forming the structural representation of the RB-IGBT of isolated area by positive thermal diffusion;
The preparation method that Fig. 2 is the RB-IGBT that uses the embodiment of the present invention and provide forms the structural representation of the RB-IGBT of isolated area;
Wherein, scribe line has represented the scope of a chip unit; Dotted line comprises the letter at two, be in drawing tools cross-hatching carry figure, all have need mark as the place of this hatching of scribe line, be all the similar figure of use.
Embodiment
Fig. 2 has provided the isolation region structure schematic diagram that adopts the preparation method of the RB-IGBT that the embodiment of the present invention provides to form.Different from the technology shown in Fig. 1, isolated area is not to form by long thermal diffusion, but forms by the mode of substep extension Implantation.Wherein, effective district refers to have the region of chip structure cell and front terminal structure.
The preparation method of the RB-IGBT that the embodiment of the present invention provides, first at Grown one deck N-type epitaxial loayer, and carries out P+ injection in the region of needs isolation, with after annealing, isolated area is pushed away deeply simultaneously.So just formed certain thickness isolated area.Then isolated area thickness as required, repeats above step, forms the isolated area of required thickness.For the structure cell of chip and the processing of positive terminal, and the procedure of processing such as thinning back side, identical with the technical process of common IGBT.
While adulterating after grown epitaxial layer, the present invention is by the method for Implantation propelling, in addition, at epitaxial loayer, by the method for grooving filling, is adulterated and also can be formed isolated area.
The preparation method of the RB-IGBT that the embodiment of the present invention provides, tool has the following advantages:
1) adopt Implantation, prior art, has advantages of that process time is short relatively;
2) compared with prior art, the present invention does not need high temperature thermal process, therefore almost there is no heat budget;
3) isolated area of the present invention is that substep forms, and can repeat multistep as required, can form very dark isolated area, and prior art is to form isolated area by thermal diffusion, is difficult to realize very dark isolated area.
4) there is horizontal proliferation effect in the isolated area that prior art forms, the silicon area of waste is large, has avoided this effect in the present invention.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to example, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (3)
1. a preparation method of RB-IGBT, is characterized in that, comprises:
Step 1: at Grown one deck N-type epitaxial loayer;
Step 2: to needing the region of isolation to adulterate in described N-type epitaxial loayer, form isolated area, then annealing pushes away described isolated area deeply simultaneously;
Step 3: superficial growth one deck N-type epitaxial loayer of the N-type epitaxial loayer forming in previous step;
Step 4: need the region of isolation to adulterate in the described N-type epitaxial loayer that previous step is formed, form isolated area;
Isolated area thickness as required, repeating said steps three and step 4.
2. preparation method as claimed in claim 1, is characterized in that, described doping comprises P+ injects, and after forming described isolated area, when annealing, and described isolated area is pushed away deeply.
3. preparation method as claimed in claim 1, is characterized in that, described doping is included in N-type epitaxial loayer by grooving and fills the P type polysilicon adulterating, and carries out thermal diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310618201.3A CN103632960A (en) | 2013-11-27 | 2013-11-27 | RB-IGBT (reverse blocking-insulated gate bipolar transistor) preparation method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310618201.3A CN103632960A (en) | 2013-11-27 | 2013-11-27 | RB-IGBT (reverse blocking-insulated gate bipolar transistor) preparation method |
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| CN103632960A true CN103632960A (en) | 2014-03-12 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711205A (en) * | 2015-11-16 | 2017-05-24 | 上海联星电子有限公司 | IGBT and manufacturing method thereof |
| CN106711089A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Production method of RB-IGBT chip and RB-IGBT chip |
| CN106711037A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Fabrication method of RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip and RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip |
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| US20090166722A1 (en) * | 2007-12-28 | 2009-07-02 | Alpha & Omega Semiconductor, Ltd: | High voltage structures and methods for vertical power devices with improved manufacturability |
| US20090176341A1 (en) * | 2005-02-25 | 2009-07-09 | Stmicroelectronics S.R.I. | Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process |
| CN101359664B (en) * | 2007-07-31 | 2011-10-05 | 上海贝岭股份有限公司 | N type LDMOS device in BCD process, layout making and manufacturing method |
| CN102290437A (en) * | 2011-09-20 | 2011-12-21 | 上海先进半导体制造股份有限公司 | VDMOS (vertical double-diffusion metal oxide semiconductor) transistor structure and formation method thereof |
| US20130122663A1 (en) * | 2010-08-12 | 2013-05-16 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
-
2013
- 2013-11-27 CN CN201310618201.3A patent/CN103632960A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090176341A1 (en) * | 2005-02-25 | 2009-07-09 | Stmicroelectronics S.R.I. | Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process |
| CN101359664B (en) * | 2007-07-31 | 2011-10-05 | 上海贝岭股份有限公司 | N type LDMOS device in BCD process, layout making and manufacturing method |
| US20090166722A1 (en) * | 2007-12-28 | 2009-07-02 | Alpha & Omega Semiconductor, Ltd: | High voltage structures and methods for vertical power devices with improved manufacturability |
| US20130122663A1 (en) * | 2010-08-12 | 2013-05-16 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device |
| CN102290437A (en) * | 2011-09-20 | 2011-12-21 | 上海先进半导体制造股份有限公司 | VDMOS (vertical double-diffusion metal oxide semiconductor) transistor structure and formation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711089A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Production method of RB-IGBT chip and RB-IGBT chip |
| CN106711037A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Fabrication method of RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip and RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip |
| CN106711205A (en) * | 2015-11-16 | 2017-05-24 | 上海联星电子有限公司 | IGBT and manufacturing method thereof |
| CN106711205B (en) * | 2015-11-16 | 2021-12-21 | 上海联星电子有限公司 | IGBT and manufacturing method thereof |
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Application publication date: 20140312 |