CN103596358B - SMT addition high-density packages multilayer circuit board structure and preparation method thereof - Google Patents

SMT addition high-density packages multilayer circuit board structure and preparation method thereof Download PDF

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Publication number
CN103596358B
CN103596358B CN201310648040.2A CN201310648040A CN103596358B CN 103596358 B CN103596358 B CN 103596358B CN 201310648040 A CN201310648040 A CN 201310648040A CN 103596358 B CN103596358 B CN 103596358B
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Prior art keywords
support plate
metal support
photoresistance film
circuit layer
layer
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CN103596358A (en
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梁新夫
陈灵芝
郁科锋
王津
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Abstract

The present invention relates to a kind of SMT addition high-density packages multilayer circuit board structure and preparation method thereof, described structure includes internal layer circuit layer (1) and outer-layer circuit layer (3), connection copper post (2) it is provided with between described internal layer circuit layer (1) and outer-layer circuit layer (3), described internal layer circuit layer (1) and connection copper post (2) periphery are coated with insulant (9), described internal layer circuit layer (1) back side is provided with SMT copper post (4), described SMT copper post (4) surface configuration has tin layers (5), element (6) it is pasted with in described tin layers (5), described SMT copper post (4), tin layers (5) and element (6) periphery are filled with epoxy resin (7), described outer-layer circuit layer (1) surface and periphery are coated with photosensitive insulant (8).The invention has the beneficial effects as follows: it instead of solder paste coating and forms the surface mount welding zone of solid-state, thus realizes high performance electric connection on the basis of high-density line design and fabrication and ensure with good reliability.

Description

SMT addition high-density packages multilayer circuit board structure and preparation method thereof
Technical field
The present invention relates to a kind of SMT addition high-density packages multilayer circuit board structure and preparation method thereof, belong to technical field of semiconductor encapsulation.
Background technology
The surface mount process of current high-density base board is mainly by locally using steel mesh printing or injecting coating tin cream at the wiring layer Pad of substrate surface, then carries out surface accurate placement element in tin cream region, carries out reflow soldering the most again.
As shown in figure 32, above-mentioned current high-density base board surface mount process has the following disadvantages and defect the multilayer circuit board structure of conventional brush tin cream technique:
1, the glass putty in tin cream or stannum grain have certain size, limit print gap to a certain extent, and the precision of printing depends on the size of metal ingredient in tin cream, and conventional capability can accomplish 50um, it is difficult to accomplishes highdensity design and manufacture;
2, the tin paste layer after coating is liquid (softer) and thicker (general 70-80um), is unfavorable for controlling the spatial stability of element pasted on surface;
3, tin cream is the pasty masses that many kinds of substance is mixed into, and mobility is relatively poor, is easily formed welding zone bubble after reflow soldering, reduces electrical stability;
4, after mount components carries out Reflow Soldering, tin cream softens and element collapses over tin paste layer, easily causes the space between element and line layer too small and cause the unfilled problem of follow-up encapsulation;
5, high-density base board land and frame have certain thickness drop, and during brush tin cream, the placement of printed steel mesh is with to remove operation relatively difficult, and the skew easily causing printed steel mesh position is the most uneven with tin cream, thus can reduce the electrical property of connection.
Summary of the invention
It is an object of the invention to overcome above-mentioned deficiency, a kind of SMT addition high-density packages multilayer circuit board structure and preparation method thereof is provided, it is local electric copper plated pillars on substrate surface circuit, Tin plating on copper post again, replace solder paste coating to form the surface mount welding zone of solid-state, thus on the basis of high-density line design and fabrication, realize high performance electric connection ensure with good reliability.
The object of the present invention is achieved like this: a kind of SMT addition high-density packages multilayer circuit board structure, it includes internal layer circuit layer and outer-layer circuit layer, connection copper post it is provided with between described internal layer circuit layer and outer-layer circuit layer, described internal layer circuit layer and connection copper post periphery are coated with insulant, the described internal layer circuit layer back side is provided with SMT copper post, described SMT copper post surface configuration has stannum layer, it is pasted with element in described tin layers, described SMT copper post, tin layers and element periphery are filled with epoxy resin, described outer-layer circuit layer surface and periphery are coated with photosensitive insulant, described photosensitive insulant offers in the position in outer-layer circuit layer front plants ball region, ball placement is provided with anti oxidation layer in region.
Described internal layer circuit layer and tin layers surface configuration have anti oxidation layer.
A kind of manufacture method of SMT addition high-density packages multilayer circuit board structure, described method comprises the following steps that:
Step one, take metal support plate
Step 2, metal support plate surface preplating copper material
At one layer of copper material thin film of metal support plate electroplating surface;
Step 3, patch photoresistance film
Stick the photoresistance film that can be exposed development respectively in the metal support plate front and the back side completing preplating copper material thin film, described photoresistance film can use wet type photoresistance film or dry type photoresistance film;
Step 4, development are windowed
The metal support plate front utilizing exposure imaging equipment that step 3 completes to paste photoresistance film carries out graph exposure, develops and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to carry out internal layer circuit layer plating, metal support plate front;
Step 5, plating internal layer circuit layer
Metallic circuit layer is electroplated as internal layer circuit layer in the region of metal support plate front removal part photoresistance film in step 4;
Step 6, removal photoresistance film
Remove the photoresistance film on metal support plate surface;
Step 7, patch photoresistance film
The photoresistance film that can be exposed development is sticked at the front and the back side that complete the metal support plate of internal layer circuit layer plating in step 5 respectively;
Step 8, development are windowed
The metal support plate front utilizing exposure imaging equipment that step 7 completes to paste photoresistance film carries out graph exposure, develops and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to be attached the plating of copper post, metal support plate front;
Step 9, plate bonding copper post
Metal level is electroplated as connecting internal layer circuit layer and the copper post of outer-layer circuit layer in the region of metal support plate front removal part photoresistance film in step 8;
Step 10, removal photoresistance film
Remove the photoresistance film on metal support plate surface;
Step 11, covering insulating material layer
At metal support plate front one layer of insulant of covering in order to the insulating barrier done between internal layer circuit layer and outer-layer circuit layer, do basis for follow-up plating outer-layer circuit layer simultaneously;
Step 12, insulant surface are thinning
Insulant surface is carried out mechanical reduction, until exposing connection copper post;
Step 13, insulant surface metalation
Insulant surface is carried out metalized so that it is surface is follow-up can electroplate;
Step 14, patch photoresistance film
Complete metallized metal support plate front and the back side is sticked and can be exposed the photoresistance film of development;
Step 15, development are windowed
Exposure imaging equipment is utilized metal support plate front to carry out graph exposure, develop and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to carry out outer-layer circuit layer plating, metal support plate front;
Step 10 six, plating outer-layer circuit layer
Metallic circuit layer is electroplated as outer-layer circuit layer in the region of metal support plate front removal part photoresistance film in step 15;
Step 10 seven, removal photoresistance film
Remove the photoresistance film on metal support plate surface;
Step 10 eight, fast-etching
Metal support plate front is carried out fast-etching, removes the metal beyond outer-layer circuit layer;
Step 10 nine, coat photosensitive insulant
Complete the photosensitive insulant of metal support plate front surface coated of outer-layer circuit layer;
Step 2 ten, development are windowed
Exposure imaging equipment is utilized metal support plate front to carry out graph exposure, develop and removes partial graphical photoresistance film, to expose the graphics field that the follow-up needs in metal support plate front are processed;
Step 2 11, removal metal support plate
Remove metal support plate and form the wiring board exposing internal layer circuit layer;
Step 2 12, patch photoresistance film
The photoresistance film that can be exposed development is sticked at the wiring board front formed after removing metal support plate and the back side respectively;
Step 2 13, development are windowed
Utilize exposure imaging equipment the wiring board back side is carried out graph exposure, develop with remove partial graphical photoresistance film, with expose the follow-up needs in the wiring board back side carry out electroplate SMT copper post graphics field;
Step 2 14, plating SMT copper post
In step 2 13, electroplate SMT copper post in the region of circuit back removal part photoresistance film, prepare for sequent surface attachment;
Step 2 15, electrotinning
Electrotinning on the SMT copper post that step 2 14 plating is formed, makees place mat for sequent surface attachment;
Step 2 16, removal photoresistance film
Remove the photoresistance film of PCB surface;
Step 2 17, carry out the organic protection of metal
The metal level exposing wiring board front and back carries out organic protection;
Step 2 18, coating help wlding material
Tin plating region coating on circuit back SMT copper post helps wlding material;
Step 2 19, mount components Reflow Soldering
Help the SMT copper post element pasted on surface of wlding material in the coating of circuit back and carry out reflow soldering;
Step 3 ten, epoxy resin plastic packaging
Step 2 19 complete mount components and by Reflow Soldering realize be electrically connected with the wiring board back side carry out epoxy resin plastic packaging.
Compared with prior art, the method have the advantages that
1, the present invention uses direct local selective plated solder layer, and the precision of welding zone is without limitations, and about 20um can accomplish in area size, can accomplish highdensity design and manufacture;
2, the attachment welding zone of the present invention uses electro-coppering post re-plating process of tin and straight forming, and welding zone is solid-state, the spatial stability of element when improve surface mount, thus improves electrical property;
3, plating welding zone Theil indices is close to very belonging to pure tin, produces the risk of welding zone bubble, improve reliability after can being effectively reduced paster welding;
4, the copper post design of welding zone of the present invention adds the gap between mount components and line layer, produces and encapsulate unfilled risk when greatly reducing follow-up encapsulation;
5, the present invention uses plate surface attachment welding zone to replace paste solder printing on high-density base board, can avoid the puzzlement in base plate line region and seal ring thickness drop, simple to operate and can avoid the uneven problem of solder paste coating.
Accompanying drawing explanation
Fig. 1 ~ Figure 30 is one SMT addition high-density packages manufacturing method of multi-layer circuit board each operation schematic diagram of the present invention.
Figure 31 is the schematic diagram of the present invention a kind of SMT addition high-density packages multilayer circuit board structure.
Figure 32 is the schematic diagram of the multilayer circuit board structure of conventional brush tin cream technique.
Wherein:
Internal layer circuit layer 1
Connect copper post 2
Outer-layer circuit layer 3
SMT copper post 4
Tin layers 5
Element 6
Epoxy resin 7
Photosensitive insulant 8
Insulant 9
Anti oxidation layer 10
Plant ball region 11.
Detailed description of the invention
One SMT addition high-density packages multilayer circuit board structure of the present invention, it includes internal layer circuit layer 1 and outer-layer circuit layer 3, connection copper post 2 it is provided with between described internal layer circuit layer 1 and outer-layer circuit layer 3, described internal layer circuit layer 1 and connection copper post 2 periphery are coated with insulant 9, described internal layer circuit layer 1 back side is provided with SMT copper post 4, described SMT copper post 4 surface configuration has tin layers 5, it is pasted with element 6 in described tin layers 5, described SMT copper post 4, tin layers 5 and element 6 periphery are filled with epoxy resin 7, described outer-layer circuit layer 3 surface and periphery are coated with photosensitive insulant 8, described photosensitive insulant 8 offers in the position in outer-layer circuit layer 3 front plants ball region 11, anti oxidation layer 10 it is provided with in ball placement region 11.
Described internal layer circuit layer 1 and tin layers 5 surface configuration have anti oxidation layer 10.
Its manufacture method is as follows:
Step one, take metal support plate
Seeing Fig. 1, take the suitable metal support plate of a piece of thickness, the material of metal support plate can convert with characteristic according to the function of chip, such as: copper material, iron material, ferronickel material or zinc-iron material etc.;
Step 2, metal support plate surface preplating copper material
Seeing Fig. 2, at one layer of copper material thin film of metal support plate electroplating surface, it is therefore an objective to make basis for follow-up plating, the mode of described plating can use chemical plating or electrolysis plating;
Step 3, patch photoresistance film
Seeing Fig. 3, stick the photoresistance film that can be exposed development in the metal support plate front and the back side completing preplating copper material thin film respectively, described photoresistance film can use wet type photoresistance film or dry type photoresistance film;
Step 4, development are windowed
Seeing Fig. 4, the metal support plate front utilizing exposure imaging equipment that step 3 completes to paste photoresistance film carries out graph exposure, develops and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to carry out internal layer circuit layer plating, metal support plate front;
Step 5, plating internal layer circuit layer
See Fig. 5, in step 4, electroplate metallic circuit layer as internal layer circuit layer in the region of metal support plate front removal part photoresistance film;
Step 6, removal photoresistance film
Seeing Fig. 6, remove the photoresistance film on metal support plate surface, minimizing technology uses chemical medicinal liquid to soften (if desired and use high pressure water jets to remove);
Step 7, patch photoresistance film
Seeing Fig. 7, the photoresistance film that can be exposed development is sticked at the front and the back side that complete the metal support plate of internal layer circuit layer plating in step 5 respectively;
Step 8, development are windowed
Seeing Fig. 8, the metal support plate front utilizing exposure imaging equipment that step 7 completes to paste photoresistance film carries out graph exposure, develops and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to be attached the plating of copper post, metal support plate front;
Step 9, plate bonding copper post
See Fig. 9, in step 8, electroplate metal level as connecting internal layer circuit layer and the copper post of outer-layer circuit layer in the region of metal support plate front removal part photoresistance film;
Step 10, removal photoresistance film
See Figure 10, remove the photoresistance film on metal support plate surface, remove the method for photoresistance film and use chemical medicinal liquid to soften (if desired and use high pressure water jets to remove);
Step 11, covering insulating material layer
See Figure 11, at metal support plate front one layer of insulant of covering in order to the insulating barrier done between internal layer circuit layer and outer-layer circuit layer, do basis for follow-up plating outer-layer circuit layer simultaneously;
Step 12, insulant surface are thinning
See Figure 12, insulant surface is carried out mechanical reduction, until exposing connection copper post.Purpose is to make connection copper post be connected with follow-up outer-layer circuit layer, can increase the adhesion of subsequent chemistry copper simultaneously;
Step 13, insulant surface metalation
See Figure 13, insulant surface is carried out metalized so that it is surface is follow-up can electroplate;
Step 14, patch photoresistance film
See Figure 14, complete metallized metal support plate front and the back side is sticked and can be exposed the photoresistance film of development;
Step 15, development are windowed
See Figure 15, utilize exposure imaging equipment metal support plate front to carry out graph exposure, develop and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to carry out outer-layer circuit layer plating, metal support plate front;
Step 10 six, plating outer-layer circuit layer
See Figure 16, in step 15, electroplate metallic circuit layer as outer-layer circuit layer in the region of metal support plate front removal part photoresistance film;
Step 10 seven, removal photoresistance film
See Figure 17, remove the photoresistance film on metal support plate surface, remove the method for photoresistance film and use chemical medicinal liquid to soften (if desired and use high pressure water jets to remove);
Step 10 eight, fast-etching
See Figure 18, metal support plate front is carried out fast-etching, remove the metal beyond outer-layer circuit layer;
Step 10 nine, coat photosensitive insulant
See Figure 19, complete the photosensitive insulant of metal support plate front surface coated of outer-layer circuit layer;
Step 2 ten, development are windowed
See Figure 20, utilize exposure imaging equipment metal support plate front to carry out graph exposure, develop and removes partial graphical photoresistance film, be processed the graphics field of (planting ball) exposing the follow-up needs in metal support plate front;
Step 2 11, removal metal support plate
Seeing Figure 21, remove metal support plate and form the wiring board exposing internal layer circuit layer, etching solution can use copper chloride or iron chloride;
Step 2 12, patch photoresistance film
Seeing Figure 22, the photoresistance film that can be exposed development is sticked at the wiring board front formed after removing metal support plate and the back side respectively;
Step 2 13, development are windowed
See Figure 23, utilize exposure imaging equipment the wiring board back side is carried out graph exposure, develop with remove partial graphical photoresistance film, with expose the follow-up needs in the wiring board back side carry out electroplate SMT copper post graphics field;
Step 2 14, plating SMT copper post
See Figure 24, in step 2 13, electroplate SMT copper post in the region of circuit back removal part photoresistance film, prepare for sequent surface attachment;
Step 2 15, electrotinning
See Figure 25, electrotinning on the SMT copper post that step 2 14 plating is formed, make place mat for sequent surface attachment;
Step 2 16, removal photoresistance film
See Figure 26, remove the photoresistance film of PCB surface;
Step 2 17, carry out the organic protection of metal
Seeing Figure 27, the metal level exposing wiring board front and back carries out organic protection;
Step 2 18, coating help wlding material
Seeing Figure 28, the tin plating region coating on circuit back SMT copper post helps wlding material;
Step 2 19, mount components Reflow Soldering
See Figure 29, help the SMT copper post element pasted on surface of wlding material in the coating of circuit back and carry out reflow soldering;
Step 3 ten, epoxy resin plastic packaging
See Figure 30, step 2 19 complete mount components and by Reflow Soldering realize be electrically connected with the wiring board back side carry out epoxy resin plastic packaging.

Claims (1)

1. the manufacture method of a SMT addition high-density packages multilayer circuit board structure, it is characterised in that described method comprises the following steps that:
Step one, take metal support plate
Step 2, metal support plate surface preplating copper material
At one layer of copper material thin film of metal support plate electroplating surface;
Step 3, patch photoresistance film
The photoresistance film that can be exposed development is sticked respectively in the metal support plate front and the back side completing preplating copper material thin film;
Step 4, development are windowed
The metal support plate front utilizing exposure imaging equipment that step 3 completes to paste photoresistance film carries out graph exposure, develops and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to carry out internal layer circuit layer plating, metal support plate front;
Step 5, plating internal layer circuit layer
Metallic circuit layer is electroplated as internal layer circuit layer in the region of metal support plate front removal part photoresistance film in step 4;
Step 6, removal photoresistance film
Remove the photoresistance film on metal support plate surface;
Step 7, patch photoresistance film
The photoresistance film that can be exposed development is sticked at the front and the back side that complete the metal support plate of internal layer circuit layer plating in step 5 respectively;
Step 8, development are windowed
The metal support plate front utilizing exposure imaging equipment that step 7 completes to paste photoresistance film carries out graph exposure, develops and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to be attached the plating of copper post, metal support plate front;
Step 9, plate bonding copper post
Metal level is electroplated as connecting internal layer circuit layer and the copper post of outer-layer circuit layer in the region of metal support plate front removal part photoresistance film in step 8;
Step 10, removal photoresistance film
Remove the photoresistance film on metal support plate surface;
Step 11, covering insulating material layer
One layer of insulant is covered in metal support plate front;
Step 12, insulant surface are thinning
Insulant surface is carried out mechanical reduction, until exposing connection copper post;
Step 13, insulant surface metalation
Insulant surface is carried out metalized so that it is surface is follow-up can electroplate;
Step 14, patch photoresistance film
Complete metallized metal support plate front and the back side is sticked and can be exposed the photoresistance film of development;
Step 15, development are windowed
Exposure imaging equipment is utilized metal support plate front to carry out graph exposure, develop and removes partial graphical photoresistance film, to expose the follow-up graphics field needing to carry out outer-layer circuit layer plating, metal support plate front;
Step 10 six, plating outer-layer circuit layer
Metallic circuit layer is electroplated as outer-layer circuit layer in the region of metal support plate front removal part photoresistance film in step 15;
Step 10 seven, removal photoresistance film
Remove the photoresistance film on metal support plate surface;
Step 10 eight, fast-etching
Metal support plate front is carried out fast-etching, removes the metal beyond outer-layer circuit layer;
Step 10 nine, coat photosensitive insulant
Complete the photosensitive insulant of metal support plate front surface coated of outer-layer circuit layer;
Step 2 ten, development are windowed
Exposure imaging equipment is utilized metal support plate front to carry out graph exposure, develop and removes partial graphical photoresistance film, to expose the graphics field that the follow-up needs in metal support plate front are processed;
Step 2 11, removal metal support plate
Remove metal support plate and form the wiring board exposing internal layer circuit layer;
Step 2 12, patch photoresistance film
The photoresistance film that can be exposed development is sticked at the wiring board front formed after removing metal support plate and the back side respectively;
Step 2 13, development are windowed
Utilize exposure imaging equipment the wiring board back side is carried out graph exposure, develop with remove partial graphical photoresistance film, with expose the follow-up needs in the wiring board back side carry out electroplate SMT copper post graphics field;
Step 2 14, plating SMT copper post
In step 2 13, electroplate SMT copper post in the region of circuit back removal part photoresistance film, prepare for sequent surface attachment;
Step 2 15, electrotinning
Electrotinning on the SMT copper post that step 2 14 plating is formed, makees place mat for sequent surface attachment;
Step 2 16, removal photoresistance film
Remove the photoresistance film of PCB surface;
Step 2 17, carry out the organic protection of metal
The metal level exposing wiring board front and back carries out organic protection;
Step 2 18, coating help wlding material
Tin plating region coating on circuit back SMT copper post helps wlding material;
Step 2 19, mount components Reflow Soldering
Help the SMT copper post element pasted on surface of wlding material in the coating of circuit back and carry out reflow soldering;
Step 3 ten, epoxy resin plastic packaging
Step 2 19 complete mount components and by Reflow Soldering realize be electrically connected with the wiring board back side carry out epoxy resin plastic packaging.
CN201310648040.2A 2013-12-04 2013-12-04 SMT addition high-density packages multilayer circuit board structure and preparation method thereof Active CN103596358B (en)

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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
CN103874347B (en) * 2014-03-28 2016-09-07 江阴芯智联电子科技有限公司 High-density multi-layered substrate surface symmetrical structure and preparation method
US10002839B2 (en) * 2016-08-29 2018-06-19 Via Alliance Semiconductor Co., Ltd. Electronic structure, and electronic structure array
CN106783794B (en) * 2017-03-16 2019-03-22 江阴芯智联电子科技有限公司 Pre-packaged no conducting wire electrodepositable lead-frame packages structure and its manufacturing method
CN113225937A (en) * 2021-05-19 2021-08-06 惠州市金百泽电路科技有限公司 Manufacturing method applied to high-density interconnection circuit board coreless board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1792126A (en) * 2003-05-19 2006-06-21 大日本印刷株式会社 Double-sided wiring board and manufacturing method of double-sided wiring board
TW200929388A (en) * 2007-12-26 2009-07-01 Stats Chippac Ltd Semiconductor device and method of forming the device using sacrificial carrier
CN203608451U (en) * 2013-12-04 2014-05-21 江苏长电科技股份有限公司 SMT addition high-density packaged multilayer circuit board structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7738257B2 (en) * 2006-12-13 2010-06-15 Intel Corporation Microelectronic device including bridging interconnect to top conductive layer of passive embedded structure and method of making same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1792126A (en) * 2003-05-19 2006-06-21 大日本印刷株式会社 Double-sided wiring board and manufacturing method of double-sided wiring board
TW200929388A (en) * 2007-12-26 2009-07-01 Stats Chippac Ltd Semiconductor device and method of forming the device using sacrificial carrier
CN203608451U (en) * 2013-12-04 2014-05-21 江苏长电科技股份有限公司 SMT addition high-density packaged multilayer circuit board structure

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