CN103594518B - Metal source-drain structure and forming method thereof - Google Patents

Metal source-drain structure and forming method thereof Download PDF

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CN103594518B
CN103594518B CN201310553688.1A CN201310553688A CN103594518B CN 103594518 B CN103594518 B CN 103594518B CN 201310553688 A CN201310553688 A CN 201310553688A CN 103594518 B CN103594518 B CN 103594518B
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layer
gesn
drain structure
metal source
substrate
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CN103594518A (en
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赵梅
刘磊
王敬
梁仁荣
许军
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Tsinghua University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention proposes a kind of metal source-drain structure and forming method thereof, and wherein, the method comprises the following steps: provide the substrate with Ge layer as surface;Forming Sn layer on Ge layer, wherein, the interface between Ge layer and Sn layer is GeSn layer;Remove Sn layer to expose GeSn layer;Metal level is formed on GeSn layer.The present invention can improve the switch current ratio of device and the electronic barrier height of schottky device, has simple, the advantage of low cost.

Description

Metal source-drain structure and forming method thereof
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of metal source-drain structure and forming method thereof.
Background technology
Quasiconductor Ge has higher electronics and hole mobility, brilliant in novel high-performance Metal-oxide-semicondutor field effect The device channel material aspect of body pipe (MOSFET) has a high potential.For the MOSFET element under small size, suppressor The short-channel effect of part is a very important problem, typically requires that the source and drain pn-junction junction depth of device should be with device size Scaled, to weaken the two dimensional effects of Potential Distributing in raceway groove, strengthen the grid control ability to groove potential to suppress short Channelling effect.Therefore, for the MOSFET element of very small dimensions, super-shallow source-drain pn-junction realizes good device performance Crucial.Meanwhile, the dead resistance of source-drain area also becomes brighter to the impact of device ON state current with device dimensions shrink Aobvious, also to make its dead resistance reduce while realizing super-shallow source-drain pn-junction and just become the most important.
For Ge base MOSFET, higher carrier mobility can realize more more preferable device than traditional Si sill Performance.But general impurity solid solubility in Ge is relatively low and is susceptible to diffusion, thus is not easily formed high-dopant concentration Source-drain area and the shallower source and drain pn-junction of junction depth so that the device source drain parasitic resistance of formation is relatively big and is unfavorable for suppression device Short-channel effect.Metal source-drain structure based on schottky junction can be used to solve this problem.With traditional source and drain pn-junction class Seemingly, the schottky junction that metal and semi-conducting material can be formed as the source-drain structure of MOSFET to realize low dead resistance Shallow junction structures.For being not easily formed the Ge material of preferable source and drain pn-junction, schottky junction source-drain structure can be as one Ideal solution.
People typically use the metals such as Pt, Ni to form alloy with Ge, are constituted schottky junction as MOSFET device using this with Ge The source-drain structure of part, it is to avoid traditional pn-junction spreads, because of impurity, the problem brought.But, generally have in these processing methods There is higher hot expense, and when removing sacrificial metal layer often with strong acid treatment etc., for Ge base device, wherein High-k dielectric and metal gate constitute rhythmic structure of the fence typically can not bear such high temperature or strong acid treatment, these process can The deterioration of MOSFET element rhythmic structure of the fence electric property can be caused.Additionally, the current-carrying of the Ge based Schottky obtained at present Sub-schottky barrier height is not the most especially desirable, and the switch current ratio of schottky junction is not the highest, thus is applied to Higher off-state current and bigger ghost effect can be caused time in MOSFET element, and then Ge MOSFET element can be affected Switch current ratio.
Summary of the invention
It is contemplated that solve one of above-mentioned technical problem the most to a certain extent or provide at a kind of useful choice of technology.
To this end, it is an object of the present invention to propose the metal source-drain structure forming method that a kind of thickness is thin and electrical properties is good.
Further object is that and propose the metal source-drain structure that a kind of thickness is thin and electrical properties is good.
The metal source-drain structure forming method of embodiment according to a first aspect of the present invention, may comprise steps of: provide with Ge Layer is the substrate on surface;Sn layer, wherein, the interface between described Ge layer and described Sn layer is formed on described Ge layer For GeSn layer;Remove described Sn layer to expose described GeSn layer;Metal level is formed on described GeSn layer.
Metal source-drain structure forming method according to embodiments of the present invention, it is possible to increase the switch current ratio of device and schottky device Electronic barrier height, there is the advantage that technique is simple, simple and easy to do.
It addition, metal source-drain structure forming method according to embodiments of the present invention can also have a following additional technical feature:
In one embodiment of the invention, farther included before removing described Sn layer: described by annealing strengthening GeSn layer.
In one embodiment of the invention, the described substrate with Ge layer as surface includes: pure Ge substrate or top layer are that Ge is thin The substrate of film.
In one embodiment of the invention, the thickness of described metal level is 200-500nm.
In one embodiment of the invention, during described metal level is Al, Ni, Co, W, Pt, Ti, Ta, Pd, Zr The combination of one or more metals.
In one embodiment of the invention, the solution to GeSn and Sn with high corrosion selection ratio is utilized to clean to remove institute State Sn layer to expose described GeSn layer.
In one embodiment of the invention, the thickness of the described GeSn layer remained after described cleaning is 0.5-3nm.
The metal source-drain structure of embodiment according to a second aspect of the present invention, may include that the substrate with Ge layer as surface;It is positioned at GeSn layer on described Ge layer;It is positioned at the metal level on described GeSn layer.
Metal source-drain structure according to embodiments of the present invention, it is possible to increase the switch current ratio of device and the electronics gesture of schottky device Build height.Additionally, the metal source-drain structure of the embodiment of the present invention also has simple in construction, lower-cost advantage.
It addition, metal source-drain structure according to embodiments of the present invention can also have a following additional technical feature:
In one embodiment of the invention, described GeSn layer is first to form Sn layer on described Ge layer, then described Interface self-assembling formation between Ge layer and described Sn layer or obtained by annealing strengthening.
In one embodiment of the invention, the described substrate with Ge layer as surface includes: pure Ge substrate or top layer are that Ge is thin The substrate of film.
In one embodiment of the invention, the thickness of described metal level is 200-500nm.
In one embodiment of the invention, during described metal level is Al, Ni, Co, W, Pt, Ti, Ta, Pd, Zr The combination of one or more metals.
In one embodiment of the invention, the surface part of described GeSn layer is to utilize to have high corrosion choosing to GeSn and Sn Select than solution clean to come out after removing the described Sn layer on described GeSn.
In one embodiment of the invention, the thickness of the described GeSn layer remained after described cleaning is 0.5-3nm.
The additional aspect of the present invention and advantage will part be given in the following description, and part will become bright from the following description Aobvious, or recognized by the practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage the accompanying drawings below description to embodiment will be apparent from from combining and Easy to understand, wherein:
Fig. 1 is the flow chart of the forming method of the metal source-drain structure of the embodiment of the present invention;
Fig. 2 is the structural representation of the metal source-drain structure of the embodiment of the present invention;
Fig. 3 is the XRD test result in Ge/GeSn structure (004) face;With
Fig. 4 is the schottky junction Jg-Vg characteristic curve of Ge/GeSn/Al structure.
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, the most identical or Similar label represents same or similar element or has the element of same or like function.Describe below with reference to accompanying drawing Embodiment is exemplary, it is intended to is used for explaining the present invention, and is not considered as limiting the invention.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or D score permissible Directly contact including the first and second features, it is also possible to include that the first and second features are not directly contact but by them Between other characterisation contact.And, fisrt feature second feature " on ", " top " and " above " include first Feature is directly over second feature and oblique upper, or is merely representative of fisrt feature level height higher than second feature.First is special Levy second feature " under ", " lower section " and " below " include fisrt feature immediately below second feature and obliquely downward, or only Only represent that fisrt feature level height is less than second feature.
As it is shown in figure 1, the forming method of metal source-drain structure according to embodiments of the present invention, may include steps of:
S1., substrate with Ge layer as surface is provided.
Specifically, it is provided that the substrate that the substrate with Ge layer as surface can be pure Ge substrate or top layer is Ge thin film, such as Si matrix has the substrate on Ge thin film top layer.
S2. forming Sn layer on Ge layer, wherein, the interface between Ge layer and Sn layer is GeSn layer.
The technique such as magnetron sputtering, electron beam evaporation generally can be used to form Sn layer on Ge layer.In these techniques, lining End temperature control is between room temperature to 200 DEG C.In technical process, due to atom diffusion between bi-material interface, At Ge/Sn interface self-assembling formation GeSn layer.In a preferred embodiment of the invention, it is also possible to come strong by annealing Change this GeSn layer.The temperature range of annealing is 50-200 DEG C, and the temperature the highest time is the longest, then the GeSn layer formed is the thickest.
The GeSn layer diffuseed to form is a kind of solid solution, has the crystal structure identical with Ge, and it is special to have fine quasiconductor Property, as GeSn has more higher hole mobility than Ge.Therefore, Ge surface forms GeSn layer and generally will not deteriorate Ge The performance of device.
S3. Sn layer is removed to expose GeSn layer.
Specifically, the solution to GeSn and Sn with high corrosion selection ratio is utilized to clean to remove Sn layer to expose GeSn layer. Common cleaning solution includes dilute hydrochloric acid, dilute sulfuric acid, ammonia or sodium hydroxide solution.The GeSn layer remained after cleaning Thickness is 0.5-40nm, it is preferable that GeSn layer thickness is 0.5-10nm.
S4. on GeSn layer, form metal level.
Specifically, available on GeSn layer, 200-500nm thickness is formed by the mode such as magnetron sputtering, electron beam evaporation The combination of one or more metals in Al, Ni, Co, W, Pt, Ti, Ta, Pd, Zr.Preferably, the thickness of metal level For 300nm.
Metal source-drain structure forming method according to embodiments of the present invention, first sputters Sn metal level on Ge surface, then with dilute The wet processings such as hydrochloric acid are removed upper strata Sn layer and are obtained GeSn layer, then form metal level on GeSn layer such that it is able to carry The switch current ratio of high device and the electronic barrier height of schottky device.Additionally, this method also has, technique is simple, simplicity is easy The advantage of row.
As in figure 2 it is shown, metal source-drain structure according to embodiments of the present invention, may include that the lining with Ge layer 100 as surface The end;It is positioned at the GeSn layer 200 on Ge layer 100;It is positioned at the metal level 300 on GeSn layer 200.
Wherein, the substrate with Ge layer 100 as surface can be pure Ge substrate, it is also possible to be top layer be the substrate of Ge thin film, Such as there is on Si matrix the substrate on Ge thin film top layer.
Wherein, GeSn layer 200 is finally to be sacrificed by formation this Sn layer 110 of Sn layer 110(on Ge layer 100, Therefore Fig. 2 does not shows), then interface self-assembling formation between Ge layer 100 and Sn layer 110 or by annealing Strengthening obtains.The temperature range of annealing can be 50-200 DEG C, and the temperature the highest time is the longest, then the GeSn layer 200 formed is more Thick.Because the GeSn layer diffuseed to form is a kind of solid solution, there is the crystal structure identical with Ge, and have and partly lead very well Bulk properties, as GeSn has more higher hole mobility than Ge, so, the GeSn layer that Ge surface is formed is the most not The performance of Ge device can be deteriorated, it is also possible to device performance can be improved.
Wherein, metal level 300 can be one or more metals in Al, Ni, Co, W, Pt, Ti, Ta, Pd, Zr Combination.Metal level 300 is obtained by the mode such as magnetron sputtering, electron beam evaporation on GeSn layer 200, thickness For 200-500nm, preferably 300nm.
Metal source-drain structure according to embodiments of the present invention, it is possible to increase the switch current ratio of device and the electronics gesture of schottky device Build height.Additionally, the metal source-drain structure of the embodiment of the present invention also has simple in construction, lower-cost advantage.
In order to make those skilled in the art be more fully understood that, the present invention, inventor combine Fig. 3-Fig. 4 and illustrate that a specific embodiment is as follows:
In the following embodiments, realize the schottky junction of Ge by introducing GeSn layer, Ge substrate sputters Sn Form GeSn layer, can use the modes such as annealing to strengthen GeSn layer, then remove top Sn layer with dilute HCl, finally at GeSn Layer surface evaporation forms Al electrode and constitutes schottky junction using the metal source-drain structure as MOSFET element.It was found that There is the schottky junction switch current ratio of GeSn layer up to 7 × 104, electronics schottky barrier height is up to 0.62eV.Specifically Ground:
First, sputtering one layer of thicker Sn layer above N-shaped germanium wafer after cleaning, re-annealing processes and is formed in interface GeSn layer, finally uses the dilute hydrochloric acid of 10% to clean and removes surface unreacted Sn layer, more directly on Ge/GeSn surface Evaporation forms the Al electrode that 300nm is thick, and whole stacked structure is carried out photoetching, etching is applied to source metal to be formed The schottky junction of leakage.The sign of this schottky junction is specifically included that A. high-resolution X-ray diffractometer (XRD) point The elemental composition of analysis material and crystallization situation.B. the electricity of this schottky junction is measured with Agilent B1500A semiconductor device analyser Current density-voltage (Jg-Vg) characteristic curve, analyzes its electrology characteristic.
Fig. 3 gives the XRD figure spectrum of sample surfaces, is 66.5 ° at Bragg diffraction angle as we can clearly see from the figure Ge peak near occur in that a small peak, its peak position is 64.6 °, it may be determined that it is GeSn peak.
Fig. 4 by under room temperature to the Ge/GeSn/Al schottky junction formed and as comparison Ge/Al schottky junction electricity The test result of current density-voltage characteristic.It can be seen that without the Ge/Al structure Schottky device in GeSn intermediate layer The switch current ratio of part is 150, and Ge/GeSn/Al its switch current ratio of structure Schottky device adding GeSn layer can Reach 7 × 104.The reverse current of particularly Ge/GeSn/Al structure reduces nearly 2 orders of magnitude.According to thermionic emission Theory, it is 0.62eV that Test extraction obtains the electronic barrier height of Ge/GeSn/Al schottky junction, it is contemplated that germanium material Energy gap is 0.66eV, then can obtain hole barrier height and be about 0.04eV.By introducing GeSn layer so that Xiao Te Base junction reverse saturation current substantially diminishes, and conducting electric current can be made to increase during as the metal source-drain structure of PMOS.
Generally speaking, the present invention realizes the schottky junction of Ge by introducing GeSn layer, is particularly suitable as Ge base The metal source-drain structure of MOSFET element.The preparation method of the schottky junction wherein with GeSn layer is: on Ge One layer of Sn layer of face sputtering, can make annealing treatment and strengthen the GeSn layer formed in interface, uses dilute hydrochloric acid to clean and removes surface Sn layer, then Ge/GeSn table surface forming electrode constitute Schottky contacts.This be used for metal source and drain schottky junction its Electronics schottky barrier height is up to 0.62eV, and switch current ratio is 7 × 104.There is the Ge schottky junction of GeSn layer It is highly suitable for the metal source-drain structure of Ge base MOSFET.
In flow chart or at this, any process described otherwise above or method description are construed as, and represent and include one The module of code, fragment or the portion of the executable instruction of the individual or more step for realizing specific logical function or process Divide, and the scope of the preferred embodiment of the present invention includes other realization, wherein can not be by shown or discussion Sequentially, including according to involved function by basic mode simultaneously or in the opposite order, performing function, this should be by Embodiments of the invention person of ordinary skill in the field understood.
In the description of this specification, reference term " embodiment ", " some embodiments ", " example ", " concrete example ", Or specific features, structure, material or the feature that the description of " some examples " etc. means to combine this embodiment or example describes comprises In at least one embodiment or example of the present invention.In this manual, the schematic representation to above-mentioned term not necessarily refers to It is identical embodiment or example.And, the specific features of description, structure, material or feature can at any one or Multiple embodiments or example combine in an appropriate manner.
Although above it has been shown and described that embodiments of the invention, it is to be understood that above-described embodiment is exemplary, Being not considered as limiting the invention, those of ordinary skill in the art is in the case of without departing from the principle of the present invention and objective Above-described embodiment can be changed within the scope of the invention, revise, replace and modification.

Claims (13)

1. a metal source-drain structure forming method, it is characterised in that comprise the following steps:
Substrate with Ge layer as surface is provided;
Forming Sn layer on described Ge layer, wherein, the interface between described Ge layer and described Sn layer is GeSn layer;
Remove described Sn layer to expose described GeSn layer;
Metal level is formed on described GeSn layer.
2. metal source-drain structure forming method as claimed in claim 1, it is characterised in that before removing described Sn layer Farther include: strengthen described GeSn layer by annealing.
3. metal source-drain structure forming method as claimed in claim 1, it is characterised in that described with Ge layer as surface Substrate includes: pure Ge substrate or the substrate that top layer is Ge thin film.
4. metal source-drain structure forming method as claimed in claim 1, it is characterised in that the thickness of described metal level is 200-500nm。
5. metal source-drain structure forming method as claimed in claim 1, it is characterised in that described metal level is Al, Ni, The combination of one or more metals in Co, W, Pt, Ti, Ta, Pd, Zr.
6. the metal source-drain structure forming method as described in claim 1-5 is arbitrary, it is characterised in that utilize GeSn and Sn has high corrosion and selects the solution of ratio to clean to remove described Sn layer to expose described GeSn layer.
7. metal source-drain structure forming method as claimed in claim 6, it is characterised in that remain after described cleaning The thickness of described GeSn layer is 0.5-3nm.
8. a metal source-drain structure, it is characterised in that including:
Substrate with Ge layer as surface;
It is positioned at the GeSn layer on described Ge layer;
It is positioned at the metal level on described GeSn layer;
Wherein, described GeSn layer is first to form Sn layer on described Ge layer, then at described Ge layer and described Sn layer Between interface self-assembling formation or obtained by annealing strengthening.
9. metal source-drain structure as claimed in claim 8, it is characterised in that the described substrate with Ge layer as surface includes: Pure Ge substrate or the substrate that top layer is Ge thin film.
10. metal source-drain structure as claimed in claim 8, it is characterised in that the thickness of described metal level is 200-500nm.
11. metal source-drain structure as claimed in claim 8, it is characterised in that described metal level is Al, Ni, Co, W, The combination of one or more metals in Pt, Ti, Ta, Pd, Zr.
12. metal source-drain structure as described in claim 9-11 is arbitrary, it is characterised in that the skin section of described GeSn layer After dividing the solution cleaning being to utilize and have high corrosion selection ratio to GeSn and Sn to remove the described Sn layer on described GeSn Come out.
13. metal source-drain structure as claimed in claim 12, it is characterised in that the described GeSn remained after described cleaning The thickness of layer is 0.5-3nm.
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CN103839980B (en) * 2014-02-25 2017-01-18 清华大学 MOSFET with SiGeSn source drain and forming method thereof
CN103839829A (en) * 2014-02-25 2014-06-04 清华大学 Fin type field effect transistor with SiGeSn channel and forming method thereof
WO2015127697A1 (en) * 2014-02-25 2015-09-03 Tsinghua University Method for forming fin field effect transistor
WO2015127702A1 (en) * 2014-02-25 2015-09-03 Tsinghua University Method for forming germanium-based layer
CN103839832A (en) * 2014-02-25 2014-06-04 清华大学 Fin type field effect transistor with GeSn source drain and forming method thereof
CN103811304A (en) * 2014-02-25 2014-05-21 清华大学 GeSn layer and forming method thereof
CN103839775A (en) * 2014-02-25 2014-06-04 清华大学 GeSn layer of selected area and method for forming GeSn layer of selected area
CN106783566A (en) * 2016-11-29 2017-05-31 东莞市广信知识产权服务有限公司 A kind of N-type Ohm contact production method of Ge

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CN101866953B (en) * 2010-05-26 2012-08-22 清华大学 Low Schottky barrier semiconductor structure and formation method thereof
CN102136428B (en) * 2011-01-25 2012-07-25 北京大学 Preparation method of germanium-based Schottky N-type field effect transistor
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