CN103839832A - Fin type field effect transistor with GeSn source drain and forming method thereof - Google Patents
Fin type field effect transistor with GeSn source drain and forming method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention provides a fin type field effect transistor with GeSn source drain and a forming method thereof. The forming method comprises the following steps of providing a substrate, forming a fin-shaped Ge structure on the substrate, forming a gate stack or a pseudo gate on the fin-shaped Ge structure, forming an opening of a source area and an opening of a drain area in the two sides of the gate stack or the pseudo gate, exposing the fin-shaped Ge structure from the positions of the openings, and injecting atoms or molecules or ions or plasma containing a Sn element into the fin-shaped Ge structure so that a GeSn layer can be formed at the positions of the openings. According to the forming method of the fin type field effect transistor, a FinFET with the GeSn source drain can be formed; the thickness of the GeSn source drain is small, the crystalline quality is good, and therefore the transistor has the good electrical property; the method has the advantages of being simple and easy to implement and low in cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to fin formula field effect transistor leaking in a kind of GeSn of having source and forming method thereof.
Background technology
Metal-oxide semiconductor fieldeffect transistor (MOSFET) is for integrated circuit industry served for four more than ten years.People have invented various ingenious technology constantly dwindles its characteristic size, but does not change its basic structure.But integrated circuit (IC) design window, comprises performance, dynamic power consumption, quiescent dissipation and device tolerance, has narrowed down to the stage of having to invent a kind of new transistor arrangement.Along with long constantly the dwindling of grid, the transfer characteristic (I of MOSFET
ds-V
gs) degenerate, be mainly manifested in two aspects.The one, sub-threshold slope becomes large and threshold voltage reduction, that is to say, by reducing gate electrode voltage V
gscan not make MOS device turn-off finely.On the other hand, sub-threshold slope and threshold voltage are all responsive especially to the long variation of grid, that is to say, the process allowance of MOS device becomes non-constant, and this phenomenon is called as short-channel effect.
In order effectively to suppress short-channel effect, researcher has proposed a kind of device architecture on the one hand, and this device architecture makes semiconductor channel only exist only in the very place near grid, can eliminate all leak channels away from grid.Because now this semiconductor channel is sufficiently thin, its shape looks like the fin (Fin) of a fish, thereby researcher is called fin formula field effect transistor (FinFET) visually.FinFET device can significantly strengthen the control ability of grid to raceway groove, has effectively suppressed short-channel effect, make it have that drive current is large, off-state current is little, devices switch than high, cost is low, transistor density advantages of higher.The material of Fin can adopt cheap body Si substrate or silicon-on-insulator substrate (SOI) to process.
On the other hand, along with constantly dwindling of device size, the mobility that Si material is lower has become the principal element of restriction device performance.For the performance of continuous boost device, must adopt the more channel material of high mobility.The main technical schemes of research is at present: adopt Ge or SiGe material to do the channel material of PMOSFET device, III-V compound semiconductor materials is the channel material of NMOSFET device.Ge has the hole mobility that is four times in Si, and along with deepening continuously of research, the technological difficulties in Ge and SiGe channel mosfet are captured one by one.In the MOSFET of Ge or SiGe device, in order to introduce single shaft compressive strain in Ge or SiGe raceway groove, can fill strain Ge at source and drain areas
1-xsn
x(GeSn) alloy, the strain GeSn leaking by source like this can introduce single shaft compressive strain in raceway groove, significantly promotes the performance of Ge or SiGe raceway groove, and when channel length is during at nanoscale, its performance boost is particularly evident.With Ge mutually compatible GeSn alloy be a kind of IV family semi-conducting material, and there is good compatibility with complementary metal oxide semiconductors (CMOS) (CMOS) technique of silicon.But the GeSn alloy of the high Sn content of direct growth high-quality is very difficult.First, the equilirbium solid solubility of Sn in Ge is less than 1%(and is about 0.3%); Secondly, the surface of Sn can be less than Ge, is very easy to occur fractional condensation on surface; Again, Ge and α-Sn have very large lattice mismatch (14.7%).
In the time of growth GeSn material, the method conventionally adopting is molecular beam epitaxy (MBE).Wherein, the process of existing MBE technique growth GeSn material is: insert Sn solid metal as Sn source material in the Sn solid source stove of vacuum chamber; Substrate is inserted on the heater of vacuum chamber of molecular beam epitaxy source stove, vacuum chamber is vacuumized, substrate is heated; To the heating of Sn solid metal, make the fusing of Sn solid metal, evaporation produces the atom of Sn, opens baffle plate, makes Sn atom arrive substrate surface; In the vacuum chamber of molecular beam epitaxy source stove, pass into the chemical compound gas that contains Ge, make Ge atomic deposition to substrate surface, complete the epitaxial growth of GeSn alloy.The method can obtain the good GeSn film of crystal mass, but apparatus expensive, growth course is comparatively time-consuming, and cost is higher, in large-scale production, will be subject to certain limitation.Also someone adopts chemical vapor deposition (CVD) technique growth GeSn film, but the GeSn film quality making is poor, and thermal stability is not good, and the easy fractional condensation of Sn, is not suitable for semiconductor device yet.And, in FinFET structure, the method that generally need to adopt constituency to form forms GeSn at source-drain area, can adopt in theory chemical vapor deposition to carry out selective growth GeSn film, and the thermal stability of the method in the time of non-selective growth GeSn alloy is not good at present, the easy fractional condensation of Sn, its selective growth technique is still immature, and cost is also higher.
Summary of the invention
The present invention is intended to solve at least to a certain extent above-mentioned FinFET source and is difficult to form the measured GeSn film of matter, problem that production cost is high in leaking.For this reason, the object of the invention is to propose a kind of simple and cost is low has fin formula field effect transistor leaking in GeSn source and forming method thereof.
For achieving the above object, can comprise the following steps according to the formation method with the fin formula field effect transistor leaking in GeSn source of the embodiment of the present invention: substrate is provided; On described substrate, form Ge fin structure; On described Ge fin structure, form the stacking or false grid of grid; At the opening in formation source region, the stacking or false grid of described grid both sides and drain region, expose described Ge fin structure at described aperture position; Inject the atom, molecule, ion or the plasma that contain Sn element to described Ge fin structure, to form GeSn layer at described aperture position.
Can form and have the FinFET that leak in GeSn source according to the method for the embodiment of the present invention, thinner thickness, the crystal mass that leak in its GeSn source are better, and therefore transistor has good electric property, and this method have advantages of simple, cost is low.
Alternatively, also there is following technical characterictic according to the formation method with the fin formula field effect transistor leaking in GeSn source of the embodiment of the present invention:
In an example of the present invention, also comprise: before forming the opening in described source region and drain region, form grid side wall in the stacking or false grid of described grid both sides.
In an example of the present invention, also comprise: after forming described GeSn layer, remove described false grid, form grid in described false gate region stacking.
In an example of the present invention, described substrate is Si substrate, ge-on-insulator substrate on Si substrate, Ge substrate, insulator, have the Si substrate on Ge surface.
In an example of the present invention, on described substrate, form described Ge fin structure by selective epitaxial process.
In an example of the present invention, on described substrate, form described Ge fin structure by photoetching and etching technics, wherein, described underlayer surface is Ge material.
In an example of the present invention, described top layer is that the substrate of Ge material is Ge substrate, ge-on-insulator substrate, or has the Si substrate on Ge surface.
In an example of the present invention, the method for described injection comprises Implantation.
In an example of the present invention, described Implantation comprises that plasma source Implantation and plasma immersion ion inject.
In an example of the present invention, the method for described injection comprises magnetron sputtering.
In an example of the present invention, the process that adopts described magnetron sputtering to inject loads back bias voltage on described substrate.
In an example of the present invention, also comprise, remove the Sn film that described magnetron sputtering forms on described GeSn layer.
In an example of the present invention, utilize GeSn and Sn are had to high corrosion to select the solution of ratio to clean to remove described Sn film.
In an example of the present invention, the process of described injection heats described substrate, and heating-up temperature is 100-600 ℃.
In an example of the present invention, also comprise, after described injection, to described GeSn layer annealing, annealing temperature is 100-600 ℃.
In an example of the present invention, described GeSn layer is strain GeSn layer.
In an example of the present invention, the thickness of described strain GeSn layer is 0.5-100nm.
In an example of the present invention, in described strain GeSn layer, the atomic percentage conc of Sn is less than 20%.
For achieving the above object, according to the fin formula field effect transistor that leak in GeSn source that has of the embodiment of the present invention, comprising: substrate; Be formed on the Ge fin-shaped channel district on substrate; Be formed on the grid stacked structure on described Ge fin-shaped channel district; And be formed on GeSn source and the leakage of both sides, described Ge fin-shaped channel district.
According to the fin formula field effect transistor that leak in GeSn source that has of the embodiment of the present invention, have advantages of that electric property is good.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is the flow chart of the formation method with the fin formula field effect transistor leaking in GeSn source of first embodiment of the invention;
Fig. 2 to Fig. 5 b is the detailed process schematic diagram of the formation method shown in Fig. 1;
Fig. 6 is the flow chart of the formation method with the fin formula field effect transistor leaking in GeSn source of second embodiment of the invention;
Fig. 7 to Figure 11 b is the detailed process schematic diagram of the formation method shown in Fig. 6.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic it " on " or D score can comprise that the first and second features directly contact, also can comprise that the first and second features are not directly contacts but by the other feature contact between them.And, First Characteristic Second Characteristic " on ", " top " and " above " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " comprise First Characteristic under Second Characteristic and tiltedly, or only represent that First Characteristic level height is less than Second Characteristic.
Can adopt first grid technique according to the formation method with the fin formula field effect transistor leaking in GeSn source of first embodiment of the invention, as shown in Figure 1, can comprise the steps:
S11., substrate is provided.
Particularly, this substrate can be Si substrate, ge-on-insulator substrate on Si substrate, Ge substrate, insulator, have the Si substrate on Ge surface etc.
S12. on substrate, form Ge fin structure.
Particularly, on substrate 00, form Ge fin structure 10, with reference to figure 2.
In one embodiment of the invention, can on substrate 00, form by selective epitaxial process Ge fin structure 10.At this moment, Ge fin structure 10 not substrate 00 originally had, but rear extension out, and therefore the range of choice of substrate 00 is wider, can be for Si substrate, ge-on-insulator substrate on Si substrate, Ge substrate, insulator, have the Si substrate on Ge surface etc.
In another embodiment of the present invention, can on substrate 00, form Ge fin structure 10 by photoetching and etching technics, wherein, substrate 00 is that top layer is the substrate of Ge material.At this moment, Ge fin structure 10 is that substrate 00 originally had, but not rear formation, therefore the range of choice of substrate 00 is narrower, can be Ge substrate, ge-on-insulator substrate, or has the Si substrate on Ge surface etc.
S13. on Ge fin structure, form grid stacking.
Particularly, on Ge fin structure 10, deposit successively gate dielectric material and grid material, form patterned, to comprise gate dielectric layer 20a and grid layer 20b grid stacking 20 by photoetching and etching technics.With reference to figure 3a and Fig. 3 b, wherein Fig. 3 a is schematic perspective view, and Fig. 3 b is the profile along channel direction.
S14. at the opening in grid formation source region, stacking both sides and drain region, expose Ge fin structure at aperture position.
Preferably, can further form grid side wall 30 in stacking 20 both sides of grid, to limit the opening in source region and drain region.This grid side wall 30 can play the effect that reduces element leakage.Detailed process is: after above-mentioned steps, first deposit the required dielectric material of grid side wall, then by suitable dry etch process, form grid side wall 30 in the stacking both sides of patterned grid, above source region and drain region, form opening, expose Ge fin structure 10 at aperture position simultaneously.With reference to figure 4a and Fig. 4 b, wherein Fig. 4 a is schematic perspective view, and Fig. 4 b is the profile along channel direction.
S15. inject to Ge fin structure the atom, molecule, ion or the plasma that contain Sn element, to form GeSn layer at aperture position.
Particularly, can inject the atom, molecule, ion or the plasma that contain Sn element to Ge fin structure 10, the top layer of the Ge fin structure 10 that aperture position is exposed or all change target GeSn layer 40 into.This GeSn layer 40 is used as the source leakage of FinFET.With reference to figure 5a and Fig. 5 b, wherein Fig. 5 a is schematic perspective view, and Fig. 5 b is the profile along channel direction.
According to the formation method of the FinFET of first embodiment of the invention, can obtain the fin-shaped field effect transistor of GeSn source-drain area, and the GeSn layer thickness of source-drain area is thinner, quality is better, and the method have advantages of simple, cost is low.
Can adopt rear grid technique according to the formation method with the fin formula field effect transistor leaking in GeSn source of second embodiment of the invention, as shown in Figure 6, can comprise the steps:
S21., substrate is provided.
Particularly, this substrate can be Si substrate, ge-on-insulator substrate on Si substrate, Ge substrate, insulator, have the Si substrate on Ge surface etc.
S22. on substrate, form Ge fin structure.
Particularly, on substrate 00, form Ge fin structure 10, with reference to figure 7.
In one embodiment of the invention, can on substrate 00, form by selective epitaxial process Ge fin structure 10.At this moment, Ge fin structure 10 not substrate 00 originally had, but rear extension out, and therefore the range of choice of substrate 00 is wider, can be for Si substrate, ge-on-insulator substrate on Si substrate, Ge substrate, insulator, have the Si substrate on Ge surface etc.
In another embodiment of the present invention, can on substrate 00, form Ge fin structure 10 by photoetching and etching technics, wherein, substrate 00 is that top layer is the substrate of Ge material.At this moment, Ge fin structure 10 is that substrate 00 originally had, but not rear formation, therefore the range of choice of substrate 00 is narrower, can be Ge substrate, ge-on-insulator substrate, or has the Si substrate on Ge surface etc.
S23. on Ge fin structure, form false grid.
Particularly, on the stacking region of the default grid of Ge fin structure 10, form false grid 50.With reference to figure 8a and Fig. 8 b, wherein Fig. 8 a is schematic perspective view, and Fig. 8 b is the profile along channel direction.
S24. at the opening in formation source region, false grid both sides and drain region, expose Ge fin structure at aperture position.
Particularly, further form grid side wall 30 in false grid 50 both sides, to limit the opening in source region and drain region.This grid side wall 30 can play the effect that reduces element leakage.Detailed process is: after above-mentioned steps, first deposit the required dielectric material of grid side wall, general employing and the different dielectric material of false grid material, then by suitable dry etch process, form grid side wall 30 in patterned false grid 50 both sides, above source region and drain region, form opening, and expose Ge fin structure 10 at aperture position simultaneously.With reference to figure 9a and Fig. 9 b, wherein Fig. 9 a is schematic perspective view, and Fig. 9 b is the profile along channel direction.
S25. inject to Ge fin structure the atom, molecule, ion or the plasma that contain Sn element, to form GeSn layer at aperture position.
Particularly, can inject the atom, molecule, ion or the plasma that contain Sn element to Ge fin structure 10, the top layer of the Ge fin structure 10 that aperture position is exposed or all change target GeSn layer 40 into.This GeSn layer 40 is used as the source leakage of FinFET.With reference to figure 10a and Figure 10 b, wherein Figure 10 a is schematic perspective view, and Figure 10 b is the profile along channel direction.
S26. remove false grid, form grid in false gate region stacking.
Particularly, can combine and remove false grid 50 by wet-chemical etching or dry etching and wet-chemical etching, and deposit successively gate dielectric material and grid material, and then by photoetching and etching technics, patterned to form, to comprise gate dielectric layer 20a and grid layer 20b grid stacking 20.So far, formed the FinFET with GeSn source-drain area.With reference to figure 11a and Figure 11 b, wherein Figure 11 a is schematic perspective view, and Figure 11 b is the profile along channel direction.
According to the formation method of the FinFET of second embodiment of the invention, can obtain equally the fin-shaped field effect transistor that GeSn is source-drain area, and the GeSn layer thickness of source-drain area is thinner, quality is better, and the method have advantages of simple, cost is low.
According to the present invention in the formation method of the FinFET of above-mentioned two embodiment, by utilizing injection technology to carry out surface modification to original Ge layer.The atom, molecule, ion or the plasma that are about to contain Sn element are injected in original Ge layer, by controlling suitable temperature and implantation dosage, make the not obvious diffusion of Sn element of injecting, just can make the Sn atom in lattice can not assemble the sediment that forms Sn, keep the metastable state of GeSn alloy and fractional condensation does not occur, can obtain like this thinner thickness, the good GeSn layer of quality, have advantages of simple, cost is low.And in existing GeSn formation method, MBE method needs expensive equipment and needs ultra high vacuum, complex process and cost are high; CVD method is also not exclusively ripe, because growth temperature is high, thus often there is the fractional condensation of Sn element in metastable GeSn, thus the crystal mass of GeSn layer affected, and its equipment and comparatively costliness of source of the gas, thereby cost is also higher.
It should be noted that, in injection technology process, original Ge fin structure can only have surface part to be changed to GeSn layer, also can all be changed to GeSn layer.Particularly, in the time that the leakage of the source of FinFET needs to form thicker GeSn layer, can inject the ion or the plasma that contain Sn element.Ion and energy of plasma are high, can inject and reach certain depth.In the time that the leakage of the source of FinFET needs to form thinner GeSn layer, not only inject ion or plasma and can form GeSn layer, the molecule that injects Sn atom or contain Sn element also can form GeSn layer.
In an example of the present invention, the method of injecting can adopt Implantation, that is: incide in Ge layer and go thering is ion beam certain energy, that contain Sn element (comprising Sn ion or the plasma containing Sn element), and rest in Ge layer, make Ge layer segment or be all converted to GeSn alloy.The degree of depth that changes injection by changing the energy of ion beam, ion beam energy is higher, injects darker.In injection process, can adopt the voltage of variation to obtain the ion beam energy of variation, thereby Sn element is distributed within the specific limits comparatively equably.Particularly, except conventional Implantation, Implantation also comprises that plasma source Implantation and plasma immersion ion inject, and plasma based ion is injected.In the time that plasma based ion is injected, Ge layer is buried in the plasma that contains Sn element, accelerated under electric field action containing the cation of Sn element, and directive Ge layer surface is also injected in Ge layer.Inject by plasma based ion, can be easy to the implantation dosage that reaches very high, be easy to the GeSn layer of the Sn content that obtains 1%～20%, highly efficient in productivity, cost is also very low, and is subject to the impact of surface configuration little, and nonplanar Ge surface also can be realized equably and being injected.Wherein, plasma immersion ion is injected to a kind of preferred injection mode, because injecting, plasma immersion ion is subject to the impact of substrate shape little, inject more even, on this nonplanar structure of Ge fin structure, inject and can obtain the effect that each position is comparatively evenly injected, make whole source-drain area comparatively be formed uniformly GeSn film, thereby can promote to amplitude peak the electric property of raceway groove.Implantation can form thicker GeSn layer, and Implantation Energy is higher, and GeSn layer is thicker.Preferably, the thickness of GeSn layer is 0.5-100nm.
In an example of the present invention, the method for injection can adopt magnetron sputtering.When magnetron sputtering, Ar ion accelerates to fly to negative electrode Sn target or the target containing Sn under electric field action, and with high-energy bombardment target surface, makes target generation sputter.Sputtering particle is mainly atom, also has a small amount of ion.By adjusting voltage of electric field, the technological parameters such as vacuum degree, make sputtering particle have higher energy, and with higher speed directive Ge layer, part particle can be injected in Ge layer and form metastable GeSn alloy.Alternatively, in the process of utilizing magnetron sputtering to inject to Ge layer, on substrate, load back bias voltage, such as-40～-120V, can make like this part particle sputtering there is more high-energy, be conducive to particle and be injected into the more depths on Ge top layer, for example, can be deep to some nanometers.It should be noted that, the material sputtering during due to magnetron sputtering is more, conventionally can after forming GeSn layer, further form Sn film.Therefore after magnetron sputtering, also need to remove the Sn film that magnetron sputtering forms on GeSn layer.For example, can utilize and GeSn and Sn are had to high corrosion select the solution of ratio to clean to remove Sn film and expose GeSn layer.Common cleaning solution comprises watery hydrochloric acid, dilute sulfuric acid, rare nitric acid.The thickness of the GeSn layer remaining after cleaning is 0.5-20nm, and preferably, this GeSn layer thickness is 0.5-10nm.
In an example of the present invention, in injection technology, heating-up temperature can be controlled between 100-600 ℃, preferably 150-450 ℃.The film quality obtaining under this temperature range is better.Temperature is too low, injects the damage that brings and can not repair, GeSn layer second-rate; Excess Temperature, will spread seriously the Sn in GeSn layer, and the solid solubility of Sn in Ge very low (being atomic percent 0.3% under equilibrium state), the Sn in GeSn layer easily separates out and forms Sn sediment.
In an example of the present invention, after forming GeSn layer, can also strengthen this GeSn layer by annealing in process.The temperature range of annealing is 100-600 ℃, preferably 150-450 ℃.Temperature is too low, injects the damage that brings and can not repair, GeSn layer second-rate; Excess Temperature, will the Sn in GeSn layer be spread seriously, and the solid solubility of Sn in Ge be very low, and the Sn in GeSn easily separates out and forms Sn sediment.It is pointed out that if adopt first grid technique, gate medium wherein may not bear 450 ℃ of above high temperature, and now, the heating-up temperature in injection technology and annealing in process temperature can be controlled at below 400 ℃.
In an example of the present invention, GeSn layer is strain GeSn layer.The thickness of strain GeSn layer is 0.5-100nm.Be preferably 10-40nm.In strain GeSn layer, the atomic percentage conc of Sn is less than 20%.It should be noted that, in the GeSn layer of strain, Sn content is higher completely, and it answers variation larger, and correspondingly its thickness should be reduced to below the critical thickness of relaxation, could keep complete strain.In strain GeSn layer, Sn content is higher, and its critical thickness is thinner.In the time that Sn content is 10%, the variation of answering of the GeSn film of the upper complete strain of Ge is about 1.5%, the now about 30nm of the critical thickness of strain GeSn layer, that is now the GeSn thickness of FinFET source-drain area should not exceed 30nm; And in the time that Sn content is 5%, it answers variation approximately 0.8%, more than its critical thickness can reach 100nm, illustrate that now the GeSn thickness of FinFET source-drain area can reach 100nm and GeSn layer still keeps complete strain.
Need to further illustrate, in the time that GeSn layer is strain GeSn layer, in injection technology, in heating-up temperature and annealing process, the height of annealing temperature need to mate with the material character of strain GeSn layer.The strain GeSn layer that the atomic percentage conc that for example needs Sn in common FinFET device is 3-8%, and the GeSn layer that Sn atomic percentage conc is 8% is stable substantially at 450 ℃, thus now in injection technology in heating-up temperature and annealing process annealing temperature need to be no more than 450 ℃.
The invention allows for the fin formula field effect transistor that leak in a kind of GeSn of having source, formed by above-mentioned disclosed any method, comprising: substrate; Be formed on the Ge fin-shaped channel district on substrate; Be formed on the grid stacked structure on described Ge fin-shaped channel district; And be formed on GeSn source and the leakage of both sides, described Ge fin-shaped channel district.The source-drain area of this fin formula field effect transistor has thinner thickness, the good GeSn layer of quality, has advantages of that electric property is good, cost is low.
It should be noted that, this fin formula field effect transistor with the leakage of GeSn source can form by above-disclosed any method, but is not limited to this.
For making those skilled in the art understand better the present invention, elaboration specific embodiment is as follows:
First, prepare Si substrate, and adopt successively acetone, absolute ethyl alcohol, deionized water and hydrofluoric acid clean for subsequent use.
Secondly, on Si substrate, form Ge fin structure by selective epitaxial process.Particularly, can be on Si substrate first deposited silicon nitride mask, then by photoetching and etching technics, in mask, form opening, pass through selective epitaxial process, in the aperture position selective epitaxial growth Ge of Si top surface fin structure, control the thickness of Ge fin structure, make Ge fin structure thickness be greater than mask layer thickness and form the structure that is fin-shaped.
Then, on Ge fin structure, deposit according to this gate dielectric material HfO
2with grid material TaN/TiAl/TiN, then by photoetching and etching technics, obtain patterned HfO
2/ TaN/TiAl/TiN grid are stacking, and form opening above source region and drain region.
Then, deposition grid spacer material, can, with silicon nitride as grid spacer material, by dry etch process, form grid side wall in the stacking both sides of grid, and form opening above source region and drain region, exposes Ge fin structure at aperture position.The opening size of opening size now when thering is no grid side wall is little.
Finally, using plasma immersion ion injection technology is injected the plasma that contains Sn element in substrate, and now substrate heating temperature is 100-200 ℃, and injecting voltage is 10-25KeV, and implantation dosage is about 5 × 10
16/ cm
2.After injection completes, formed the thick strain GeSn layer of 15-30nm on the Ge fin structure top layer of source and leakage opening part, Sn content is about 8%.Further, by Implantation, can form heavily doped source and drain structure.The substrate that Implantation is completed carries out annealing in process, and annealing temperature is 200-300 ℃, further to strengthen GeSn layer.
Now, obtained the FinFET device that source region and drain region are GeSn material.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, modification, replacement and modification.
Claims (19)
1. a formation method with the fin formula field effect transistor leaking in GeSn source, is characterized in that, comprises the following steps:
Substrate is provided;
On described substrate, form Ge fin structure;
On described Ge fin structure, form the stacking or false grid of grid;
At the opening in formation source region, the stacking or false grid of described grid both sides and drain region, expose described Ge fin structure at described aperture position;
Inject the atom, molecule, ion or the plasma that contain Sn element to described Ge fin structure, to form GeSn layer at described aperture position.
2. the formation method with the fin formula field effect transistor leaking in GeSn source as claimed in claim 1, is characterized in that, also comprises:
Before forming the opening in described source region and drain region, form grid side wall in the stacking or false grid of described grid both sides.
3. the formation method with the fin formula field effect transistor leaking in GeSn source as claimed in claim 1 or 2, is characterized in that, also comprises:
After forming described GeSn layer, remove described false grid, form grid in described false gate region stacking.
4. as described in claim 1-3 any one, have a formation method of fin formula field effect transistor that leak in GeSn source, it is characterized in that, described substrate is Si substrate, ge-on-insulator substrate on Si substrate, Ge substrate, insulator, have the Si substrate on Ge surface.
5. the formation method with the fin formula field effect transistor leaking in GeSn source as described in claim 1-3 any one, is characterized in that, forms described Ge fin structure by selective epitaxial process on described substrate.
6. the formation method with the fin formula field effect transistor leaking in GeSn source as described in claim 1-3 any one, is characterized in that, on described substrate, form described Ge fin structure by photoetching and etching technics, wherein, described underlayer surface is Ge material.
7. the formation method with the fin formula field effect transistor leaking in GeSn source as claimed in claim 6, is characterized in that, described top layer is that the substrate of Ge material is Ge substrate, ge-on-insulator substrate, or has the Si substrate on Ge surface.
8. the formation method with the fin formula field effect transistor leaking in GeSn source as described in claim 1-3 any one, is characterized in that, the method for described injection comprises Implantation.
9. the formation method with the fin formula field effect transistor leaking in GeSn source as claimed in claim 8, is characterized in that, described Implantation comprises that plasma source Implantation and plasma immersion ion inject.
10. the formation method with the fin formula field effect transistor leaking in GeSn source as described in claim 1-3 any one, is characterized in that, the method for described injection comprises magnetron sputtering.
The 11. formation methods with the fin formula field effect transistor leaking in GeSn source as claimed in claim 10, is characterized in that, the process that adopts described magnetron sputtering to inject loads back bias voltage on described substrate.
12. have a formation method of fin formula field effect transistor that leak in GeSn source as described in claim 10 or 11, it is characterized in that, also comprise, remove the Sn film that described magnetron sputtering forms on described GeSn layer.
13. as claimed in claim 12ly have formation methods of fin formula field effect transistors that leak in GeSn source, it is characterized in that, utilize GeSn and Sn are had to high corrosion to select the solution of ratio to clean to remove described Sn film.
14. have a formation method of fin formula field effect transistor that leak in GeSn source as described in claim 1-3 any one, it is characterized in that, the process of described injection heats described substrate, and heating-up temperature is 100-600 ℃.
15. have a formation method of fin formula field effect transistor that leak in GeSn source as described in claim 1-3 any one, it is characterized in that, also comprise, after described injection, to described GeSn layer annealing, annealing temperature is 100-600 ℃.
16. have a formation method of fin formula field effect transistor that leak in GeSn source as described in claim 1-3 any one, it is characterized in that, described GeSn layer is strain GeSn layer.
The 17. formation methods with the fin formula field effect transistor leaking in GeSn source as claimed in claim 16, is characterized in that, the thickness of described strain GeSn layer is 0.5-100nm.
The 18. formation methods with the fin formula field effect transistor leaking in GeSn source as claimed in claim 16, is characterized in that, in described strain GeSn layer, the atomic percentage conc of Sn is less than 20%.
19. 1 kinds have the fin formula field effect transistor that leak in GeSn source, it is characterized in that, comprising:
Substrate;
Be formed on the Ge fin-shaped channel district on substrate;
Be formed on the grid stacked structure on described Ge fin-shaped channel district; And
Be formed on GeSn source and the leakage of both sides, described Ge fin-shaped channel district.
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| CN201410064598.0A CN103839832A (en) | 2014-02-25 | 2014-02-25 | Fin type field effect transistor with GeSn source drain and forming method thereof |
| PCT/CN2014/073838 WO2015127701A1 (en) | 2014-02-25 | 2014-03-21 | Method for forming fin field effect transistor |
| US14/350,677 US20150243505A1 (en) | 2014-02-25 | 2014-03-21 | Method for forming fin field effect transistor |
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| CN201410064598.0A CN103839832A (en) | 2014-02-25 | 2014-02-25 | Fin type field effect transistor with GeSn source drain and forming method thereof |
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| US20130285153A1 (en) * | 2012-04-25 | 2013-10-31 | Taiwan Semiconductor Manufacturing Company Ltd. | Strained structure of semiconductor device and method of making the strained structure |
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| US20130285153A1 (en) * | 2012-04-25 | 2013-10-31 | Taiwan Semiconductor Manufacturing Company Ltd. | Strained structure of semiconductor device and method of making the strained structure |
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