CN108666267A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108666267A CN108666267A CN201710213163.1A CN201710213163A CN108666267A CN 108666267 A CN108666267 A CN 108666267A CN 201710213163 A CN201710213163 A CN 201710213163A CN 108666267 A CN108666267 A CN 108666267A
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- conductive plunger
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 132
- 239000002184 metal Substances 0.000 claims abstract description 132
- 238000004140 cleaning Methods 0.000 claims abstract description 58
- 238000000137 annealing Methods 0.000 claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 18
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 79
- 239000000758 substrate Substances 0.000 claims description 62
- 230000004888 barrier function Effects 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- -1 silicon phosphorus compound Chemical class 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 238000002294 plasma sputter deposition Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 238000007733 ion plating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 318
- 239000012535 impurity Substances 0.000 description 21
- 230000008569 process Effects 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 230000006378 damage Effects 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 208000027418 Wounds and injury Diseases 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 208000014674 injury Diseases 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910021341 titanium silicide Inorganic materials 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000007872 degassing Methods 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000010534 mechanism of action Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical group 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes：Form through dielectric layer and expose the first through hole on source and drain doping area surface；It is formed through dielectric layer and exposes the second through-hole at the top of gate structure；In first through hole bottom and side wall and the second via bottoms and side wall deposition cap layer；First cleaning treatment is carried out to first through hole bottom and the second via bottoms, removal is positioned at first through hole bottom and the cap layer of the second via bottoms；After the first cleaning treatment, the gate structure in the source and drain doping area and the exposing of the second via bottoms expose to first through hole bottom carries out the second cleaning treatment；After carrying out second cleaning treatment, at the top of the first through hole bottom and side wall and the second via bottoms and side wall and dielectric layer on form metal layer；The metal layer is made annealing treatment, converts the metal layer in the source and drain doping area to metal silicide layer.Present invention improves the electric properties of the semiconductor structure of formation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
Develop to super large-scale integration with the making of integrated circuit, the current densities of IC interior are increasingly
Greatly, including number of elements it is also more and more so that crystal column surface is difficult to provide enough areas to make required interconnection
Line.
In order to meet the interconnection line demand after component size reduces, interconnecting metal layer is designed to ultra-large integrated electricity
A kind of method of road technique institute generally use.Currently, the conducting between interconnecting metal layer is realized by conductive plunger, mutually
Even the conducting between metal layer and semiconductor structure is also to be realized by conductive plunger.Specifically, in semiconductor structure
Source and drain doping area is electrically connected by conductive plunger with interconnecting metal layer or other component, and the gate structure in semiconductor structure is logical
Conductive plunger is crossed to be electrically connected with interconnecting metal layer or other component.
However, the electric property for the semiconductor structure with conductive plunger that the prior art is formed is to be improved.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, improves the semiconductor structure of formation
Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
It is formed with gate structure in substrate, forms source and drain doping area in the substrate of the gate structure both sides, and the gate structure reveals
It is formed with dielectric layer in the substrate gone out and at the top of gate structure；It is formed through the dielectric layer and exposes the source and drain doping
The first through hole on area surface；It is formed through the dielectric layer and exposes the second through-hole at the top of the gate structure；Described
One via bottoms and side wall and second via bottoms and side wall deposition cap layer；To the first through hole bottom and
Second via bottoms carry out the first cleaning treatment, block of the removal positioned at the first through hole bottom and the second via bottoms
Layer；The source and drain doping area expose to the first through hole bottom after first cleaning treatment and the second via bottoms
The gate structure of exposing carries out the second cleaning treatment；After carrying out second cleaning treatment, in the first through hole bottom
Metal layer is formed in side wall and the second via bottoms and side wall and dielectric layer top；It anneals to the metal layer
Processing, converts the metal layer in the source and drain doping area to metal silicide layer；After carrying out the annealing,
The first conductive plunger of the full first through hole of filling is formed,；And form the second conductive plunger of full second through-hole of filling.
Optionally, silicon, germanium, silicon Germanium compound or silicon phosphorus compound.
Optionally, the thickness of the cap layer is 5 angstroms~200 angstroms.
Optionally, first cleaning treatment is carried out using physical bombardment technique.
Optionally, using plasma sputtering technology carries out first cleaning treatment.
Optionally, second cleaning treatment is carried out using isotropic dry etch technique.
Optionally, second cleaning treatment is carried out using long-range enhancing plasma process.
Optionally, second cleaning treatment is carried out using SiCoNi etching technics.
Optionally, further include step before forming the cap layer：The grid knot that second via bottoms are exposed
Reproducibility processing is carried out at the top of structure, the reproducibility processing is for removing the oxide layer at the top of the gate structure.
Optionally, the reproducibility processing is carried out using hydrogen plasma.
Optionally, the step coverage of the metal layer of formation is greater than or equal to 80%.
Optionally, the metal layer is formed using radio frequency-ion depositing process.
Optionally, the thickness of the metal layer is 5 angstroms~200 angstroms.
Optionally, the metal layer is formed using atom layer deposition process.
Optionally, before carrying out the annealing or after annealing, formed first conductive plunger and
Further include step before second conductive plunger：Barrier layer is formed on the metal layer；Form first conductive plunger and
In the processing step of two conductive plungers, first conductive plunger and the second conductive plunger are formed on the barrier layer.
Optionally, the material on the barrier layer is TiN or TaN.
Optionally, it is formed in the processing step of first conductive plunger and the second conductive plunger, on the metal layer
Form first conductive plunger and the second conductive plunger.
Optionally, the material of the metal layer is Ti；The material of first conductive plunger is W；Described second is conductive slotting
The material of plug is W.
The present invention also provides a kind of semiconductor structures, including：Substrate has gate structure, the grid in the substrate
There is source and drain doping area in the substrate of structure both sides, and have in the substrate of gate structure exposing and on gate structure top
There is dielectric layer；Through the first conductive plunger of the dielectric layer in the source and drain doping area, first conductive plunger and institute
State the electrical connection of source and drain doping area；Second conductive plunger of the dielectric layer at the top of the gate structure, described second
Conductive plunger is electrically connected with the gate structure；Between the first conductive plunger side wall and the dielectric layer, Yi Jisuo
State the metal layer between the second conductive plunger side wall and the dielectric layer；Metal layer on the first conductive plunger side wall
With the cap layer between the dielectric layer, and the cap layer is also located at metal layer and institute on the second conductive plunger side wall
It states between dielectric layer；Metal silicide layer between first conductive plunger and the source and drain doping area.
Optionally, silicon or germanium, silicon Germanium compound or silicon phosphorus compound.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the technical solution of the forming method of semiconductor structure provided by the invention, first through hole bottom and side wall, with
And second via bottoms and side wall deposition cap layer；Then, first is carried out clearly to first through hole bottom and the second via bottoms
Processing is washed, can both remove the cap layer positioned at first through hole bottom and the second via bottoms, and can also remove positioned at first
The partial impurities of via bottoms and the second via bottoms；The source and drain doping area of first through hole bottom is being exposed and is being led to second
After the gate structure of hole bottom exposes, the second cleaning treatment is carried out, it is logical that second cleaning treatment can effectively remove first
The impurity of hole bottom and the second via bottoms, second cleaning treatment is for removing first through hole bottom and the second through-hole
The silica of bottom, and during the second cleaning treatment, the first through hole side wall and the second through-hole side wall are by block
The protective effect of layer prevents first through hole width dimensions and the second entire widths size from increasing；Then carry out being formed metal layer,
The processing step of metal silicide layer, the first conductive plunger and the second conductive plunger.Therefore, because second cleaning process
In, the cap layer provides protective effect so that the second cleaning treatment more effectively can more thoroughly remove logical positioned at first
The impurity in hole and the second via bottoms, for be subsequently formed the metal layer of high quality, metal silicide layer, the first conductive plunger and
Second conductive plunger provides Process ba- sis so that between the first conductive plunger and source and drain doping area to be electrically connected performance good,
And performance is good for being electrically connected between gate structure and the second conductive plunger, so as to improve the performance of the semiconductor structure of formation.
In alternative, the step coverage of the metal layer of formation is greater than or equal to 80% so that is subsequently formed
The process window of first conductive plunger and the second conductive plunger is big, improves filling out for the first conductive plunger and the second conductive plunger
Pore performance.
Description of the drawings
Fig. 1 is a kind of semiconductor structure along the cross-sectional view for being parallel to fin extending direction；
Fig. 2 is a kind of semiconductor structure along the cross-sectional view perpendicular to fin extending direction；
Fig. 3 to Figure 18 is that the corresponding cross-section structure of each step of method for forming semiconductor structure provided in an embodiment of the present invention shows
It is intended to.
Specific implementation mode
By background technology it is found that the electric property for the semiconductor structure with conductive plunger that the prior art is formed needs to be carried
It is high.
It is analyzed in conjunction with a kind of forming method of semiconductor structure, with reference to figure 1 and Fig. 2, wherein Fig. 1 is a kind of half
For conductor structure along the cross-sectional view for being parallel to fin extending direction, Fig. 2 is a kind of semiconductor structure along perpendicular to fin
The cross-sectional view of extending direction.
With reference to figure 1 and Fig. 2, substrate is provided, there is gate structure 104, the base of the gate structure both sides in the substrate
There is source and drain doping area 105, and the dielectric layer in the substrate of gate structure exposing and on gate structure top in bottom；It passes through
The first through hole 108 of the dielectric layer of 105 top of the source and drain doping area is worn, the first through hole 108 exposes the source and drain doping
105 surface of area；Second through-hole 109 of the dielectric layer above the gate structure 104, second through-hole 109 expose institute
State 104 surface of gate structure.
Wherein, the substrate include substrate 101, the fin 102 on the substrate 101 and be located at the fin
Isolation structure 103 on 102 substrates 101 exposed, the isolation structure 103 cover the partial sidewall of the fin 102, and institute
103 top of isolation structure is stated less than 102 top of fin.The dielectric layer includes：Interlayer dielectric layer in the substrate
106,106 top of the interlayer dielectric layer is flushed with 104 top of the gate structure；Positioned at 106 top of the interlayer dielectric layer
And the top dielectric layer 107 at 104 top of gate structure.
Subsequent processing step includes：In 108 bottom and side wall of the first through hole, 109 bottom and side wall of the second through-hole
Form metal layer；The metal layer is made annealing treatment, metal silicide layer is formed in the source and drain doping area 105；
The first conductive plunger of the filling completely first through hole 108 is formed on the metal layer；It is full that filling is formed on the metal layer
Second conductive plunger of second through-hole 109.
Before forming the metal layer, it usually needs cleaned to the first through hole 108 and the second through-hole 109
Processing removes the impurity of 108 bottom of first through hole and 109 bottom of the second through-hole.However, the cleaning treatment easily causes first
The width dimensions of through-hole 108 and the second through-hole 109 broaden, and then influence the performance of the semiconductor structure formed.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
It is formed with gate structure in substrate, forms source and drain doping area in the substrate of the gate structure both sides, and the gate structure reveals
It is formed with dielectric layer in the substrate gone out and at the top of gate structure；It is formed through the dielectric layer and exposes the source and drain doping
The first through hole on area surface；It is formed through the dielectric layer and exposes the second through-hole at the top of the gate structure；Described
One via bottoms and side wall and second via bottoms and side wall deposition cap layer；To the first through hole bottom and
Second via bottoms carry out the first cleaning treatment, block of the removal positioned at the first through hole bottom and the second via bottoms
Layer；The source and drain doping area expose to the first through hole bottom after first cleaning treatment and the second via bottoms
The gate structure of exposing carries out the second cleaning treatment；After carrying out second cleaning treatment, in the first through hole bottom
Metal layer is formed in side wall and the second via bottoms and side wall and dielectric layer top；It anneals to the metal layer
Processing, converts the metal layer in the source and drain doping area to metal silicide layer；Form the full first through hole of filling
The first conductive plunger；Form the second conductive plunger of full second through-hole of filling.
Since the cap layer positioned at first through hole side wall provides protective effect to the first through hole side wall, it is logical to be located at second
The cap layer of hole side wall provides protective effect to second through-hole side wall, therefore the present invention is logical in removal first through hole and second
While the impurity of hole bottom, effectively prevent the first through hole width dimensions and the second entire widths size from increasing, from
And so that the width dimensions of the first conductive plunger formed and the second conductive plunger meet the requirements, and improve the semiconductor junction of formation
The performance of structure.To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 18 is that the corresponding cross-section structure of each step of method for forming semiconductor structure provided in an embodiment of the present invention shows
It is intended to.
With reference to figure 3 and Fig. 4, substrate is provided, there is gate structure in the substrate, in the substrate of the gate structure both sides
It is formed with source and drain doping area, and dielectric layer is formed in the substrate of gate structure exposing and on gate structure top.
Wherein, Fig. 3 is along the cross-sectional view for being parallel to fin extending direction, and Fig. 4 is to extend along perpendicular to fin
The cross-sectional view in direction.
In the present embodiment, by taking the semiconductor structure of formation is FinFET as an example, the substrate includes：Substrate 201；Position
In the discrete fin 202 on the substrate 201；Isolation structure 203 on the substrate 201 that the fin 202 exposes, institute
The partial sidewall that isolation structure 203 covers fin 202 is stated, and 203 top of the isolation structure is less than 202 top of fin.
In other embodiments, the semiconductor structure can also be planar device, and the substrate is planar substrate.
The material of the substrate 201 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium, and the substrate 201 can also
Enough it is the germanium substrate on the silicon substrate or insulator on insulator；The material of the fin 202 includes silicon, germanium, SiGe, carbon
SiClx, GaAs or gallium indium.In the present embodiment, the substrate 201 is silicon substrate, and the material of the fin 202 is silicon.
The isolation structure 203 plays the role of being electrically isolated adjacent fin 202, and the material of the isolation structure 203 is exhausted
Edge material, for example, silica, silicon nitride, silicon oxynitride or carbon silicon oxynitride.In the present embodiment, the isolation structure 203
Material is silica.
By taking the semiconductor structure of formation is cmos device as an example, the substrate 101 includes NMOS area I and PMOS area
II, the NMOS area I provide technique platform to form NMOS tube, and to provide technique flat to form PMOS tube by the PMOS area II
Platform.In another embodiment, the substrate can also only include PMOS area or NMOS area, the FinFET being correspondingly formed
For PMOS tube or NMOS tube.
It should be noted that in other embodiments, the semiconductor structure of formation can also be NMOS device or PMOS
Device.
The gate structure is located on the isolation structure 203 and across the fin 202, and the gate structure covers
The atop part and side wall of fin 202.In the present embodiment, the gate structure includes：Positioned at the first grid knot of NMOS area I
Structure and second grid structure positioned at PMOS area II.
Wherein, the first grid structure including the first high-k gate dielectric layer 211 and is located at first high-k gate dielectric
First gate electrode layer 213 on layer 211；The second grid structure includes the second high-k gate dielectric layer 221 and positioned at described the
The second gate electrode layer 223 on two high-k gate dielectric layers 221.
The material of first high-k gate dielectric layer, 211 and second high-k gate dielectric layer 221 is high-k gate dielectric material,
In, high-k gate dielectric material refers to that relative dielectric constant is more than the gate dielectric material of silica relative dielectric constant, the high k
Gate dielectric material is HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3.The first gate electrode layer
213 material is Cu, Al or W；The material of second gate electrode layer 223 is Cu, Al or W.
It should be noted that in order to adjust the threshold voltage of NMOS tube and PMOS tube, first high-k gate dielectric layer 211
Can also be formed with N-type workfunction layer 212 between the first gate electrode layer 213, second high-k gate dielectric layer 221 with
It can also be formed with P-type workfunction layer 222 between second gate electrode layer 223.First high-k gate dielectric layer 211 with
Interfacial TCO layer can also be formed between the substrate and between second high-k gate dielectric layer 221 and the substrate, is improved
It is interface characteristics between first high-k gate dielectric layer 211 and the substrate and between the second high-k gate dielectric layer 221 and the substrate
Energy.The material of the boundary layer is silica.
It should be noted that in the present embodiment, the gate structure is metal gate structure；In other embodiments, institute
It can also be polysilicon gate construction to state gate structure.
Side wall 200 is also formed on the gate structure sidewall.The material of the side wall 200 be silicon nitride, silica or
Silicon oxynitride.In the present embodiment, the material of the side wall 200 is silicon nitride.
The source and drain doping area includes：Intrabasement first source and drain of NMOS area I positioned at first grid structure both sides is mixed
Miscellaneous area 231, wherein first source and drain doping area 231 is located in the NMOS area I fins 202, first source and drain doping
The Doped ions in area 231 are N-type ion, for example, P, As or Sb；PMOS area II positioned at second grid structure both sides
Intrabasement second source and drain doping area 232, wherein second source and drain doping area 232 is located at the PMOS area II fins 202
Interior, the Doped ions in second source and drain doping area 232 are p-type ion, for example, B, Ga or In.
In the present embodiment, in order to improve formation semiconductor devices operating rate, form first source and drain doping area
231 processing step includes：The fin 202 for etching the segment thickness of first grid structure both sides, in the first grid
The first groove is formed in the fin 202 of structure both sides；The first stressor layers of full first groove of filling are formed, described first answers
The material of power layer is SiC or SiCP；In the technical process for forming first stressor layers, first stressor layers are carried out former
Position doping, forms first source and drain doping area 231；Alternatively, after forming first stressor layers, to first stress
Layer is doped processing, forms first source and drain doping area 231.
The processing step for forming second source and drain doping area 232 includes：Etch the portion of second grid structure both sides
The fin 202 for dividing thickness forms the second groove in the fin 202 of second grid structure both sides；It is full described to form filling
The material of second stressor layers of the second groove, second stressor layers is SiGe or SiGeB；Forming second stressor layers
In technical process, doping in situ is carried out to second stressor layers, forms second source and drain doping area 232；Alternatively, being formed
After second stressor layers, processing is doped to second stressor layers, forms second source and drain doping area 232.
The material of the dielectric layer is silica, silicon nitride or silicon oxynitride.In the present embodiment, the dielectric layer includes：
Interlayer dielectric layer 301 in the substrate that the gate structure exposes, 301 top of the interlayer dielectric layer and the grid knot
It is flushed at the top of structure；Top dielectric layer 302 at the top of 301 top of the interlayer dielectric layer and the gate structure.
The interlayer dielectric layer 301 can be single layer structure or laminated construction.
It should be noted that in other embodiments, the dielectric layer may be single layer structure.
In the present embodiment, the technique in order to avoid being subsequently formed the second through-hole causes etching injury to the gate structure,
It is also formed with protective layer 303 at the top of the gate structure；Likewise, in order to avoid being subsequently formed the technique of first through hole to institute
It states source and drain doping area and causes etching injury, etching stop layer 304 is also formed in the source and drain doping area；Specifically, the quarter
Stop-layer 304 is lost between the interlayer dielectric layer 301 and the substrate, and is also located at the interlayer dielectric layer 301 and institute
It states between gate structure sidewall.
Wherein, the material of the protective layer 303 is different from the material of the dielectric layer, the material of the etching stop layer 304
Material is different from the material of the dielectric layer.The material of the present embodiment, the dielectric layer is silica, the material of the protective layer 303
Material is silicon nitride, and the material of the etching stop layer 304 is silicon nitride.
With reference to figure 5 and Fig. 6, the first through hole 305 on source and drain doping area surface is formed through the dielectric layer and exposed；
It is formed through the dielectric layer and exposes the second through-hole 306 at the top of the gate structure.
Fig. 5 is structural schematic diagram on the basis of Fig. 3, and Fig. 6 is structural schematic diagram on the basis of Fig. 4.
The first through hole 305 provides technique to be subsequently formed the first conductive plunger being electrically connected with the source and drain doping area
Basis；In addition, the first through hole 305 also provides work to be subsequently formed the metal contact layer being electrically connected with the source and drain doping area
Skill basis.Second through-hole 306 provides technique base to be subsequently formed the second conductive plunger being electrically connected with the gate structure
Plinth.
305 bottom-exposed of the first through hole goes out the part surface or all surfaces in the source and drain doping area.Specifically,
The first through hole 305 exposes first source and drain doping area, 231 part surface or all surfaces, the first through hole
305 also expose second source and drain doping area, 232 part surface or all surfaces.
In the present embodiment, the first through hole 305 exposes first source and drain doping area, 231 all surfaces and second
232 all surfaces of source and drain doping area.
In the present embodiment, second through-hole 306 exposes the gate structure atop part.Specifically, described second
Through-hole 306 exposes at the top of the first grid structure division and at the top of second grid structure division.
In order to save the process step, in the present embodiment, formed in the processing step with along with the first through hole 305 and
Second through-hole 306.In other embodiments, the first through hole and the second through-hole can also be sequentially formed, is initially formed described
Second through-hole is formed after first through hole, or forms the first through hole after being initially formed second through-hole.
Subsequent processing step includes：305 bottom and side wall of the first through hole, 306 bottom of the second through-hole and
Side wall deposition cap layer.Further include step before depositing the cap layer in the present embodiment：To second via bottoms
Reproducibility processing is carried out at the top of the gate structure of exposing.
Specifically, with reference to figure 7, Fig. 7 is structural schematic diagram on the basis of Fig. 6, is exposed to 306 bottom of the second through-hole
Gate structure at the top of carry out reproducibility processing 307, reproducibility processing 307 is located at for removing at the top of the gate structure
Oxide layer.
It is influenced by process environments, it is upper at the top of the gate structure that 306 bottom of the second through-hole is exposed easily to form oxidation
Layer.In the present embodiment, the gate structure is metal gate structure, correspondingly, the material of the oxide layer is metal oxide.
The oxide layer can generate unfavorable shadow to the electrical connection properties between the second conductive plunger being subsequently formed and the gate structure
It rings.For this reason, it may be necessary to remove the oxide layer at the top of the gate structure that 306 bottom of the second through-hole is exposed.
Oxide layer at the top of the gate structure is located at using 307 removal of reproducibility processing.Its specific mechanism of action includes：
Redox reaction is carried out to the oxide layer at the top of the gate structure by gas of the introducing with reproducibility, by the oxidation
The material of layer is reduced into metal material.
Oxide layer at the top of the gate structure is located at using 307 removal of reproducibility processing, can either ensure to be located at grid
The oxide layer of structural top is removed, additionally it is possible to be reduced or even eliminated the oxide layer to be formed and be made to the gate structure thickness parameter
At harmful effect.Further, it is also possible to which the reproducibility is avoided to handle 307 pairs of source and drain for being located at 305 bottom of the first through hole
Doped region causes harmful effect.
In the present embodiment, the reproducibility processing 307 is carried out using hydrogen plasma.
It should be noted that before carrying out the reproducibility processing, to the first through hole 305 and the second through-hole
306 carry out degassing processing (degas), and the degassing processing is for removing in the first through hole 305 and the second through-hole 306
Steam.
With reference to figure 8 and Fig. 9, in 305 bottom and side wall of the first through hole and 306 bottom of the second through-hole and side
Wall deposits cap layer 308.
Wherein, Fig. 8 is structural schematic diagram on the basis of Fig. 5, and Fig. 9 is structural schematic diagram on the basis of Fig. 7.
In the present embodiment, the cap layer 308 of formation is also located at the top of the dielectric layer.The cap layer 308 is located at
In the source and drain doping area of 305 bottom of the first through hole, and it is also located at the top of the gate structure of 306 bottom of the second through-hole
On.The effect of the cap layer 308 includes：
On the one hand, rear extended meeting starts the cleaning processing 305 bottom of the first through hole and 306 bottom of the second through-hole, removal
The impurity of 306 bottom of 305 bottom of first through hole and the second through-hole, the first conductive plunger and second to be subsequently formed high quality are led
Electric plug provides Process ba- sis；During the cleaning treatment, the cap layer 308 for being located at 305 side wall of the first through hole is right
305 side wall of the first through hole plays a protective role, and prevents the width dimensions of first through hole 305 from increasing；Likewise, described clear
It washes in processing procedure, the cap layer 308 positioned at 306 side wall of the second through-hole plays a protective role to 306 side wall of the second through-hole,
Prevent the width dimensions of second through-hole 306 from increasing.
On the other hand, rear extended meeting forms metal layer in the cap layer 308, and the metal layer can be undergone at annealing
Reason, in the annealing process, the cap layer 308 being located on 305 side wall of the first through hole occurs with the metal layer
Chemical reaction then improves the be subsequently formed to improve the adhesiveness between 305 side wall of metal layer and the first through hole
Adhesiveness between 305 side wall of one conductive plunger and the first through hole；Likewise, on 306 side wall of the second through-hole
Cap layer 308 be conducive to improve the adhesiveness between metal layer and 306 side wall of the second through-hole, then improve and be subsequently formed
The second guided missile plug and 306 side wall of the second through-hole between adhesiveness.
Since rear extended meeting removal is located at the cap layer 308 of 306 bottom of 305 bottom of the first through hole and the second through-hole,
Therefore the material of the cap layer 308 is to be easy to be etched the material of removal, and etch the technique pair for removing the cap layer 308
The damage of the source and drain doping area and gate structure is small；Meanwhile the material of the cap layer 308 be also can be subsequently formed
The material that reacts of metal layer, play the role of reducing contact resistance, improve interface contact performance.
For this purpose, in the present embodiment, the material of the cap layer 308 is silicon.In other embodiments, the material of the cap layer
Material can also be germanium, silicon Germanium compound or silicon phosphorus compound.
The thickness of the cap layer 308 is unsuitable excessively thin, also unsuitable blocked up.If the thickness of the cap layer 308 is excessively thin, after
During continuous cleaning treatment, it is located at the cap layer 308 on 305 side wall of the first through hole to 305 side wall of the first through hole
The protective effect played is insufficient, is located at the cap layer 308 on 306 side wall of the second through-hole to 306 side wall of the second through-hole
The protective effect played is insufficient；If the thickness of the cap layer 308 is blocked up, subsequent etching removal is located at the first through hole
The technology difficulty of the cap layer 308 of 306 bottom of 305 bottoms and the second through-hole is high.
For this purpose, in the present embodiment, the thickness of the cap layer 308 is 5 angstroms~200 angstroms.
In the present embodiment, in order to improve formation cap layer 308 Step Coverage ability, using atom layer deposition process shape
At the cap layer 308.
With reference to figure 10 and Figure 11,305 bottom of the first through hole and 306 bottom of the second through-hole are carried out at the first cleaning
Reason 309, cap layer 308 of the removal positioned at 306 bottom of 305 bottom of the first through hole and the second through-hole.
Wherein, Figure 10 is structural schematic diagram on the basis of Fig. 8, and Figure 11 is structural schematic diagram on the basis of Fig. 9.
Lid of the removal of first cleaning treatment 309 positioned at 306 bottom of 305 bottom of the first through hole and the second through-hole
Cap layers 308, subsequently to carry out the second cleaning treatment to first through hole 305 and 306 bottom of the second through-hole, removal is located at described
The impurity of 306 bottom of 305 bottom of first through hole and the second through-hole.
In the present embodiment, first cleaning treatment 309 also removes the cap layer 308 at the top of the dielectric layer.
First cleaning treatment 309 is carried out using physical bombardment technique so that the first cleaning treatment 309 is to first through hole
305 and 306 bottom of the second through-hole damage it is small.
In the present embodiment, using plasma sputtering technology (plasma sputter) carries out first cleaning treatment
309。
With reference to figure 12 and Figure 13, after first cleaning treatment 309,305 bottom of the first through hole is exposed
The gate structure that source and drain doping area and 306 bottom of the second through-hole are exposed carries out the second cleaning treatment 310.
Second cleaning treatment 310 is located at 306 bottom of 305 bottom of the first through hole and the second through-hole for removing
Impurity.
Specifically, the source and drain doping area surface of 305 bottom of the first through hole easily generates natural oxide by oxidation
(native oxide) impurity, and aforementioned etch in the processing step for forming first through hole 305 also easily makes the first through hole 305
Bottom remains etch by-products impurity.Second cleaning treatment 310 is used to remove positioned at 305 bottom of the first through hole
Natural oxide impurity and etch by-products impurity.
306 bottom of the second through-hole is also easily set to remain quarter in the processing step of the second through-hole 306 of aforementioned etching formation
Lose by-product impurities.Second cleaning treatment 310 is additionally operable to etch by-products of the removal positioned at 306 bottom of the second through-hole
Impurity.
During the second cleaning treatment 310, due to 306 side of 305 side wall of the first through hole and the second through-hole
Wall by cap layer 308 protection, therefore can to avoid 305 side wall of the first through hole and 306 side wall of the second through-hole by
Damage, to which removal is located at 305 bottom of the first through hole under conditions of not increasing by 305 width dimensions of first through hole
Impurity, removal is positioned at the miscellaneous of 306 bottom of the second through-hole under conditions of not increasing by 306 width dimensions of the second through-hole
Matter.
Due to the protective effect of the cap layer 308 on 305 side wall of the first through hole so that at second cleaning
Reason can more effectively remove the impurity positioned at 305 bottom of the first through hole, without protecting 305 side wall of first through hole for consideration
Degree that is injury-free and reducing removal 305 impurities at bottom of first through hole.Likewise, second cleaning treatment can more have
The removal of effect is reduced positioned at the impurity of 306 bottom of the second through-hole without being consideration 306 side wall of the second through-hole injury-free two
Remove the degree of 306 impurities at bottom of the second through-hole.
Second cleaning treatment is carried out using isotropic dry etch technique.In the present embodiment, using long-range enhancing
Plasma process (enhanced remote plasma) carries out second cleaning treatment 310, is located at described the in removal
While the impurity of 306 bottom of one through-hole, 305 bottom and the second through-hole, be conducive to reduce or avoid the first through hole 305
The damage that the source and drain doping area of bottom is subject to, and the damage for reducing or the gate structure of 306 bottom of the second through-hole being avoided to be subject to
Wound.In other embodiments, SiCoNi etching technics can also be used to carry out second cleaning treatment.
With reference to figure 14 and Figure 15, after second cleaning treatment 309,305 bottom and side wall of the first through hole,
And form metal layer 311 on 306 bottom and side wall of the second through-hole and dielectric layer top.
In the present embodiment, 311 foregoing description first through hole of metal layer, 305 side wall and the second through-hole 306 are being formed
Also there is cap layer 308, therefore the metal layer 311 formed is also located in the cap layer 308 on side wall.
The metal layer 311 provides metallic atom to be subsequently formed metal silicide layer.The material of the metal layer 311 is
It is one or more in Ni, W, Ti, Ta, Pt or Co.
In the present embodiment, the material of the metal layer 311 is Ti.Material using Ti as the metal layer 311, rear
Continue after being made annealing treatment, without removing the metal layer 311 not chemically reacted, therefore metal layer 311 can retain
In 306 bottom and side wall of the second through-hole, to save processing step；In addition, being located at 306 bottom of the second through-hole
It can also play the role of adhesion layer with the metal layer 311 on side wall；Metal layer on 106 side wall of the first through hole
304 can also play the role of adhesion layer.
In the present embodiment, the step coverage of the metal layer 311 of formation is greater than or equal to 80%, for example, 80%,
90%.Wherein, the step coverage refers to thickness positioned at the metal layer 311 of 305 bottom of the first through hole and is located at
The ratio of the thickness of metal layer 311 at the top of the dielectric layer.
Since the step coverage of the metal layer 311 is big so that be located at the metal layer 311 at the top of the dielectric layer
Thickness differs small with 311 thickness of metal layer of 305 bottom of the first through hole, and the metal layer on dielectric layer top
311 thickness differs smaller with the thickness of the metal layer 311 of 306 bottom of the second through-hole, therefore is forming the metal layer
After 311, the process window that the first conductive plunger is formed subsequently in the first through hole 305 is big, so that formed the
The filling perforation performance of one conductive plunger is good, likewise, the filling perforation function admirable for the second conductive plunger being subsequently formed.
In the present embodiment, the metal layer 311 is formed using radio frequency-ion depositing process, the thickness of the metal layer 311 is 5
Angstrom~200 angstroms.
In other embodiments, can also the metal layer be formed using atom layer deposition process.
Extended meeting makes annealing treatment the metal layer 311 afterwards.In the present embodiment, before carrying out the annealing,
It further include step：Barrier layer 312 is formed on the metal layer 311.
The barrier layer 312 can play improve between metal layer 311 and the first conductive plunger being subsequently formed, Yi Jijin
Belong to the effect of the adhesiveness between layer 311 and the second conductive plunger being subsequently formed；Also, works as and be subsequently formed the first conductive plunger
And second source material of conductive plunger when including fluorine material, the barrier layer 312 can stop fluorine ion and the gold
Belong to layer 311 and unnecessary reaction occurs.
In the present embodiment, the material on the barrier layer 312 is titanium nitride, and the blocking is formed using atom layer deposition process
Layer 312.In other embodiments, the material on the barrier layer can also be tantalum nitride.
In the present embodiment, the barrier layer 312 is formed before carrying out the annealing, is conducive to prevent metal layer
311 material is the O in environment before being made annealing treatment2It is aoxidized, and is conducive to promote in subsequent anneal processing procedure
Into the formation of metal silicide layer.
It should be noted that in other embodiments, after the annealing can also being carried out, on the metal layer
Form barrier layer.
With reference to figure 16, Figure 16 is structural schematic diagram on the basis of Figure 14, is made annealing treatment to the metal layer 311,
Convert the metal layer 311 in the source and drain doping area to metal silicide layer 313.
In the annealing process, gold occurs for the material of the metal layer 311 and the material in the source and drain doping area
Belong to silicification reaction, to convert the metal layer 311 being located in the source and drain doping area to metal silicide layer 313.Specifically,
Metal layer 311 in first source and drain doping area 231 is converted into metal silicide layer 313, and is located at second source
Metal layer 311 on leakage doped region 232 is converted into metal silicide layer 313.
Second cleaning treatment has been carried out to 305 bottom of the first through hole due to aforementioned, has been eliminated logical positioned at described first
The impurity in source and drain doping area that 305 bottom of hole is exposed, for the good metal silication of forming properties in the source and drain doping area
Nitride layer 313 provides good interface basis.
In the present embodiment, the material Ti of the metal layer 311, the material of the metal silicide layer 313 formed accordingly
Material is titanium silicide.
After carrying out the reaction annealing, retain in the first through hole 305 and the second through-hole 306
Barrier layer 312 and the metal layer 3111 not reacted.It is conductive in be subsequently formed the filling completely first through hole 305 first
When plug, metal layer 311 and barrier layer 312 on 305 side wall of the first through hole, which play, improves the first conductive plunger
The effect of adhesiveness between dielectric layer；In rear formation filling completely the second conductive plunger of second through-hole 306, it is located at institute
State metal layer 311 and barrier layer 312 on 306 side wall of the second through-hole play improve the second conductive plunger and the dielectric layer it
Between adhesiveness effect.
In the annealing process, it is located at the cap layer 308 on 305 side wall of the first through hole and the metal layer
311 chemically react, and transition is formed between the cap layer 308 and the metal layer 311 of 305 side wall of the first through hole
Layer；It is chemically reacted between cap layer 308 and the metal layer 311 on 306 side wall of the second through-hole, described
Shape crosses layer between the cap layer 308 and the metal layer 311 of second through-hole, 306 side wall.
Transition zone on 305 side wall of the first through hole is conducive to improve the metal layer 311 and the dielectric layer
Between adhesiveness, the transition zone on 306 side wall of the second through-hole is conducive to improve the metal layer 311 and given an account of
Adhesiveness between matter layer.
In the present embodiment, the material of the cap layer 308 is silicon, and the material of the metal layer 311 is titanium, correspondingly, institute
The material for stating transition zone is titanium silicide.
With reference to figure 17 and Figure 18, after carrying out the annealing, the full 305 (reference of the first through hole of filling is formed
The first conductive plunger 315 Figure 16), and form the second conductive plunger of full second through-hole 306 (with reference to figure 15) of filling
316。
In the present embodiment, first conductive plunger, 315 and second conductive plunger is formed on the barrier layer 312
316。
The material of first conductive plunger 316 includes copper, aluminium or tungsten；The material of second conductive plunger 316 includes
Copper, aluminium or tungsten.In the present embodiment, the material of first conductive plunger 316 is tungsten, the material of second conductive plunger 316
For tungsten.
The processing step for forming first conductive plunger, 315 and second conductive plunger 316 includes：Form the full institute of filling
The conductive film of first through hole 305 and the second through-hole 306 is stated, the conductive film is also located on the dielectric layer top；Using flat
Smooth chemical industry skill, removal are higher than the conductive film at the top of the dielectric layer, and form the filling completely first through hole 305 first is conductive slotting
Second conductive plunger 316 of plug 315 and filling completely second through-hole 306.
In the present embodiment, it includes fluorine-containing to form the source material of 315 and second conductive plunger 316 of the first conductive plunger
Material, wherein in the technical process for forming 315 and second conductive plunger 316 of the first conductive plunger, the barrier layer
312 play the role of stopping that fluorine ion reacts with 311 material of metal layer.
During the flatening process, also removal is located at the barrier layer 312 at the top of the dielectric layer and metal
Layer 311.
Due to the block in the aforementioned processing step for carrying out the second cleaning treatment, being located on 305 side wall of the first through hole
308 pairs of 305 side wall of the first through hole of layer play a protective role, and reduce or avoid second cleaning treatment to described first
The influence of 305 width dimensions of through-hole, to ensure that 315 width dimensions of the first conductive plunger to be formed meet the requirements.Likewise, position
It plays a protective role to second through-hole 306 in the cap layer 308 on 306 side wall of the second through-hole, and then ensures to be formed
316 width dimensions of the second conductive plunger meet the requirements.Therefore, the property for the semiconductor structure that the present embodiment is formed is improved.
In addition, the step coverage of the metal layer 311 formed in the present embodiment is big, pushed up so as to improve first through hole 305
The metal layer 311 in portion region protrudes (overhang) problem, so that the process window for forming the first conductive plunger 315 increases
Add, improves the performance of the first conductive plunger 315 of formation.Likewise, in the present embodiment, the work of the second conductive plunger 316 is formed
Skill window increases, and improves the performance for the second conductive plunger 316 to be formed.
It should be noted that in other embodiments, forming the source of first conductive plunger and the second conductive plunger
Can also not have fluorine material in material, it is aforementioned accordingly to may not need to form barrier layer, it is conductive slotting forming described first
In the processing step of plug and the second conductive plunger, first conductive plunger is formed on the metal layer and the second conduction is inserted
Plug.
With reference to figure 17 and Figure 18, the present invention also provides a kind of semiconductor structure, the semiconductor structure includes：
Substrate has gate structure in the substrate, in the substrate of the gate structure both sides there is source and drain often to go, and institute
Stating in the substrate of gate structure exposing and at the top of gate structure has dielectric layer；
Through the first conductive plunger 315 of the dielectric layer in the source and drain doping area, first conductive plunger 315
It is electrically connected with the source and drain doping area；
Second conductive plunger 316 of the dielectric layer at the top of the gate structure, second conductive plunger
316 are electrically connected with the gate structure；
Between 315 side wall of the first conductive plunger and the dielectric layer and second conductive plunger 316 with
Metal layer 311 between the dielectric layer；
The cap layer 308 between metal layer 311 and the dielectric layer on 315 side wall of the first conductive plunger,
And the cap layer 308 is also located at the metal layer 311 on 316 side wall of the second conductive plunger and between the dielectric layer；
Metal silicide layer 313 between first conductive plunger 315 and the source and drain doping area.
Semiconductor structure provided in an embodiment of the present invention is described in detail below with reference to attached drawing.
In the present embodiment, the substrate includes NMOS area I and PMOS area II；The substrate include substrate 201 with
And the fin 202 on the substrate 201, the isolation structure 203 being located on the substrate 201.
The gate structure includes the second gate positioned at the first grid structure of NMOS area I and positioned at PMOS area II
Pole structure.The source and drain doping area includes positioned at the first source and drain doping area 231 of NMOS area I and positioned at PMOS area II
Second source and drain doping area 232.
The dielectric layer includes interlayer dielectric layer 301 and positioned at the top of the interlayer dielectric layer 301 and gate structure top
The top dielectric layer 302 in portion.
It can refer to the phase of previous embodiment in relation to the description of the substrate, gate structure, source and drain doping area and dielectric layer
It should describe, details are not described herein.
In the present embodiment, the material of first conductive plunger 315 is tungsten, and the material of second conductive plunger 316 is
Tungsten.The material of the metal layer 311 is titanium；The material of the metal silicide layer 313 is titanium silicide.
In the present embodiment, the material of the cap layer 308 is silicon.In other embodiments, the material of the cap layer is also
Can be germanium, silicon Germanium compound or silicon phosphorus compound.Can also have between the cap layer 308 and the metal layer 311
Transition zone, wherein the material of the cap layer 308 is silicon, when the material of the metal layer 311 is titanium, the material of the transition zone
Material is titanium silicide.
In the present embodiment, the semiconductor structure further includes：Positioned at the metal layer 311 and first conductive plunger
Barrier layer 312 between 315, the barrier layer 312 between the metal layer 311 and second conductive plunger 316.It is described
The material on barrier layer 312 is titanium nitride or tantalum nitride；The barrier layer 312 be conducive to improve the metal layer 311 with it is described
Adhesiveness between first conductive plunger 315 and between the metal layer 311 and second conductive plunger 316.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, gate structure is formed in the substrate, source and drain doping area is formed in the substrate of the gate structure both sides,
And it is formed with dielectric layer in the substrate of the gate structure exposing and on gate structure top；
Form through the dielectric layer and expose the first through hole on source and drain doping area surface；
It is formed through the dielectric layer and exposes the second through-hole at the top of the gate structure；
In the first through hole bottom and side wall and second via bottoms and side wall deposition cap layer；
First cleaning treatment is carried out to the first through hole bottom and the second via bottoms, removal is located at the first through hole bottom
The cap layer of portion and the second via bottoms；
The source and drain doping area expose to the first through hole bottom after first cleaning treatment and the second via bottoms
The gate structure of exposing carries out the second cleaning treatment；
After carrying out second cleaning treatment, in the first through hole bottom and side wall and the second via bottoms and side
Metal layer is formed at the top of wall and dielectric layer；
The metal layer is made annealing treatment, converts the metal layer in the source and drain doping area to metal silicide
Layer；
Form the first conductive plunger of the full first through hole of filling；
Form the second conductive plunger of full second through-hole of filling.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the cap layer be silicon,
Germanium, silicon Germanium compound or silicon phosphorus compound.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of the cap layer is 5 angstroms
~200 angstroms.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that carry out institute using physical bombardment technique
State the first cleaning treatment.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that using plasma sputtering technology into
Row first cleaning treatment.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that use isotropic dry etch work
Skill carries out second cleaning treatment.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that using long-range enhancing plasma work
Skill carries out second cleaning treatment.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that carried out using SiCoNi etching technics
Second cleaning treatment.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that before forming the cap layer,
It further include step：Reproducibility processing, the reproducibility processing are carried out at the top of the gate structure exposed to second via bottoms
For removing the oxide layer being located at the top of the gate structure.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that carry out institute using hydrogen plasma
State reproducibility processing.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the platform of the metal layer of formation
Rank coverage rate is greater than or equal to 80%.
12. the forming method of the semiconductor structure as described in claim 1 or 11, which is characterized in that use RF ion plating work
Skill forms the metal layer.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of the metal layer is 5 angstroms
~200 angstroms.
14. the forming method of the semiconductor structure as described in claim 1 or 11, which is characterized in that use atomic layer deposition work
Skill forms the metal layer.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that carrying out the annealing
After preceding or annealing, is formed before first conductive plunger and the second conductive plunger, further include step：In the gold
Belong to and forms barrier layer on layer；It is formed in the processing step of first conductive plunger and the second conductive plunger, on the barrier layer
It is upper to form first conductive plunger and the second conductive plunger.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that the material on the barrier layer is
TiN or TaN.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that form first conductive plunger
In the processing step of the second conductive plunger, first conductive plunger and the second conductive plunger are formed on the metal layer.
18. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the metal layer is Ti；
The material of first conductive plunger is W；The material of second conductive plunger is W.
19. a kind of semiconductor structure, which is characterized in that including：
Substrate has gate structure in the substrate, has source and drain doping area in the substrate of the gate structure both sides, and described
There is dielectric layer in the substrate that gate structure exposes and at the top of gate structure；
Through the first conductive plunger of the dielectric layer in the source and drain doping area, first conductive plunger and the source and drain
Doped region is electrically connected；
Second conductive plunger of the dielectric layer at the top of the gate structure, second conductive plunger and the grid
Pole structure electrical connection；
Between the first conductive plunger side wall and the dielectric layer and the second conductive plunger side wall with given an account of
Metal layer between matter layer；
The cap layer between metal layer and the dielectric layer on the first conductive plunger side wall, and the cap layer is also
Between metal layer and the dielectric layer on the second conductive plunger side wall；
Metal silicide layer between first conductive plunger and the source and drain doping area.
20. semiconductor structure as claimed in claim 19, which is characterized in that the material of the cap layer is silicon or germanium, SiGe
Compound or silicon phosphorus compound.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021169816A1 (en) * | 2020-02-28 | 2021-09-02 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN113644026A (en) * | 2021-07-29 | 2021-11-12 | 上海华力集成电路制造有限公司 | Method for improving threshold voltage adaptation and alternating current performance of FinFET device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347331A (en) * | 2010-08-02 | 2012-02-08 | 海力士半导体有限公司 | Semiconductor device and method for manufacturing same |
| CN104733389A (en) * | 2013-12-20 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Forming method for transistor |
| CN105448863A (en) * | 2014-09-04 | 2016-03-30 | 台湾积体电路制造股份有限公司 | Semiconductor structure with contact plug |
| CN105590910A (en) * | 2014-09-05 | 2016-05-18 | 联华电子股份有限公司 | Semiconductor structure and manufacturing process thereof |
| CN106548940A (en) * | 2015-09-16 | 2017-03-29 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
-
2017
- 2017-04-01 CN CN201710213163.1A patent/CN108666267B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347331A (en) * | 2010-08-02 | 2012-02-08 | 海力士半导体有限公司 | Semiconductor device and method for manufacturing same |
| CN104733389A (en) * | 2013-12-20 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Forming method for transistor |
| CN105448863A (en) * | 2014-09-04 | 2016-03-30 | 台湾积体电路制造股份有限公司 | Semiconductor structure with contact plug |
| CN105590910A (en) * | 2014-09-05 | 2016-05-18 | 联华电子股份有限公司 | Semiconductor structure and manufacturing process thereof |
| CN106548940A (en) * | 2015-09-16 | 2017-03-29 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021169816A1 (en) * | 2020-02-28 | 2021-09-02 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN113644026A (en) * | 2021-07-29 | 2021-11-12 | 上海华力集成电路制造有限公司 | Method for improving threshold voltage adaptation and alternating current performance of FinFET device |
| CN113644026B (en) * | 2021-07-29 | 2024-04-26 | 上海华力集成电路制造有限公司 | Method for improving threshold voltage adaptation and alternating current performance of FinFET device |
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