CN103594364A - A method for manufacturing a semiconductor device - Google Patents
A method for manufacturing a semiconductor device Download PDFInfo
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- CN103594364A CN103594364A CN201210289041.8A CN201210289041A CN103594364A CN 103594364 A CN103594364 A CN 103594364A CN 201210289041 A CN201210289041 A CN 201210289041A CN 103594364 A CN103594364 A CN 103594364A
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 18
- 238000010276 construction Methods 0.000 claims description 12
- 230000000873 masking effect Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 7
- 238000005224 laser annealing Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000470 constituent Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 31
- 230000003628 erosive effect Effects 0.000 abstract description 14
- 229910052759 nickel Inorganic materials 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 49
- 229910021332 silicide Inorganic materials 0.000 description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
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- 229920005591 polysilicon Polymers 0.000 description 3
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 150000004706 metal oxides Chemical class 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
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- 229910017604 nitric acid Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
The invention provides a method for manufacturing a semiconductor device comprising providing a semiconductor substrate on which a grid structure and sidewall structures are formed, wherein the sidewall structures are arranged on the two sides of the grid structure and tightly close to the grid structure; executing ion implantation on regions at the two sides of the grid structure on the semiconductor substrate, wherein a source region and a drain region are to be formed in the regions; forming an insulating layer on the semiconductor substrate in order to fill a region over the regions which are located on the two sides of the grid structure and where ion implantation is executed; executing an annealing process in order to excite implanted ions in the region where ion implantation is executed; removing the insulating layer; forming silicified nickel layer on the top of the grid structure and the surfaces of the source region and the drain region, wherein in the annealing process, a silicon crystal lattice displaced boundary is not formed on the semiconductor substrate under the sidewall structure. The method may stop silicified nickel from eroding the channel region of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor fabrication process, the method in particular to a kind of minimizing nickle silicide (NiSi) to the erosion of semiconductor device channel region.
Background technology
Live width based on narrower, less sheet resistance and the less advantages such as silicon consumption, nickle silicide has been widely used as contact (contact) metal silicide.In existing MOS transistor technique; conventionally according to following process sequences at the top of grid structure and the surface in source region and drain region form nickle silicide: source/drain region Implantation, high annealing → prerinse semiconductor substrate surface → nickel deposited metal level and TiN protective layer → anneal for the first time → selective etch is removed the nickel that do not react with silicon → anneal for the second time.In the process of above-mentioned annealing in process, the channel region of formed nickle silicide meeting transversal erosion grid below, as shown in Figure 1A; This transversal erosion meeting causes the electrical short of transistor unit, the electrical short between source transistor, leakage and trap for example, thus finally cause the low yield of semiconductor device finished product.
In existing MOS transistor technique, before the top of grid structure and the surface in source region and drain region formation nickle silicide, conventionally according to following process sequences, implement a stress memory process: Implantation → deposition stress material layer is implemented to cover described grid structure and described source region and drain region → the injection element in described source region and drain region is evenly spread by enforcement annealing process in the source region in the Semiconductor substrate of grid structure both sides and drain region, and the stress transfer that described stress material layer is had in Semiconductor substrate → remove described stress material layer.Figure 1B shows take the schematic cross sectional view of NMOS as the device architecture of example after above-mentioned stress memory process, under the effect of the tension stress in transferring to Semiconductor substrate 100, 102He drain region, source region 103 in grid structure 101 both sides there will be the silicon crystal lattice dislocation boundary shown in oblique line 104 near the place of channel region respectively, this be when annealing be positioned at described grid structure 101 both sides side wall construction 105 below by light shield edge effect, caused, and described light shield edge effect is by the generation that difference in height is induced between described grid structure 101 and 102Ji drain region, described source region 103.When the silicide on 103 surfaces, 102He drain region, the described source region of follow-up formation, described silicide moves to described channel region along described silicon crystal lattice dislocation boundary, thereby causes the generation of above-mentioned erosion.
Therefore, need a kind of manufacture method of semiconductor device, expectation the method can address the above problem effectively, to improve the rate of finished products that semiconductor device is manufactured.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: Semiconductor substrate is provided, in described Semiconductor substrate, be formed with grid structure, and in described Semiconductor substrate, be formed with and be positioned at described grid structure both sides and near the side wall construction of described grid structure; To forming the region in source region and drain region in the Semiconductor substrate of described grid structure both sides, implement Implantation; In described Semiconductor substrate, form an insulating barrier, to fill the region of the top, region of the described enforcement Implantation that is positioned at described grid structure both sides; Carry out an annealing process, to activate the injection ion in the region of described enforcement Implantation; Remove described insulating barrier; And at the top of described grid structure and the surface in described source region and described drain region form nickel silicide layer, wherein, described insulating barrier is offset the edge effect of the described side wall construction being produced by the difference in height between described grid structure and described source/drain region, in described annealing process, in the Semiconductor substrate of described side wall construction below, can not form silicon crystal lattice dislocation boundary.
Further, the constituent material of described insulating barrier comprises silicon dioxide, silicon nitride or amorphous carbon.
Further, adopt chemical vapor deposition method or radio frequency plasma chemical vapor deposition method to form described insulating barrier.
Further, the thickness of described insulating barrier is 10-1000nm.
Further, described annealing process is peak value annealing, samming annealing, laser annealing or flash lamp annealing.
Further, while adopting described peak value annealing, annealing temperature is 300-1100 ℃.
Further, while adopting described samming annealing, annealing temperature is 200-1100 ℃, and annealing time is 5s-5h.
Further, while adopting described laser annealing or described flash lamp annealing, annealing temperature is 500-1350 ℃, and annealing time is 0.1ms-1s.
Further, before forming described insulating barrier, be also included in the step that forms a stressor layers in described Semiconductor substrate, to cover the region of described grid structure and described enforcement Implantation.
Further, before carrying out described annealing process, also comprise the step of grinding described insulating barrier, make the surfacing of described insulating barrier.
Further, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer stacking gradually.
Further, in removing the process of described insulating barrier, described grid hard masking layer is removed in the lump.
According to the present invention, can stop the erosion of nickle silicide to semiconductor device channel region, thereby improve the rate of finished products that semiconductor device is manufactured.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A is the schematic diagram of nickle silicide to the erosion of semiconductor device channel;
Figure 1B is for take the schematic cross sectional view of NMOS as the device architecture of example after implementing stress memory process;
Fig. 2 A-Fig. 2 E is the schematic cross sectional view of the minimizing nickle silicide that proposes of the present invention to each step of the method for the erosion of semiconductor device channel region;
Fig. 3 is the flow chart of the minimizing nickle silicide that proposes of the present invention to the method for the erosion of semiconductor device channel region.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the method for the minimizing nickle silicide that explaination the present invention proposes to the erosion of semiconductor device channel region.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Below, only take nmos pass transistor as example, with reference to Fig. 2 A-Fig. 2 E and Fig. 3, minimizing nickle silicide that the present invention the proposes detailed step to the method for the erosion of semiconductor device channel region is described.
With reference to Fig. 2 A-Fig. 2 E, wherein show minimizing nickle silicide that the present invention the proposes schematic cross sectional view to each step of the method for the erosion of semiconductor device channel region.
First, as shown in Figure 2 A, provide Semiconductor substrate 200, the constituent material of described Semiconductor substrate 200 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, described Semiconductor substrate 200 selects single crystal silicon material to form.In described Semiconductor substrate 200, can also be formed with isolation channel, buried regions (not shown) etc.In addition, for nmos pass transistor, in described Semiconductor substrate 200, can also be formed with P trap (not shown), and before forming grid structure, can carry out once low dose of arsenic to whole P trap and inject, for adjusting the threshold voltage V of nmos pass transistor
th.
In described Semiconductor substrate 200, be formed with grid structure 201, as an example, described grid structure 201 can comprise gate dielectric, gate material layers and the grid hard masking layer stacking gradually from bottom to top.Gate dielectric can comprise oxide, as, silicon dioxide (SiO
2) layer.Gate material layers can comprise one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, and wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can comprise titanium nitride (TiN) layer; Conductive metal oxide layer can comprise yttrium oxide (IrO
2) layer; Metal silicide layer can comprise titanium silicide (TiSi) layer.Grid hard masking layer can comprise one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon, wherein, oxide skin(coating) can comprise boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride layer can comprise silicon nitride (Si
3n
4) layer; Oxynitride layer can comprise silicon oxynitride (SiON) layer; In the present embodiment, the material of grid hard masking layer is silicon nitride.
In addition,, as example, in described Semiconductor substrate 200, be also formed with and be positioned at described grid structure 201 both sides and near the side wall construction 204 of described grid structure 201.Wherein, described side wall construction 204 can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.In the present embodiment, described side wall construction 204 can be for controlling the distance of metal silicide and raceway groove, further to prevent that metal silicide and raceway groove are communicated with.
Next, to forming the region in 202He drain region, source region 203 in the Semiconductor substrate 200 of described grid structure 201 both sides, implement Implantation.Those skilled in the art can know, the concrete technology parameter of the described Implantation requirement that time expectation reaches according to designing semiconductor device and determining.
Then, as shown in Figure 2 B, in described Semiconductor substrate 200, form an insulating barrier 205, to fill the region of the top, region of the described enforcement Implantation that is positioned at described grid structure 201 both sides.The constituent material of described insulating barrier 205 comprises silicon dioxide (SiO
2), silicon nitride (SiN), amorphous carbon etc.The technology that adopts those skilled in the art to have the knack of forms described insulating barrier 205, for example, and chemical vapor deposition (CVD) or radio frequency plasma body chemical vapor phase growing (F-CVD).The thickness of described insulating barrier 205 is 10-1000nm.
Before forming described insulating barrier 205, can also in described Semiconductor substrate 200, form a stressor layers (do not give and illustrating in diagram), to cover the region of described grid structure 201 and described enforcement Implantation.The material of described stressor layers preferably has the silicon nitride of tension stress.
Then, as shown in Figure 2 C, grind described insulating barrier 205, make the surfacing of described insulating barrier 205.In the present embodiment, adopt described in cmp (CMP) process implementing and grind, described process of lapping is optional.
Next, carry out an annealing process, to activate the injection ion in the region of described enforcement Implantation.The tension stress that described annealing process can also make described stressor layers have is transferred in the channel region of described Semiconductor substrate 200.Because the thickness of described insulating barrier 205 is thicker, it can offset the edge effect of the described side wall construction being produced by the difference in height between described grid structure and described source/drain region, therefore, in described annealing process, in described Semiconductor substrate 200, there will not be the silicon crystal lattice dislocation boundary going out as shown in Figure 1B.
Described annealing process can be peak value annealing, samming annealing, laser annealing or flash lamp annealing.In the present embodiment, while adopting peak value annealing, annealing temperature is 300-1100 ℃; While adopting samming annealing, annealing temperature is 200-1100 ℃, and annealing time is 5s-5h; While adopting laser annealing or flash lamp annealing, annealing temperature is 500-1350 ℃, and annealing time is 0.1ms-1s.
Then, as shown in Figure 2 D, remove described insulating barrier 205.Described removal process can complete by the technology that adopts those skilled in the art to have the knack of, and at this, is no longer repeated.In above-mentioned removal process, the grid hard masking layer that is positioned at described grid structure 201 topmosts is also removed in the lump.
Then, as shown in Figure 2 E, at the top of described grid structure 201 and the surface in described source region 202 and described drain region 203 form nickel silicide layer 206.In the present embodiment, the processing step that forms described nickel silicide layer comprises: first remove the grid hard masking layer of the described grid structure 201Zhong the superiors, can adopt the prewashed method of wet method to complete this process; In Semiconductor substrate 200, form again metallic nickel (Ni) layer to cover top and described source region 202 and the described drain region 203 of described grid structure 201, the technique that forms described metallic nickel (Ni) layer can adopt method conventional in this area, for example, physical vaporous deposition or vapour deposition method etc.; Simultaneously; can on described metallic nickel (Ni) layer, form protective layer; the material of described protective layer is the nitride of refractory metal/refractory metal, Ti/TiN for example, and the effect of described protective layer is to avoid described metallic nickel (Ni) layer be exposed to the environment of non-inertia and be oxidized.
Then, described metallic nickel (Ni) layer is carried out to annealing in process, annealing process can be laser annealing, peak value annealing or samming annealing.Annealed processing, the nickel in metal level (Ni) spreads in the gate material layers of the silicon materials in described source region 202 and described drain region 203 and described grid structure 201, forms metallic nickel silicide with silicon or polysilicon wherein.
Next, remove the metal nickel dam not reacting.As example, by selectivity wet etching, remove less than the polysilicon in the gate material layers of the silicon with described source region 202 and described drain region 203 and described grid structure 201 and react the metallic nickel that generates metal silicide.The corrosive liquid of described wet etching can adopt the mixed solution of sulfuric acid and hydrogen peroxide (SPM); or the mixed solution of the aqueous solution of aqua ammonia and hydrogen peroxide (SC1) and phosphoric acid, nitric acid and formic acid (MII); in etching process, the protective layer on described metallic nickel (Ni) layer is also removed in the lump.Further, after described etching process stops, can carry out annealing in process for the second time to the metallic nickel silicide forming.
After annealing in process step completes, at surface and the top of described grid structure 201 in described source region 202 and described drain region 203, form nickel silicide layer 206.
So far, completed whole processing steps that method is implemented according to an exemplary embodiment of the present invention, the method proposing by the present invention, can stop the erosion of nickle silicide to semiconductor device channel region, thereby improves the rate of finished products that semiconductor device is manufactured.
Next, can by subsequent technique, complete the making of whole semiconductor device, described subsequent technique is identical with traditional process for fabricating semiconductor device.Those skilled in the art can know, and the method that the present invention proposes is equally applicable to PMOS transistor, only the material with tension stress that forms described stressor layers need to be replaced with to the material with compression.
With reference to Fig. 3, wherein show minimizing nickle silicide that the present invention the proposes flow chart to the method for the erosion of semiconductor device channel region, for schematically illustrating the flow process of whole manufacturing process.
In step 301, Semiconductor substrate is provided, in described Semiconductor substrate, be formed with grid structure, and in described Semiconductor substrate, be formed with and be positioned at described grid structure both sides and near the side wall construction of described grid structure;
In step 302, to forming the region in source region and drain region in the Semiconductor substrate of described grid structure both sides, implement Implantation;
In step 303, in described Semiconductor substrate, form an insulating barrier, to fill the region of the top, region of the described enforcement Implantation that is positioned at described grid structure both sides;
In step 304, carry out an annealing process, to activate the injection ion in the region of described enforcement Implantation;
In step 305, remove described insulating barrier;
In step 306, at the top of described grid structure and the surface in described source region and described drain region form nickel silicide layer.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure, and in described Semiconductor substrate, be formed with and be positioned at described grid structure both sides and near the side wall construction of described grid structure;
To forming the region in source region and drain region in the Semiconductor substrate of described grid structure both sides, implement Implantation;
In described Semiconductor substrate, form an insulating barrier, to fill the region of the top, region of the described enforcement Implantation that is positioned at described grid structure both sides;
Carry out an annealing process, to activate the injection ion in the region of described enforcement Implantation;
Remove described insulating barrier; And
At the top of described grid structure and the surface in described source region and described drain region form nickel silicide layer,
Wherein, described insulating barrier is offset the edge effect of the described side wall construction being produced by the difference in height between described grid structure and described source/drain region, in described annealing process, in the Semiconductor substrate of described side wall construction below, can not form silicon crystal lattice dislocation boundary.
2. method according to claim 1, is characterized in that, the constituent material of described insulating barrier comprises silicon dioxide, silicon nitride or amorphous carbon.
3. method according to claim 1, is characterized in that, adopts chemical vapor deposition method or radio frequency plasma chemical vapor deposition method to form described insulating barrier.
4. method according to claim 1, is characterized in that, the thickness of described insulating barrier is 10-1000nm.
5. method according to claim 1, is characterized in that, described annealing process is peak value annealing, samming annealing, laser annealing or flash lamp annealing.
6. method according to claim 5, is characterized in that, while adopting described peak value annealing, annealing temperature is 300-1100 ℃.
7. method according to claim 5, is characterized in that, while adopting described samming annealing, annealing temperature is 200-1100 ℃, and annealing time is 5s-5h.
8. method according to claim 5, is characterized in that, while adopting described laser annealing or described flash lamp annealing, annealing temperature is 500-1350 ℃, and annealing time is 0.1ms-1s.
9. method according to claim 1, is characterized in that, before forming described insulating barrier, is also included in the step that forms a stressor layers in described Semiconductor substrate, to cover the region of described grid structure and described enforcement Implantation.
10. method according to claim 1, is characterized in that, before carrying out described annealing process, also comprises the step of grinding described insulating barrier, makes the surfacing of described insulating barrier.
11. methods according to claim 1, is characterized in that, described grid structure comprises gate dielectric, gate material layers and the grid hard masking layer stacking gradually.
12. methods according to claim 11, is characterized in that, in removing the process of described insulating barrier, described grid hard masking layer is removed in the lump.
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| CN1719610A (en) * | 2004-07-08 | 2006-01-11 | 富士通株式会社 | Semiconductor device and CMOS integrated circuit (IC)-components |
| CN1933181A (en) * | 2005-09-15 | 2007-03-21 | 东部电子株式会社 | Semiconductor device and method of fabricating semiconductor device |
| CN101064254A (en) * | 2006-04-30 | 2007-10-31 | 联华电子股份有限公司 | Method for producing compressive nitrifier layer and method for forming transistor |
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| JPH0474439A (en) * | 1990-07-16 | 1992-03-09 | Matsushita Electron Corp | Mos transistor and its manufacture |
| CN1719610A (en) * | 2004-07-08 | 2006-01-11 | 富士通株式会社 | Semiconductor device and CMOS integrated circuit (IC)-components |
| CN1933181A (en) * | 2005-09-15 | 2007-03-21 | 东部电子株式会社 | Semiconductor device and method of fabricating semiconductor device |
| CN101064254A (en) * | 2006-04-30 | 2007-10-31 | 联华电子股份有限公司 | Method for producing compressive nitrifier layer and method for forming transistor |
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