CN103593321A - Dual-core PLC (programmable logic controller) system supporting instruction extension of functional blocks of ladder diagram - Google Patents
Dual-core PLC (programmable logic controller) system supporting instruction extension of functional blocks of ladder diagram Download PDFInfo
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- CN103593321A CN103593321A CN201310485344.1A CN201310485344A CN103593321A CN 103593321 A CN103593321 A CN 103593321A CN 201310485344 A CN201310485344 A CN 201310485344A CN 103593321 A CN103593321 A CN 103593321A
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Abstract
Disclosed is a dual-core PLC (programmable logic controller) system supporting instruction extension of functional blocks of a ladder diagram. An instruction extension module, an input module, an instruction analysis module and an output module are arranged in a universal processor; a special ladder diagram processor transmits current instructions of the functional blocks of the ladder diagram to the universal processor and the instruction extension module; the instruction extension module receives the instructions of the functional blocks of the ladder diagram, extends the instructions of the functional blocks of the ladder diagram and transmits the extended instructions to the instruction analysis module; a user transmits the register address of shared data required for corresponding functions of functional block numbers in the instructions of the functional blocks of the ladder diagram and the initial address of shared data blocks to the instruction extension module by using the universal processor; the special ladder diagram processor transmits at least one channel of electric signals to the input module; the input module converts the received electric signals into control signals; and the instruction analysis module analyzes and carries out the received instructions according to the control signals, invokes corresponding application programs in the universal processor, and inputs results of the application programs to the special ladder diagram processor through the output module.
Description
Technical field
The present invention relates to a kind of double-core PLC system of supporting ladder diagram functional block instruction extension, belong to Industry Control application specific processor design field.
Background technology
The elementary cell of PLC exploitation comprises two kinds of primary element and functional modules, and elementary cell is used for representing the state of switch, coil, and functional module is used for realizing specific control function.Because the PLC product of external import is not to survey and send out control and require to design towards space flight, it is mainly in order to meet industry spot application, functions such as Timer Controlling, data-moving, simple data computing that its functional module arranges.Increase along with guided missile/rocket launch vehicle measurement controlled device function complexity, as the Based Intelligent Control of the closed-loop control for analog quantity, digital quantity, complicated algorithm control etc., the program design of the trapezoid figure language of tradition based on elementary instruction cannot meet the demands, must expand existing ladder diagram instruction, to meet complex control technical development demand.
In existing space missile/rocket launch vehicle measurement, for realizing for the closed-loop control of analog quantity, the Based Intelligent Control of digital quantity, complicated algorithm control etc. are controlled function, be merely able to complete by an other central computer, this has greatly improved the complicacy of system.
In order to meet, guided missile/rocket launch vehicle measurement is integrated, miniaturization, production domesticization requirement, adopts SPARC V8 and ladder diagram application specific processor, and the core circuit that makes the whole survey based on PLC controller send out control designs realization in a SOC chip.Ladder diagram application specific processor adopts hardware to realize the read-write of primary element state and ladder diagram topological structure is resolved and controls function, the speed of comparing the execution of ladder diagram application program with software mode significantly promotes, but current SOC chip does not possess complex control ability, need equally an other central computer to complete the parsing and execution function of these complex control instructions.Due to SOC integrated chip SPARC V8 general processor, the ability that has possessed complex control computing, by the ladder diagram instruction to ladder diagram application specific processor, expand, can realize in PLC inside the parsing and execution function of complex control instruction, greatly reduce the complicacy of system.Because ladder diagram application specific processor is 16 bit processors, its instruction space is limited, cannot meet complex control requirement, therefore need on the basis that guarantees original instruction compatibility, to instruction, expand.
Summary of the invention
Technology of the present invention is dealt with problems and is: the deficiency that overcomes present technology, a kind of double-core PLC system of supporting ladder diagram functional block instruction extension is provided, this system can solve the limited problem of the existing Dinuclear Systems instruction space, by instruction extension, meets complex control requirement.
Technical solution of the present invention is: a kind of double-core PLC system of supporting ladder diagram functional block instruction extension, comprises ladder diagram application specific processor and general processor; In general processor inside, instruction extension module, load module, command analysis module and output module are set;
Ladder diagram application specific processor is sent to general processor and instruction extension module by the instruction of current ladder diagram functional block; Described ladder diagram functional block instruction comprises function build, instruction word size and functional block number;
Instruction extension module receives the ladder diagram functional block instruction of ladder diagram application specific processor input, and it is expanded, and in the instruction receiving, increases extended instruction, and the instruction after expansion is sent to command analysis module; Described extended instruction comprises functional block constant, functional block register, functional block pointer; Functional block constant is for storing the initial value of current functional block corresponding function, and functional block register is for storing the register address of each ladder diagram functional block instruction data sharing; The start address of functional block pointer for storing each ladder diagram functional block instruction data sharing piece;
The start address of the register address of the shared data that user needs functional block corresponding function in the instruction of current ladder diagram functional block by general processor, shared data block is sent to instruction extension module;
Ladder diagram application specific processor sends at least one road electric signal to load module, and load module converts the electric signal of reception to control signal, and control signal is sent to command analysis module;
Command analysis module resolves and carries out the instruction receiving according to control signal, according to corresponding application program in instruction calls general processor, application program result is inputed to ladder diagram application specific processor by output module.
The performing step of described command analysis module parsing instruction is as follows:
(1) resolve the function build in instruction, according to function build, determine whether present instruction is functional block instruction, if not, ignore this instruction, wait for next time and resolving; Otherwise go to step (2);
(2) resolve instruction word size, according to all extended instructions corresponding to instruction word size reading command word size, according to the register address of the shared data in extended instruction, from general processor, read shared data, according to start address read block from general processor of sharing data block, the size of data block is determined by data corresponding to start address;
(3) analytical capabilities piece number calls corresponding functional block application program according to functional block number from general processor, and the input using all data that read in step (2) as described application program, carries out this application program, and the result obtaining is delivered to output module.
The present invention's beneficial effect is compared with prior art: the present invention is by design function piece extended instruction, on the original Dinuclear Systems instruction of compatibility basis, increased ladder diagram functional block extended instruction, in the constant situation of maintenance PLC ladder diagram application specific processor bit wide, by increase, process the module of complex control function, strengthened the function of PLC system, can simplify the complicacy of guided missile/rocket launch vehicle measurement, improve the reliability of whole system.
Accompanying drawing explanation
Fig. 1 is former launch vehicle measurement complex control function realization flow;
Fig. 2 is that instruction extension of the present invention is implemented block diagram
Fig. 3 is two pin function pieces and three-prong ladder diagram schematic functional block;
Fig. 4 is that high level triggers and rising edge triggering mode contrast schematic diagram;
Fig. 5 is typical ladder diagram complex control functional schematic.
Embodiment
Below in conjunction with drawings and Examples, the present invention is elaborated.As shown in Figure 1, tradition launch vehicle measurement is realized complex control function by PLC and two equipment of central computer, PLC equipment completes the parsing of basic switch instruction, coil instruction, central computer carries out complicated arbitration functions according to system switching and coil state, and drives the corresponding switch of PLC equipment and coil.The present invention as shown in Figure 2, by existing double-core PLC system directive expand, by increasing PLC ladder diagram functional block extended instruction, by equipment of PLC, can realize guided missile/rocket launch vehicle measurement complex control function.
System of the present invention forms as shown in Figure 2, and instruction extension module, extended instruction parsing module, load module and output module are set in general processor inside; Expansion ladder diagram application specific processor is processed the ability of complex control instruction.
1. extended instruction definition
Ladder diagram functional block instruction definition is as shown in the table, and D15 represents the instruction of 16 ladder diagram application specific processors from high in the end to D0, and for functional block instruction, the value of D15～D12 is 1110, represents that this instruction is functional block instruction, and 1110 is exactly the head of functional block instruction.D11Dao D9 presentation directives word size, comprises that ladder diagram instruction and ladder diagram extended instruction have several instructions.D7～D0 presentation function piece number, represents the numbering of 0～255 functional block, maximumly supports 256 functional blocks.D8 is extension bits.
Ladder diagram extended instruction is defined as follows shown in table, comprises functional block constant, functional block register, functional block pointer; Functional block constant is for storing the initial value of current functional block corresponding function, and D15～D14 position of its instruction is 00, shows that this instruction is functional block constant, the value representation constant value that D13～D0 is corresponding.Functional block register is for storing the register address of each ladder diagram functional block instruction data sharing, and D15～D14 position is 01, shows that this instruction is functional block register, and calculate by D13～D0 its address.The start address of functional block pointer for storing each ladder diagram functional block instruction data sharing piece, D15～D12 is 1000, shows that this instruction is functional block pointer, represents the start address of data block by D11～D0.
2. extended instruction analysis mode
As shown in Figure 2, double-core PLC system comprises general processor, ladder diagram application specific processor, load module, instruction extension module, extended instruction parsing module and output module totally 6 parts, and extended instruction is resolved and is mainly divided into the following steps:
1) ladder diagram application specific processor is sent to general processor and instruction extension module by the instruction of ladder diagram functional block; Described ladder diagram functional block instruction comprises function build, instruction word size and functional block number;
2) instruction extension module receives the ladder diagram functional block instruction of ladder diagram application specific processor input, and it is expanded, and in the instruction receiving, increases extended instruction; Described extended instruction comprises functional block constant, functional block register, functional block pointer; Functional block constant is for storing the initial value of current functional block corresponding function, and functional block register is for storing the register address of each ladder diagram functional block instruction data sharing; The start address of functional block pointer for storing each ladder diagram functional block instruction data sharing piece;
3) in the current ladder diagram functional block instruction that instruction extension module reception general processor sends, share the register address of data and be sent to instruction extension module, share the start address of data block, complete the initialization to extended instruction, and the instruction after expansion is sent to command analysis module;
4) PLC ladder diagram processor sends at least one road electric signal to load module, and load module converts the electric signal of reception to control signal, and control signal is sent to command analysis module.The quantity of electric signal depends on the number of pins of functional block in ladder diagram, and for example the schematic diagram of two pin function pieces and three-prong ladder diagram functional block as shown in Figure 3.Two pin function pieces receive two path signal, and three-prong functional block receives three road electric signal.Each road electric signal can be converted to a corresponding road control signal.Have high level mode and rising edge that electric signal is converted to control signal trigger two kinds of modes, and its schematic functional block as shown in Figure 4.For high level mode, it is 1 o'clock that load module receives this road electric signal, and control signal is output as 1, otherwise is output as 0.For rising edge triggering mode, input electrical signal is by 0 during to 1 conversion, and control signal is output as 1, otherwise is output as 0.
5) command analysis module resolves and carries out the instruction receiving according to control signal, according to corresponding application program in instruction calls general processor, application program result is inputed to PLC ladder diagram processor by output module.For control signal, generally the control signal of first input pin is defaulted as enabling signal, and the control model of second input pin is defaulted as reset signal, and all the other are User Defined signal.When enabling signal is 1, function is resolved and is carried out in enabled instruction; When reset signal is 1, the value of all registers is reset to original state.When User Defined signal is 1, according to difference in functionality piece, defined corresponding control function.
6) performing step of command analysis module parsing instruction is as follows:
(1) resolve the function build in instruction, according to function build, determine whether present instruction is functional block instruction, if not, ignore this instruction, wait for next time and resolving; Otherwise go to step (2);
(2) resolve instruction word size, according to all extended instructions corresponding to instruction word size reading command word size, according to the register address of the shared data in extended instruction, from general processor, read shared data, according to start address read block from general processor of sharing data block, the size of data block is determined by data corresponding to start address;
(3) analytical capabilities piece number calls corresponding functional block application program according to functional block number from general processor, and the input using all data that read in step (2) as described application program, carries out this application program, and the result obtaining is delivered to output module.
3. launch vehicle measurement delay test sequential functional block instruction extension example
As shown in Figure 5, this ladder diagram is the example of a time-delay relay continuity test.Functional block shown in figure is 0.01 second timer function piece, and the initial value of its timer is set to 10, namely the timer of a 100ms.When the switch that starts to test is conducting state, timer starts, and since 10 countdowns, when counting down to 0, conducting turns electrical relay, thereby has realized the function of a 100ms Delayed conducting.
Described in the 2nd joint, time-delay relay continuity test comprises the following steps:
1) ladder diagram application specific processor is sent to general processor and instruction extension module by ladder diagram functional block instruction 0xE603;
The binary mode of 0xE603 is 0x1110011000000011, can find out function build (1110), instruction word size (011, namely 3) and functional block number (11) from ladder diagram functional block instruction definition;
2) instruction extension module receives the ladder diagram functional block instruction of ladder diagram application specific processor input, and it is expanded, and because instruction word size is 3, therefore need to expand 2 instructions again.Two extended instructions immediately after instruction extension module read functions piece, 0x48E7 and 0x000A.According to functional block extended instruction, definition can be found out, article one instruction is functional block register, and second instruction is functional block constant.The address of functional block register is 0x8E7, and the value that functional block constant is corresponding is 0xA(namely 10).
3) instruction extension module is calculated the register address of sharing data according to address 0x8E7, completes the initialization to extended instruction, and the instruction after expansion is sent to command analysis module;
4) PLC ladder diagram processor sends 2 road electric signal to load module, and load module converts the electric signal of reception to control signal, and control signal is sent to command analysis module.Two pin control signals are high level mode.For high level mode, it is 1 o'clock that load module receives this road electric signal, and control signal is output as 1, otherwise is output as 0.
5) command analysis module resolves and carries out the instruction receiving according to control signal, according to application program corresponding to timer in instruction calls general processor, application program result is inputed to PLC ladder diagram processor by output module.When first pin control signal is 1, start timer, otherwise timer quits work.When second pin signal is 1, reset timer, by initial value 0xA assignment to register corresponding to 0x8E7 address.
6) performing step of command analysis module parsing instruction is as follows:
(1) resolve the function build in instruction, according to function build (whether being 0xE), determine whether present instruction is functional block instruction, if not, ignore this instruction, wait for next time and resolving; Otherwise go to step (2);
(2) resolve instruction word size (0x3), according to all extended instructions corresponding to instruction word size reading command word size, according to the register address of the shared data in extended instruction, from general processor, read shared data;
(3) analytical capabilities piece number (0x3, corresponding is 0.01s timer), according to functional block number, from general processor, call the application program of timer, input using all data that read in step (2) as described application program, carry out this application program, the result obtaining is delivered to output module (turning electrical relay).
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (2)
1. a double-core PLC system of supporting ladder diagram functional block instruction extension, comprises ladder diagram application specific processor and general processor; It is characterized in that: in general processor inside, instruction extension module, load module, command analysis module and output module are set;
Ladder diagram application specific processor is sent to general processor and instruction extension module by the instruction of current ladder diagram functional block; Described ladder diagram functional block instruction comprises function build, instruction word size and functional block number;
Instruction extension module receives the ladder diagram functional block instruction of ladder diagram application specific processor input, and it is expanded, and in the instruction receiving, increases extended instruction, and the instruction after expansion is sent to command analysis module; Described extended instruction comprises functional block constant, functional block register, functional block pointer; Functional block constant is for storing the initial value of current functional block corresponding function, and functional block register is for storing the register address of each ladder diagram functional block instruction data sharing; The start address of functional block pointer for storing each ladder diagram functional block instruction data sharing piece;
The start address of the register address of the shared data that user needs functional block corresponding function in the instruction of current ladder diagram functional block by general processor, shared data block is sent to instruction extension module;
Ladder diagram application specific processor sends at least one road electric signal to load module, and load module converts the electric signal of reception to control signal, and control signal is sent to command analysis module;
Command analysis module resolves and carries out the instruction receiving according to control signal, according to corresponding application program in instruction calls general processor, application program result is inputed to ladder diagram application specific processor by output module.
2. a kind of double-core PLC system of supporting ladder diagram functional block instruction extension according to claim 1, is characterized in that: it is as follows that described command analysis module is resolved the performing step of instruction:
(1) resolve the function build in instruction, according to function build, determine whether present instruction is functional block instruction, if not, ignore this instruction, wait for next time and resolving; Otherwise go to step (2);
(2) resolve instruction word size, according to all extended instructions corresponding to instruction word size reading command word size, according to the register address of the shared data in extended instruction, from general processor, read shared data, according to start address read block from general processor of sharing data block, the size of data block is determined by data corresponding to start address;
(3) analytical capabilities piece number calls corresponding functional block application program according to functional block number from general processor, and the input using all data that read in step (2) as described application program, carries out this application program, and the result obtaining is delivered to output module.
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