CN112379635B - PLC ladder diagram analysis method and device, electronic equipment and readable storage medium - Google Patents
PLC ladder diagram analysis method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The invention discloses a PLC ladder diagram analysis method, a PLC ladder diagram analysis device, electronic equipment and a readable storage medium, wherein the method comprises the following steps: the method comprises the steps of obtaining a ladder diagram code instruction from an upper computer, reconstructing the ladder diagram code instruction according to the structures of a network, a column and a node to obtain a reconstructed code, and analyzing the reconstructed code according to the structures of the network, the column and the node, wherein the network comprises at least one column, and the column comprises at least one node. According to the invention, the structure conversion is firstly carried out on the ladder diagram code to obtain the reconstruction code, and then the reconstruction code is analyzed to improve the analysis speed. The reconstruction code is of a linear structure, the simple structure greatly reduces the difficulty of analysis, and the method can be applied to complex PLC programs.
Description
Technical Field
The invention relates to the field of programmable logic control, in particular to a PLC ladder diagram analysis method, a PLC ladder diagram analysis device, electronic equipment and a readable storage medium.
Background
The ladder diagram is the most common programming language for a Programmable Logic Controller (PLC), which is simple, clear and easy to understand, but the PLC cannot directly recognize the ladder diagram language, and therefore, the ladder diagram is to be converted into an instruction that can be recognized by the PLC. And analyzing the converted instruction when the PLC operates, thereby controlling the output of the PLC. However, the conventional PLC analysis method has the problems of complex description of the ladder diagram structure and complex algorithm for converting the ladder diagram into the tree data structure. Most of the current common PLC analysis methods adopt a method of directly analyzing ladder diagram instructions downloaded into the PLC, and when the ladder diagram of the PLC is complex, the analysis efficiency is greatly reduced.
Therefore, how to improve the accuracy and the efficiency of the ladder diagram analysis becomes an important point for those skilled in the art to solve the technical problem and research.
Disclosure of Invention
In view of this, embodiments of the present invention provide a PLC ladder diagram analysis method, an apparatus, an electronic device, and a readable storage medium, so as to solve the problems of low efficiency, low accuracy, and complex analysis process of the PLC ladder diagram analysis method in the prior art.
Therefore, the embodiment of the invention provides the following technical scheme:
in a first aspect of the present invention, a PLC ladder diagram analysis method is provided, including:
acquiring a ladder diagram code instruction from an upper computer;
reconstructing the ladder diagram code instruction according to the structures of networks, columns and nodes to obtain a reconstructed code;
analyzing the reconstruction codes according to the structures of the network, the columns and the nodes;
wherein the network comprises at least one column comprising at least one node.
Further, reconstructing the ladder code instructions according to the structure of the network, the columns and the nodes comprises:
setting the number of networks to 0;
executing the following steps on each sub-code in the ladder diagram code instruction in sequence:
judging whether the current subcode is an end code or not to obtain a first judgment result;
if the first judgment result is yes, finishing the reconstruction of the ladder diagram code instruction;
if the first judgment result is negative, judging whether the current subcode is a network start code to obtain a second judgment result;
if the second judgment result is yes, adding one to the number of the networks, applying for an address to store the current network, and setting the number of the columns of the current network to be 0;
if the second judgment result is negative, judging whether the current subcode is a column start code or not to obtain a third judgment result;
and if the third judgment result is yes, adding one to the number of the current network columns, and acquiring and storing the node information of the current network columns according to the current subcodes.
Further, parsing the reconfiguration code includes:
acquiring the order of analyzing each network in the reconstruction codes according to the number of the networks;
and analyzing each corresponding column of each network in turn according to the column number of each network.
Further, the node information includes connection relationships between rows;
analyzing the current column of the current network comprises analyzing each node of the current column in sequence to obtain the output of each node of the current column;
and obtaining the output of the current column according to the connection relation between the output of each node of the current column and the row of the current column.
Further, the node information also comprises the type of the node and the storage address of the variable data;
parsing the current node of the current column includes:
taking the output state of the previous column as the input state of the current column;
and obtaining the output of the current node according to the input state of the current column, the type of the current node and the storage address of the variable data of the current node.
Further, before analyzing the current network, judging whether the current network is highlighted or not to obtain a fourth judgment result;
and if the fourth judgment result is yes, storing the analysis result of the current network in the highlight array.
In a second aspect of the present invention, there is provided a PLC ladder diagram analysis device, including:
the communication module is used for acquiring ladder diagram code instructions from an upper computer;
the format conversion module is used for reconstructing the ladder diagram code instruction according to the structures of networks, columns and nodes to obtain a reconstruction code;
the analysis module is used for analyzing the reconstruction codes according to the structures of the network, the column and the node;
wherein the network comprises at least one column comprising at least one node.
Further, the format conversion module includes:
a first counting unit for setting the number of networks to 0;
a first obtaining unit, configured to sequentially obtain each sub-code in the ladder diagram code instruction:
the first judgment unit is used for judging whether the current subcode is an end code or not to obtain a first judgment result, and if the first judgment result is yes, the reconstruction of the ladder diagram code instruction is ended;
the second judgment unit is used for judging whether the current subcode is a network start code or not to obtain a second judgment result if the first judgment result is negative, and applying for an address to store the current network if the second judgment result is positive; the first counting unit increases the number of networks by one;
the second counting unit is used for setting the column number of the current network to be 0;
a third judging unit, if the second judgment result is negative, the third judging unit is configured to judge whether the current subcode is a column start code to obtain a third judgment result, and if the third judgment result is positive, the third judging unit acquires and stores node information of a current column of the current network according to the current subcode; the second counting unit increases the number of columns of the current network by one.
In a third aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to cause the at least one processor to perform the method of any one of the first aspects of the invention.
In a fourth aspect of the invention, there is provided a computer readable storage medium having stored thereon computer instructions which, when executed by a processor, carry out the steps of the method according to any one of the first aspect of the invention.
The technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a PLC ladder diagram analysis method, a PLC ladder diagram analysis device, electronic equipment and a readable storage medium. The existing PLC trapezoidal graph analysis method has the problems of low analysis efficiency, complex analysis process and low accuracy. According to the invention, the structure conversion is firstly carried out on the ladder diagram code to obtain the reconstruction code, and then the reconstruction code is analyzed to improve the analysis speed. The reconstruction code is of a linear structure, the simple structure greatly reduces the difficulty of analysis, and the method can be applied to complex PLC programs.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a PLC ladder diagram analysis method according to an embodiment of the present invention;
FIG. 2 is a flow chart of reconstructing ladder code instructions according to the structure of networks, columns, and nodes according to an embodiment of the present invention;
FIG. 3 is a ladder diagram of a PLC according to an embodiment of the present invention;
FIG. 4 is a block diagram of a PLC ladder diagram analysis device according to an embodiment of the present invention;
fig. 5 is a block diagram of a control software structure of a PLC ladder diagram analysis device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a terminal according to an alternative embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In accordance with an embodiment of the present invention, there is provided a PLC ladder diagram analysis method embodiment, it is noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a flowchart of a PLC ladder diagram analysis method according to an embodiment of the present invention. As shown in fig. 1, the PLC ladder diagram analysis method includes the steps of:
s1: and acquiring ladder diagram code instructions from an upper computer. In this embodiment, the upper computer converts the ladder diagram compiled by the user into ladder diagram code instructions that can be recognized when the PLC analyzes the ladder diagram according to the instruction set format of the PLC itself, and downloads the ladder diagram code instructions into the PLC.
S2: and reconstructing the ladder diagram code instruction according to the structures of the network, the column and the node to obtain a reconstructed code. In this embodiment, the PLC reconstructs an instruction downloaded from the upper computer in a vertical scanning manner according to a structure of a network- > column- > element node.
S3: and resolving the reconstructed codes according to the structures of the network, the columns and the nodes. In this embodiment, the analyzed result is transmitted to the input/output point of the PLC, and a corresponding action is executed or transmitted to the upper computer, and is displayed by the upper computer.
In this embodiment, the number of networks is at least one, each network includes at least one column, and each column includes at least one node. The ladder code instructions include a network start code, a column start code, an element node code, and a program end code. The network start code is 0xF000, which represents the beginning of a ladder network, and the network has 7 rows and 11 columns; the column start code is the beginning of a column, the 13-15 bits of the column start code are 101, the column start code is characterized, the 7-12 bits represent the conduction relation between the rows of the column, and the 0-6 bits represent whether elements exist in the 1-7 rows or not; the element node code represents the type of the element node and the storage address of the variable data, wherein bits 13-15 are the element type, and bits 0-12 represent the storage address of the variable data.
Compared with the prior art, the method and the device have the advantages that the structure conversion is firstly carried out on the ladder diagram codes to obtain the reconstruction codes, and then the reconstruction codes are analyzed to improve the analysis speed. The reconstruction code is of a linear structure, the simple structure greatly reduces the difficulty of analysis, and the method can be applied to complex PLC programs.
Fig. 2 is a flowchart of reconstructing ladder code instructions according to the structure of networks, columns, and nodes according to an embodiment of the present invention. As shown in FIG. 2, in one embodiment, reconstructing the ladder code instructions according to the structure of the network, the columns and the nodes comprises the following steps:
s21: the number of networks is set to 0.
S22: the following steps are performed for each subcode in the ladder code instruction in turn.
S23: and judging whether the current subcode is an end code or not to obtain a first judgment result.
S24: if the first judgment result is yes, the reconstruction of the ladder code instruction is finished.
S25: and if not, judging whether the current subcode is the network start code to obtain a second judgment result.
S26: and if the second judgment result is yes, adding the number of the networks and applying the address to store the current network, and setting the number of the columns of the current network to be 0.
S27: if the second judgment result is negative, judging whether the current subcode is the column start code or not to obtain a third judgment result.
S28: and if so, adding the number of the current network columns and acquiring and storing the node information of the current network columns according to the current subcodes. In this embodiment, the node information of the current column is stored in the current address.
In this embodiment, if the third determination result is negative, the current subcode is stored in the current address.
In a particular embodiment, parsing the restructured codes includes parsing each network in the restructured codes in turn according to the number of networks. Analyzing the current network comprises analyzing each column of the current network in sequence according to the column number of the current network. The node information includes connection relationships between the rows. Analyzing the current column of the current network comprises analyzing each node of the current column in sequence to obtain the output of each node of the current column, and obtaining the output of the current column according to the connection relation between the output of each node of the current column and the row of the current column. The node information also includes the type of the node and the storage address of the variable data. Parsing the current node of the current column includes. And taking the output state of the previous column as the input state of the current column. And obtaining the output of the current node according to the input state of the current column, the type of the current node and the storage address of the variable data of the current node.
In this embodiment, before analyzing the current network, it is further determined whether the current network is highlighted, so as to obtain a fourth determination result. And if the fourth judgment result is yes, storing the analysis result of the current network in the highlight array.
Fig. 3 is a ladder diagram of a PLC according to an embodiment of the present invention. The PLC ladder diagram analysis method according to the embodiment of the present invention will now be described with reference to the ladder diagram shown in fig. 3.
The ladder contains two nets, net 0 and net 1. 10001 and 10003 of network 0 represent normally open nodes, 10002 represents normally closed nodes, 00001 represents the output coil, and network 1 is empty. The ladder diagram code instruction received by the PLC from the upper computer is 0xF 0000 xA 0830 x 00000 x 00020 xA 0010 x 20010 xA 0010 x 88000 xF 0000 xA 0000 xE2FF, and the ladder diagram obtained from the instruction code includes two networks in total, where:
network 0:
0xF000 0xA083 0x0000 0x0002 0xA001 0x2001 0xA001 0x8800
network 1:
0xF000 0xA000
when the PLC starts to operate, the downloaded ladder diagram code instruction is reconstructed according to a specific data structure so as to be analyzed subsequently. Firstly, taking out a first subcode, judging whether the first subcode is a network initial code, if so, applying an address to store the network, adding 1 to the number of the networks, and taking down the subcode; otherwise, ending. Before the next network start code is not taken, adding 1 to the number of columns of the network every time a column start code is taken, then acquiring the existence state of nodes in each row and the connection relation between rows according to the column start code, wherein, for example, 0xA083, 6-0 bit "0000011" represents that a first row and a second row exist elements, 12-7 bit "000001" represents that a first row and a second row exist or relation, and storing the node information until the next network start code or end code is taken. Wherein the node information includes a connection relationship between the rows. The connection relationship between the rows is an "or relationship". And repeating the operation after the second network start code is taken until the end code 0xE2FF is taken, ending the conversion and informing the PLC to start the analysis.
PLC code storage format is divided into
| Number of networks | Network node pointer |
| NetNumber | pNetWork |
Dao_Ladder_Struct
NetWork
| Or relationship | Element node |
| OR | pCmd |
Column
And analyzing each network in turn according to the number of the stored networks, and analyzing each column in turn according to the number of columns stored in the network when analyzing the network.
1. 0x0000 of the first row is taken out, and the normally open switch is judged according to the bits 13-15. And obtaining the storage address of the variable data according to the 0-12 bits of the variable data, taking out whether the switch state is conducted or not, and combining the switch state with the output of the previous column of the current node to obtain the output of the current node.
2. 0x0002 of the second row is taken out and the 1 step operation is repeated.
3. And after all row node outputs are obtained, obtaining the column output according to the OR relation.
4. After the first column is finished, 0x2001 of the second column is taken out, and the above operation is repeated to obtain the output of the present column.
5. And taking out 0x8800 in the last column, judging the coil according to 13-15 bits, obtaining a storage address of variable data according to 0-12 bits of the coil, taking out whether the switch state is conducted, combining the switch state with the output of the previous column of the current node to obtain the output of the current node, and finishing the current network analysis.
6. The next network is analyzed, and the number of columns is found to be 0, and the analysis is stopped. This ladder diagram analysis is finished.
In a specific embodiment, the upper computer sends a highlighted network number to the PLC. And after receiving the highlighted network number, the PLC sets the network start to be 0 xFFFF. In the analysis process, if the network is highlighted (0xFFFF) initially, the conducting state of each node in each column in the network is stored in a highlight array and transmitted to an upper computer, and highlight display is achieved.
In this embodiment, a PLC ladder diagram analysis device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and the description of the device is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 4 is a block diagram of a PLC ladder diagram analysis apparatus according to an embodiment of the present invention, and as shown in fig. 4, the apparatus includes: and the communication module 1 is used for acquiring ladder diagram code instructions from an upper computer. And the format conversion module 2 is used for reconstructing the ladder diagram code instruction according to the structures of the network, the column and the node to obtain a reconstructed code. And the analysis module 3 is used for analyzing the reconstructed codes according to the structures of the network, the columns and the nodes. Wherein the network comprises at least one column comprising at least one node.
In a specific embodiment, the format conversion module 2 includes: a first counting unit for setting the number of networks to 0. And the first acquisition unit is used for sequentially acquiring each sub-code in the ladder diagram code instruction. And the first judgment unit is used for judging whether the current subcode is the end code to obtain a first judgment result, and if the first judgment result is yes, finishing the reconstruction of the ladder diagram code instruction. The second judgment unit is used for judging whether the current subcode is the network start code or not to obtain a second judgment result if the first judgment result is negative, and the application address is stored in the current network if the second judgment result is positive; the first counting unit increments the number of networks by one. And the second counting unit is used for setting the column number of the current network to be 0. A third judging unit, if the second judging result is negative, the third judging unit is used for judging whether the current subcode is the column start code to obtain a third judging result, if the third judging result is positive, the node information of the current column of the current network is obtained and stored according to the current subcode; the second counting unit increases the number of columns of the current network by one.
Fig. 5 is a block diagram of a control software structure of the PLC ladder diagram analysis device according to the embodiment of the present invention. In one particular embodiment, as shown in FIG. 5, the software consists of a communication module, a parsing module and a control module. The communication module is used for realizing interaction between the upper computer and the lower computer, and after the lower computer receives the instruction of the upper computer, the lower computer calls a related operation function according to the type of the instruction, and the functions of the communication module mainly comprise read-write system configuration, uploading and downloading of ladder diagram codes, setting and reading element states, setting and obtaining high brightness and the like. And the analysis module reconstructs the ladder diagram code instruction downloaded into the PLC according to a specific data structure and analyzes the data structure in the scanning process so as to obtain corresponding output. And the control module executes corresponding operation according to the analysis result of the analysis module in the scanning process, so that the operation control of the PLC is realized. The operation of the PLC controller is divided into off-line operation and on-line operation. When the controller Flash runs off line, if the controller Flash has ladder diagram codes, calling an analysis module to convert the ladder diagram codes into a specific data structure, analyzing the ladder diagram codes in scanning, and calling a control module to execute corresponding operation according to an analysis result after the analysis is finished; otherwise, no operation is performed. When the PLC works on line, besides the work, the PLC still needs to interact with the upper computer in real time, and corresponding operation is carried out according to instructions of the upper computer, so that the control and display functions of the PLC by the upper computer are realized.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a terminal according to an alternative embodiment of the present invention, and as shown in fig. 6, the terminal may include: at least one processor 601, such as a CPU (Central Processing Unit), at least one communication interface 603, memory 604, and at least one communication bus 602. Wherein a communication bus 602 is used to enable the connection communication between these components. The communication interface 603 may include a Display (Display) and a Keyboard (Keyboard), and the optional communication interface 603 may also include a standard wired interface and a standard wireless interface. The Memory 604 may be a high-speed RAM (Random Access Memory) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The memory 604 may optionally be at least one storage device located remotely from the processor 601. Wherein the processor 601 may be combined with the apparatus described in fig. 4, the memory 604 stores an application program, and the processor 601 calls the program code stored in the memory 604 for performing any of the above method steps, i.e. for performing the following:
and acquiring ladder diagram code instructions from an upper computer. And reconstructing the ladder diagram code instruction according to the structures of the network, the column and the node to obtain a reconstructed code. And resolving the reconstructed codes according to the structures of the network, the columns and the nodes. Wherein the network comprises at least one column comprising at least one node.
In the embodiment of the present invention, the processor 601 calls the program code in the memory 604, and is further configured to perform the following operations:
the number of networks is set to 0. The following steps are performed for each subcode in the ladder code instruction in turn. And judging whether the current subcode is an end code or not to obtain a first judgment result. If the first judgment result is yes, the reconstruction of the ladder code instruction is finished. If the first judgment result is negative, judging whether the current subcode is the network start code or not to obtain a second judgment result. And if the second judgment result is yes, adding one to the number of the networks, applying for an address to store the current network, and setting the number of the columns of the current network to be 0. If the second judgment result is negative, judging whether the current subcode is the column start code or not to obtain a third judgment result. And if so, adding one to the number of the current network columns, and acquiring and storing the node information of the current network columns according to the current subcodes.
In the embodiment of the present invention, the processor 601 calls the program code in the memory 604, and is further configured to perform the following operations:
and acquiring the order of analyzing each network in the reconstruction codes according to the number of the networks. And analyzing each corresponding column of each network in turn according to the column number of each network.
In the embodiment of the present invention, the processor 601 calls the program code in the memory 604, and is further configured to perform the following operations:
analyzing the current column of the current network comprises analyzing each node of the current column in sequence to obtain the output of each node of the current column. And obtaining the output of the current column according to the connection relation between the output of each node of the current column and the row of the current column.
In the embodiment of the present invention, the processor 601 calls the program code in the memory 604, and may further perform the following operations:
parsing the current node of the current column includes:
taking the output state of the previous column as the input state of the current column;
and obtaining the output of the current node according to the input state of the current column, the type of the current node and the storage address of the variable data of the current node.
The communication bus 602 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 602 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 6, but this is not intended to represent only one bus or type of bus.
The memory 604 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated: HDD) or a solid-state drive (english: SSD); the memory 604 may also comprise a combination of the above types of memory.
The processor 601 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP.
The processor 601 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
Optionally, the memory 604 is also used for storing program instructions. Processor 601 may invoke program instructions to implement a PLC ladder diagram parsing method as shown in the embodiments of fig. 1 and 2 of the present application.
The embodiment of the invention also provides a non-transitory computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions can execute the PLC trapezoidal graph analysis method in any method embodiment. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD) or a Solid State Drive (SSD), etc.; the storage medium may also comprise a combination of memories of the kind described above.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (5)
1. A PLC ladder diagram question method is characterized by comprising the following steps:
acquiring a ladder diagram code instruction from an upper computer;
reconstructing the ladder diagram code instruction according to the structures of networks, columns and nodes to obtain a reconstruction code, wherein the reconstruction code at least comprises the network number, the column number and the node information;
analyzing the reconstruction codes according to the structures of the network, the columns and the nodes;
wherein the network comprises at least one column, the column comprising at least one node;
reconstructing the ladder diagram code instruction according to the structure of the network, the columns and the nodes comprises the following steps:
setting the number of networks to 0;
executing the following steps on each sub-code in the ladder diagram code instruction in sequence:
judging whether the current subcode is an end code or not to obtain a first judgment result;
if the first judgment result is yes, finishing the reconstruction of the ladder diagram code instruction;
if the first judgment result is negative, judging whether the current subcode is a network start code to obtain a second judgment result;
if the second judgment result is yes, adding one to the number of the networks, applying for an address to store the current network, and setting the number of the columns of the current network to be 0;
if the second judgment result is negative, judging whether the current subcode is a column start code or not to obtain a third judgment result;
if the third judgment result is yes, adding one to the number of the current network columns, and acquiring and storing node information of the current network columns according to the current subcodes, wherein the node information comprises the connection relation among the rows, the type of the nodes and the storage address of the variable data;
parsing the reconstruction code comprises: acquiring the order of analyzing each network in the reconstruction codes according to the number of the networks;
analyzing each corresponding column of each network in sequence according to the column number of each network;
analyzing the current column of the current network comprises analyzing each node of the current column in sequence to obtain the output of each node of the current column;
obtaining the output of the current column according to the connection relation between the output of each node of the current column and the row of the current column;
parsing the current node of the current column includes:
taking the output state of the previous column as the input state of the current column;
and obtaining the output of the current node according to the input state of the current column, the type of the current node and the storage address of the variable data of the current node.
2. The PLC ladder diagram question method of claim 1, further comprising determining whether the current network is highlighted before parsing the current network to obtain a fourth determination result;
and if the fourth judgment result is yes, storing the analysis result of the current network in the highlight array.
3. A PLC ladder diagram problem solving device is characterized by comprising:
the communication module is used for acquiring ladder diagram code instructions from an upper computer;
the format conversion module is used for reconstructing the ladder diagram code instruction according to the structures of networks, columns and nodes to obtain a reconstruction code, and the reconstruction code at least comprises the network number, the column number and the node information;
the analysis module is used for analyzing the reconstruction codes according to the structures of the network, the column and the node; parsing the reconfiguration code includes obtaining an order of parsing each network in the reconfiguration code according to the number of networks; analyzing each corresponding column of each network in sequence according to the column number of each network, wherein analyzing the current column of the current network comprises analyzing each node of the current column in sequence to obtain the output of each node of the current column;
obtaining the output of the current column according to the connection relation between the output of each node of the current column and the row of the current column, and analyzing the current node of the current column comprises:
taking the output state of the previous column as the input state of the current column;
obtaining the output of the current node according to the input state of the current column, the type of the current node and the storage address of the variable data of the current node;
wherein the network comprises at least one column, the column comprising at least one node;
the format conversion module comprises:
a first counting unit for setting the number of networks to 0;
a first obtaining unit, configured to sequentially obtain each sub-code in the ladder diagram code instruction:
the first judgment unit is used for judging whether the current subcode is an end code or not to obtain a first judgment result, and if the first judgment result is yes, the reconstruction of the ladder diagram code instruction is ended;
the second judgment unit is used for judging whether the current subcode is a network start code or not to obtain a second judgment result if the first judgment result is negative, and applying for an address to store the current network if the second judgment result is positive; the first counting unit increases the number of networks by one;
the second counting unit is used for setting the column number of the current network to be 0;
a third judging unit, if the second judgment result is negative, the third judging unit is configured to judge whether the current subcode is a column start code to obtain a third judgment result, if the third judgment result is positive, the third judging unit is configured to obtain and store node information of a current column of a current network according to the current subcode, where the node information includes a connection relationship between rows, a type of a node, and a storage address of variable data; the second counting unit increases the number of columns of the current network by one.
4. An electronic device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of any one of claims 1 and 2.
5. A computer-readable storage medium having stored thereon computer instructions, which when executed by a processor, perform the steps of the method of any of claims 1 and 2.
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