CN103592827B - The method removing the photoresist layer after high dose ion is injected - Google Patents
The method removing the photoresist layer after high dose ion is injected Download PDFInfo
- Publication number
- CN103592827B CN103592827B CN201210292492.7A CN201210292492A CN103592827B CN 103592827 B CN103592827 B CN 103592827B CN 201210292492 A CN201210292492 A CN 201210292492A CN 103592827 B CN103592827 B CN 103592827B
- Authority
- CN
- China
- Prior art keywords
- layer
- photoresist layer
- mask layer
- wet method
- wet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The present invention discloses a kind of method removing the photoresist layer after high dose ion is injected, including step: sequentially form protective layer, mask layer and photoresist layer on a semiconductor substrate;Pattern described photoresist layer to define mask layer described in ion implanted regions expose portion;Wet method removes the mask layer of described exposure;Described substrate is performed ion implanting;Wet method removes the mask layer between protective layer and described photoresist layer to expose the interior zone of described photoresist layer further;Wet method removes described photoresist layer.The present invention can in a wet etching step the photoresist injected by high dose ion by its interior zone thorough removal, owing to eliminating in prior art the step of ashing in oxygen-containing atmosphere, so wafer will not be caused damage.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method removing the photoresist layer after high dose ion is injected.
Background technology
At present, integrated circuit can include about 1,000,000,000 devices on only tens device development each chip till now from each chip of the sixties, and why integrated circuit can develop rapidly, and the support of photoetching technique serves extremely crucial effect.Because it directly determines the physical size of single semiconductor device, therefore the level of photoetching technique has become as one of most important factor determining semiconductor device integrated level.
The basic technology of photoetching technique generally includes gluing, exposed and developed three big steps.The purpose of coating technique be wafer surface set up uniform and thin, do not have defective photoresist layer.Exposure is to be transferred on photoresist layer by the figure on photomask by Exposing Lamp or other radiating light sources.After exposure, device or circuitous pattern are to expose the form record with unexposed area on photoresist layer.The pattern of post-develop mask is secured on photoresist layer.
I.e. technique or ion implantation technology can be performed etching with photoresist layer for mask after photoetching process.
After wet etching, dry etching or ion implanting, the photoresist of wafer surface is required for removing.
Photoresist layer be one layer of organic matter layer its be frequently used for the manufacture of integrated circuit, it can use organic solvent, such as acetone, N-Methyl pyrrolidone (NMP) etc. to remove.But after the ion implantation process step of high dose, it is difficult to remove by above method.
Prior art also has the trial removed by the photoresist layer after the ion implanting step of high dose.Such as use oxygen-containing gas ashing photoresist layer and the method for wet etching.The chemical solvent that wherein wet etching is used includes the mixture (Sulfuric-peroxidemixture(SPM) of sulphuric acid and hydrogen peroxide) or NMP.But the surface of wafer can be damaged by oxygen-containing gas when removing photoresist by this method, additionally due to LDD region territory is in close proximity to the surface of wafer, so such infringement needs are avoided.
Also have and use the trial that there is the SPM solution of high volume ratio to remove the photoresist after the ion implanting of high dose.But photoresist layer is removed the longest, the highest reaction temperature of needs and produces little effect by the method.So needing a kind of method photoresist after high dose ion is injected thoroughly can removed.
Summary of the invention
In view of problem above, the present invention provides a kind of method removing the photoresist layer after high dose ion is injected, including step: a) sequentially form protective layer, mask layer and photoresist layer on a semiconductor substrate;B) described photoresist layer is patterned to define mask layer described in ion implanted regions expose portion;C) wet method removes the mask layer of described exposure;D) described substrate is performed ion implanting;E) wet method removes the mask layer between protective layer and described photoresist layer to expose the interior zone of described photoresist layer further;F) wet method removes described photoresist layer.
Further, it is characterised in that use nitride to form described protective layer,
Further, it is characterised in that the protective layer of described formation has thickness 10-20 angstrom.
Further, it is characterised in that use oxide to form described mask layer,
Further, it is characterised in that the method for described formation mask layer is LTCVD,
Further, it is characterised in that the mask layer of described formation has thickness 200-300 angstrom.
Further, it is characterised in that use DHF to perform the wet method of mask layer in step c) and step e) and remove.
Further, it is characterised in that step c) uses 100:1DHF.
Further, it is characterised in that using 300:1DHF in step e), the response time is 40 seconds.
Further, it is characterised in that using SPM to perform the wet method of photoresist layer in step f) and remove, reaction temperature is 125 degrees Celsius.
Further, it is characterised in that after being additionally included in step f), wet method removes described mask layer and described protective layer.
Further, it is characterised in that after using H3PO4 to perform step f), the wet method of mask layer is removed, and reaction temperature is 160 degrees Celsius.
Further, it is characterised in that after using DHF to perform described step f), the wet method of protective layer is removed.
Further, it is characterised in that described wet method is removed and carried out in same wet process board.
The present invention can in a wet etching step the photoresist injected by high dose ion by its interior zone thorough removal, owing to eliminating in prior art the step of ashing in oxygen-containing atmosphere, so wafer will not be caused damage.
The present invention also has and can perform multiple steps that described wet etching and wet method remove under relatively low temperature conditions and perform in a wet process board thus the advantage that reduces carrying wafers number of times.
Accompanying drawing explanation
Fig. 1-4 is the device profile map of each processing step of the present invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It will be apparent, however, to one skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to illustrate that the present invention is the most effectively to remove the photoresist layer and not hurtful to wafer surface after high dose ion is injected.Obviously, the execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.The better embodiment of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Should be understood that, when using term " to comprise " in this manual and/or time " including ", it indicates and there is described feature, entirety, step, operation, element and/or assembly, but do not preclude the presence or addition of other features one or more, entirety, step, operation, element, assembly and/or combinations thereof it follows that the present invention will be more fully described by conjunction with accompanying drawing
With reference to Fig. 1.Semiconductor substrate 200 is provided, described substrate can be at least one in the following material being previously mentioned: stacking SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacking silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator, doped region and/or isolation structure can be had in described substrate, described isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure etc., omits in figure.Sequentially form protective layer 201 and the mask layer 202 with stack architecture the most over the substrate.Wherein can be by including chemical vapour deposition technique (CVD); such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD); being used as general similarity method such as such as sputter and physical vapour deposition (PVD) (PVD) etc. uses SiN to form this protective layer 201; preferably using low temperature chemical vapor deposition (LTCVD) to be formed, it can have the thickness of 10-20 angstrom.Can be by including chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), being used as general similarity method such as such as sputter and physical vapour deposition (PVD) (PVD) etc. uses SiO2 to form this mask layer 202, preferably using low temperature chemical vapor deposition (LTCVD) to be formed, it can have the thickness of 200-300 angstrom.
Then at the upper formation photoresist layer 203 of mask layer.The step forming ARC (ARC) can also be included, i.e. can also be initially formed bottom antireflective coating (BARC) (not shown) on hard mask layer 202, TiN or SiN can be used to form BARC layer, form photoresist layer the most again on this BARC layer;Or be initially formed photoresist layer 203 on hard mask layer 202, then on this photoresist layer, form the step of top anti-reflection coating (TARC) (not shown).The method formed can be the method for spin coating.
The step being directed at can also be carried out, then this Semiconductor substrate with photoresist is placed in exposure sources the step etc. of step and the baking being exposed patterning photoresist layer, and exposes a part of mask layer 202.
See Fig. 2.Perform dilution HF(DHF) step removed, the mask layer of the SiO2 exposed can be removed and make it to be partially recessed between photoresist layer and protective layer 201 by this step.Can be to remove with 100:1DHF, the time of process could be arranged to the 20-50 second.
Then the step of ion implanting is performed.It can be i.e. the ion implanting forming raceway groove, pouch-shaped injection region, lightly-doped source drain electrode and source drain etc..The ion injected rests on the position near photoresist layer surface so that it is has the hardest surface, sees the appropriate section of the photoresist layer 203 shown in Fig. 2.
See Fig. 3.Wafer is performed again DHF and removes technique to remove the part mask layer 202 between protective layer and photoresist layer further.Selecting 300:1DHF in one embodiment, the response time is 40 seconds, makes its most recessed (pullback) between photoresist layer and protective layer 201 with the mask layer of the speed etching SiO2 of 103 angstrom min further, exposes the photoresist layer of inside.The ion injected due to great majority rests on the position near photoresist layer surface, the surface making photoresist layer has the hardest character, but the interior zone of photoresist layer, the interior zone of the photoresist layer exposed by removing the mask layer of SiO2 the most in the embodiment above still has softer character, sees the appropriate section of the photoresist layer 203 shown in Fig. 3.
With reference to Fig. 4.It is removed the step of photoresist layer.In the present invention, the wafer that processed through above-mentioned steps is performed hot sulphuric acid and or the mixture (SPM) of hydrogen peroxide remove technique, temperature of its reaction is about 125 degrees Celsius.I.e. can be easily by having photoresist layer removal inside the photoresist of more soft matter.
Then the step that mask layer 202 and the protective layer 201 of residual are removed can also be included.
In one embodiment of the invention, again perform DHF technique and remove the mask layer of remaining SiO2.
Then using H3PO4 to remove the protective layer of SiN, the reaction temperature of this step is about 160 degrees Celsius.
The method removing photoresist layer of the present invention is Whote-wet method (all-wet), it is not necessary to the plasma treatment process such as ashing.Particularly, the method removing photoresist layer of the present invention can be carried out in same wet process board, and the step of the most above-mentioned removal mask layer, protective layer and photoresist layer can be carried out in same wet process board, thus reduces the number of times to carrying wafers.
Therefore, according to the method removing photoresist of the present invention, it is possible to reduce the photoresist residual of wafer surface, and then it is effectively improved the performance of semiconductor device.
The present invention is illustrated by above-mentioned embodiment, but it is to be understood that, above-mentioned embodiment is only intended to citing and descriptive purpose, and in the range of being not intended to limit the invention to described embodiment.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-mentioned embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. the method removing the photoresist layer after high dose ion is injected, including step:
A) protective layer, mask layer and photoresist layer are sequentially formed on a semiconductor substrate;
B) described photoresist layer is patterned to define mask layer described in ion implanted regions expose portion;
C) wet method removes the mask layer of described exposure;
D) described substrate is performed ion implanting;
E) wet method removes the mask layer between protective layer and described photoresist layer to expose the interior zone of described photoresist layer further;
F) interior zone from described photoresist layer starts the wet method described photoresist layer of removal.
Method the most according to claim 1, it is characterised in that use nitride to form described protective layer.
Method the most according to claim 1, it is characterised in that the protective layer of described formation has thickness 10-20 angstrom.
Method the most according to claim 1, it is characterised in that use oxide to form described mask layer.
Method the most according to claim 1, it is characterised in that the method for described formation mask layer is LTCVD.
Method the most according to claim 1, it is characterised in that the mask layer of described formation has thickness 200-300 angstrom.
Method the most according to claim 1, it is characterised in that use DHF to perform the wet method of mask layer in step c) and step e) and remove.
Method the most according to claim 4, it is characterised in that use 100:1DHF in step c).
Method the most according to claim 4, it is characterised in that using 300:1DHF in step e), the response time is 40 seconds.
Method the most according to claim 1, it is characterised in that using SPM to perform the wet method of photoresist layer in step f) and remove, reaction temperature is 125 degrees Celsius.
11. methods according to claim 1, it is characterised in that after being additionally included in step f), wet method removes described mask layer and described protective layer.
12. methods according to claim 11, it is characterised in that use H3PO4After performing step f), the wet method of mask layer is removed, and reaction temperature is 160 degrees Celsius.
13. methods according to claim 11, it is characterised in that after using DHF to perform described step f), the wet method of protective layer is removed.
14. according to the method described in claim 1 or 11, it is characterised in that described wet method is removed and carried out in same wet process board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210292492.7A CN103592827B (en) | 2012-08-16 | 2012-08-16 | The method removing the photoresist layer after high dose ion is injected |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210292492.7A CN103592827B (en) | 2012-08-16 | 2012-08-16 | The method removing the photoresist layer after high dose ion is injected |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103592827A CN103592827A (en) | 2014-02-19 |
CN103592827B true CN103592827B (en) | 2016-08-03 |
Family
ID=50083024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210292492.7A Active CN103592827B (en) | 2012-08-16 | 2012-08-16 | The method removing the photoresist layer after high dose ion is injected |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103592827B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108305831A (en) * | 2018-02-09 | 2018-07-20 | 武汉新芯集成电路制造有限公司 | The minimizing technology of photoresist after a kind of injection of energetic ion |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6024887A (en) * | 1997-06-03 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company | Plasma method for stripping ion implanted photoresist layers |
CN101211125A (en) * | 2006-12-25 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Photoresist removeing method |
CN101308335A (en) * | 2007-05-15 | 2008-11-19 | 联华电子股份有限公司 | Method for removing photoresist layer and manufacture method of semiconductor element using the method |
CN102376552A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing grid electrode from damage in ion implantation process |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8252673B2 (en) * | 2009-12-21 | 2012-08-28 | International Business Machines Corporation | Spin-on formulation and method for stripping an ion implanted photoresist |
-
2012
- 2012-08-16 CN CN201210292492.7A patent/CN103592827B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6024887A (en) * | 1997-06-03 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company | Plasma method for stripping ion implanted photoresist layers |
CN101211125A (en) * | 2006-12-25 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Photoresist removeing method |
CN101308335A (en) * | 2007-05-15 | 2008-11-19 | 联华电子股份有限公司 | Method for removing photoresist layer and manufacture method of semiconductor element using the method |
CN102376552A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing grid electrode from damage in ion implantation process |
Also Published As
Publication number | Publication date |
---|---|
CN103592827A (en) | 2014-02-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10998235B2 (en) | FinFET with sloped surface at interface between isolation structures and manufacturing method thereof | |
US7297598B2 (en) | Process for erase improvement in a non-volatile memory device | |
US10115625B2 (en) | Methods for removal of hard mask | |
US8252673B2 (en) | Spin-on formulation and method for stripping an ion implanted photoresist | |
JP6370139B2 (en) | FINFET structure dopant implantation method | |
US8202791B2 (en) | Method for generating two dimensions for different implant energies | |
US7687388B2 (en) | Method of fabricating semiconductor high-voltage device comprising the steps of using photolithographic processes to form nitride spacer regions and dry etch process to form deep trench regions | |
JP2004152862A (en) | Method for manufacturing semiconductor device | |
CN110429034B (en) | Method for forming high voltage well region | |
CN103592827B (en) | The method removing the photoresist layer after high dose ion is injected | |
CN104253030A (en) | Method of semiconductor integrated circuit fabrication | |
CN103681248B (en) | Production method for semiconductor device | |
US20060030136A1 (en) | Method of fabricating a gate oxide layer | |
TWI305017B (en) | Semiconductor devices and methods for fabricating gate spacers | |
CN111599667A (en) | Photoetching definition method of ion implantation process | |
US20130109186A1 (en) | Method of forming semiconductor devices using smt | |
KR20090071928A (en) | Method for post cleaning of photo resist | |
KR101695901B1 (en) | Method of fabricating a substrate for manufacturing semiconductor device | |
JP2006294959A (en) | Process for fabricating semiconductor device and semiconductor substrate | |
US8034690B2 (en) | Method of etching oxide layer and nitride layer | |
KR100790740B1 (en) | Method of forming silicon-germanium junction and method of manufacturing semiconductor device using the method | |
KR100847829B1 (en) | Method for Forming Semiconductor Device | |
CN105261558A (en) | Manufacturing method for semiconductor | |
US9685330B1 (en) | Manufacturing method of semiconductor device | |
CN117174659A (en) | Method for manufacturing transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |