CN105261558A - Manufacturing method for semiconductor - Google Patents
Manufacturing method for semiconductor Download PDFInfo
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- CN105261558A CN105261558A CN201410320183.5A CN201410320183A CN105261558A CN 105261558 A CN105261558 A CN 105261558A CN 201410320183 A CN201410320183 A CN 201410320183A CN 105261558 A CN105261558 A CN 105261558A
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- photoresistance
- manufacture method
- hard baking
- ion implantation
- semiconductor substrate
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Abstract
The invention provides a manufacturing method for a semiconductor. The manufacturing method comprises the steps of providing a semiconductor substrate, and coating photoresist on the surface of the semiconductor substrate; exposing and developing for patterning the photoresist; and hard baking, wherein the temperature for hard baking ranges from 125 to 135 DEG C. According to the method, for products with thicker photoresist and deeper icon implantation depth, the hard baking process provided by the invention is adopted for better effectively removing a developing solution, water vapor and organic foreign matters hidden in the side wall and the bottom of the photoresist so as to avoid overflowing of the developing solution, the water vapor and the organic foreign matters to result in decrease of the vacuum degree of a cavity in the implantation step, so as to improve ion implantation quality, and the electrical properties and the yield of wafers.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor device.
Background technology
Generally comprise tens road lithographic process steps in chip manufacturing flow process, photoetching process is used for definition circuit figure, and for ensuing etching or ion implantation provide the figure defined, therefore photoetching process is of paramount importance link in chip manufacturing flow process.Each lithography step comprises again multiple sub-step, and wherein more crucial sub-step comprises: resist coating, exposure, development, baking (hardbake).Step of exposure be utilize reticle make segment beam through, to be irradiated on photoresistance, and photoresistance reaction, to form light acid, thus define preliminary figure.Next, development step developer solution is sprayed onto wafer (wafer) surface, the photoresistance reacted removed, forms final figure.Last baking procedure adopts certain temperature baking, and by developer solution unnecessary for crystal column surface, steam volatilization is removed.The photoetching baking temperature that current industry generally adopts is 105 DEG C, and baking time is 90 seconds.
Find aborning, for high tension apparatus product, the energy of ion implantation is larger, the degree of depth injecting silicon substrate is darker, the thickness thicker (in order to blocks ions does not enter non-injection regions) of corresponding photoresistance, therefore the developer solution of crystal column surface, organic impurities in steam or photoresistance is not easily removed totally, cause when carrying out ion implantation step, under the bombardment of energetic ion, the developer solution of crystal column surface, steam or other impurity overflow in a large number, vacuum pump has little time to take away, vacuum degree in chamber is caused to be deteriorated, especially when ion implantation just starts, thus affect the degree of depth and the concentration of ion implantation, final electric property and the yield affecting wafer.
Therefore, in order to solve the problems of the technologies described above, be necessary the manufacture method proposing a kind of new semiconductor device.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to overcome current Problems existing, the invention provides a kind of manufacture method of semiconductor device, comprising:
There is provided Semiconductor substrate, at the surface-coated photoresistance of described Semiconductor substrate;
Carry out exposing and development treatment, with photoresistance described in patterning;
Firmly dry, wherein, the temperature range of described hard baking is 125 ~ 135 DEG C.
Further, the time of described hard baking is 120 ~ 180s.
Further, the temperature of described hard baking is 130 DEG C, and the time is 150s.
Further, after described hard baking step, also comprise with the photoresistance of patterning for mask, carry out the step of ion implantation.
Further, it is thicker that described manufacture method is applicable to photoresistance thickness, the product that the ion implantation degree of depth is darker.
Further, the thickness range of described photoresistance is 5000-36000 dust.
Further, the degree of depth of described ion implantation is 0.5-1.5 μm.
Further, described semiconductor device is high tension apparatus.
In sum, according to method of the present invention, thicker for photoresistance thickness, the product that the ion implantation degree of depth is darker, adopt hard baking process conditions provided by the present invention more effectively can remove the developer solution, steam and the organic impurities that are hidden in photoresistance sidewall and bottom, thus when implantation step, avoid these materials to overflow and cause chamber vacuum degree to be deteriorated, and then the quality of ion implantation and the electric property of wafer and yield can be improved.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the process chart of method implementation step successively according to an exemplary embodiment of the present invention;
Fig. 2 A-2D implements the generalized section of obtained device successively for method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Exemplary embodiment
Below, the manufacture method of A-2D to high tension apparatus of the present invention that see figures.1.and.2 is described in detail.
First, in a step 101, Semiconductor substrate is provided, at the surface-coated photoresistance of described Semiconductor substrate.
With reference to figure 2A, described Semiconductor substrate 200 can be at least one on silicon, silicon-on-insulator (SOI), insulator on stacked silicon (SSOI), insulator in stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI).
Any method well known to those skilled in the art can be adopted to carry out the coating of photoresistance 201, and such as spin coating or curtain apply.Alternatively, the thickness range of described photoresistance 201 is 5000-36000 dust.Described photoresistance 201 can be positivity photoresistance or negativity photoresistance.The Thickness Ratio controlling the photoresistance 201 formed is thicker, in order in energetic ion injection process afterwards, has reasonable barrier effect.
Also can comprise the step of soft baking (SoftBaking) afterwards further, to remove solvent, strengthen the adhesion of photoresistance 201, the stress in release photoresistance 201, prevents photoresistance contaminated equipment.Alternatively, the baking temperature of described soft baking is 105 ~ 115 DEG C, and be preferably 110 DEG C, baking time is 60 seconds.
In a step 102, carry out exposing and development treatment, with photoresistance described in patterning.
Before exposing, also comprise the step of carrying out aiming at, any applicable method can be adopted to aim at, and therefore not to repeat here.
With reference to figure 2B, expose, utilize reticle make segment beam through, be irradiated on photoresistance 201, react with photoresistance, thus define preliminary figure.In one example, photolithography plate is provided with the pattern of deep high voltage well.
Alternatively, the step of rear baking (PostExposureBake, PEB) can also be carried out after exposure, to reduce standing wave effect.In one example, hotplate methodology is adopted to carry out the step of rear baking.Alternatively, the temperature of rear baking is 105 ~ 115 DEG C, and the time is 60 seconds.
With reference to figure 2C, the photoresistance 201 after exposure is developed, developer solution is sprayed onto Semiconductor substrate 200 surface, the photoresistance reacted is removed, forms final figure.According to the suitable developer solution of the type selecting of used photoresistance, such as, when photoresistance is positivity photoresistance, Tetramethylammonium hydroxide (TMAH) can be selected as developer solution, when photoresistance is negativity photoresistance, dimethylbenzene can be selected as developer solution.
In step 103, firmly dry.
With reference to figure 2D; hard baking can remove solvent unnecessary in photoresistance 201, strengthens the adhesive force between photoresistance 201 and substrate 200, improves the corrosion stability of photoresistance in the processes such as etching and ion implantation and protective capability simultaneously; in this step, the temperature range of described hard baking is 125 ~ 135 DEG C.The time of hard baking is 120 ~ 180s.As preferably, the temperature of described hard baking is 130 DEG C, and the time is 150s.
If the hard temperature >135 DEG C dried, or hard dry overlong time time, the risk of photoresistance melting and distortion can be produced, once cause the flowing of photoresistance 201, pattern precision can be caused to reduce, resolution variation.
Thicker for photoresistance 201 thickness, the product that the ion implantation degree of depth is darker, adopt hard baking process conditions proposed by the invention more effectively can remove the developer solution, steam and the organic impurities that are hidden in photoresistance 201 sidewall and bottom, thus when implantation step afterwards, above-mentioned substance benefit effectively can be avoided to go out to cause chamber vacuum degree to be deteriorated, and then the quality of ion implantation and the electric property of wafer and yield can be improved.
At step 104, with the photoresistance of patterning for mask, carry out ion implantation.
Alternatively, the degree of depth of described ion implantation is 0.5-1.5 μm.In one example, select N-type impurity ion, energetic ion injection is carried out to the region (i.e. the uncovered region of photoresistance) of predetermined formation high pressure trap, below described semiconductor substrate surface, forms N-type deep trap.Due to when step 103, remove completely developer solution remaining in photoresistance, steam and organic impurities, when therefore carrying out ion implantation, chamber vacuum degree can not be deteriorated, and then can improve the quality of ion implantation and the electric property of wafer and yield.
Also comprise other multiple steps afterwards for making high tension apparatus, therefore not to repeat here.It is thicker that said method is particularly useful for photoresistance thickness, the product that the ion implantation degree of depth is darker, such as, and high tension apparatus.
In sum, according to method of the present invention, thicker for photoresistance thickness, the product that the ion implantation degree of depth is darker, adopt hard baking process conditions provided by the present invention more effectively can remove the developer solution, steam and the organic impurities that are hidden in photoresistance sidewall and bottom, thus when implantation step, avoid these materials to overflow and cause chamber vacuum degree to be deteriorated, and then the quality of ion implantation and the electric property of wafer and yield can be improved.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (8)
1. a manufacture method for semiconductor device, comprising:
There is provided Semiconductor substrate, at the surface-coated photoresistance of described Semiconductor substrate;
Carry out exposing and development treatment, with photoresistance described in patterning;
Firmly dry, wherein, the temperature range of described hard baking is 125 ~ 135 DEG C.
2. manufacture method according to claim 1, is characterized in that, the time of described hard baking is 120 ~ 180s.
3. manufacture method according to claim 1, is characterized in that, the temperature of described hard baking is 130 DEG C, and the time is 150s.
4. manufacture method according to claim 1, is characterized in that, after described hard baking step, also comprises with the photoresistance of patterning for mask, carries out the step of ion implantation.
5. manufacture method according to claim 1, is characterized in that, it is thicker that described manufacture method is applicable to photoresistance thickness, the product that the ion implantation degree of depth is darker.
6. manufacture method according to claim 1, is characterized in that, the thickness range of described photoresistance is 5000-36000 dust.
7. manufacture method according to claim 4, is characterized in that, the degree of depth of described ion implantation is 0.5-1.5 μm.
8. manufacture method according to claim 1, is characterized in that, described semiconductor device is high tension apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410320183.5A CN105261558A (en) | 2014-07-04 | 2014-07-04 | Manufacturing method for semiconductor |
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| CN201410320183.5A CN105261558A (en) | 2014-07-04 | 2014-07-04 | Manufacturing method for semiconductor |
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| CN105261558A true CN105261558A (en) | 2016-01-20 |
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| CN201410320183.5A Pending CN105261558A (en) | 2014-07-04 | 2014-07-04 | Manufacturing method for semiconductor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807156A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | The method of ion implanting and the forming method of semiconductor structure |
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| US5591654A (en) * | 1992-12-28 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device and a resist composition used therein |
| CN102129167A (en) * | 2010-01-12 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Photolithographic mask and photolithographic method |
| CN102376552A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing grid electrode from damage in ion implantation process |
| CN103123444A (en) * | 2013-03-12 | 2013-05-29 | 上海集成电路研发中心有限公司 | Developing method of photolithography process |
| CN103558739A (en) * | 2013-11-21 | 2014-02-05 | 杭州士兰集成电路有限公司 | Photoresist removing method and photolithography technique reworking method |
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2014
- 2014-07-04 CN CN201410320183.5A patent/CN105261558A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591654A (en) * | 1992-12-28 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device and a resist composition used therein |
| CN102129167A (en) * | 2010-01-12 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Photolithographic mask and photolithographic method |
| CN102376552A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing grid electrode from damage in ion implantation process |
| CN103123444A (en) * | 2013-03-12 | 2013-05-29 | 上海集成电路研发中心有限公司 | Developing method of photolithography process |
| CN103558739A (en) * | 2013-11-21 | 2014-02-05 | 杭州士兰集成电路有限公司 | Photoresist removing method and photolithography technique reworking method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807156A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | The method of ion implanting and the forming method of semiconductor structure |
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