CN103531524B - Preparation method of interconnection structure with air gap - Google Patents
Preparation method of interconnection structure with air gap Download PDFInfo
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- CN103531524B CN103531524B CN201210225939.9A CN201210225939A CN103531524B CN 103531524 B CN103531524 B CN 103531524B CN 201210225939 A CN201210225939 A CN 201210225939A CN 103531524 B CN103531524 B CN 103531524B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
The present invention discloses a preparation method of an interconnection structure with an air gap, which comprises the following steps: depositing a dielectric layer on a substrate, wherein the dielectric layer is made of a carbon-containing material; selectively etching the dielectric layer for forming a plurality of groove patterns in the dielectric layer, and forming a loose first separating layer on the side walls of the groove patterns; forming filling dielectric in the groove patterns; forming a plurality of interconnected channels on the substrate, wherein the interconnected channels are staggered from the first separating layer; filling conductive material in the interconnected channels; and removing the first separating layer for forming the air gap at the side wall of each groove pattern. The method of the invention is used for reducing dielectric constant of the dielectric layer, reducing RC delay and settling a problem of low interconnection reliability.
Description
Technical field
The present invention relates to IC manufacturing field, the preparation side of more particularly to a kind of interconnection structure containing air-gap
Method.
Background technology
Integrity problem in super large-scale integration (Very Large Scale Integration, abbreviation VLSI)
Affected by device and interconnection technique.Reduce with characteristic size (Critical Dimension) and so that device gate delay is reduced
While, so that the interconnection performance of circuit is reduced.This is because characteristic size reduce will lead to interconnection line cross-sectional area and
The reduction of distance between centers of tracks, the ghost effect that resistance, electric capacity, inductance cause will have a strong impact on the performance of circuit.Therefore, interconnection can
Become the key factor of system for restricting reliability by sex chromosome mosaicism.The common method improving interlinking reliability is used for making to lead for reduction
The dielectric constant k of interlayer dielectric (ILD) material of electric metal line electric insulation, so that resistance-capacitance (RC) postpones to reduce,
Interconnecting signal can quickly pass through conductor.
At present, the method for common reduction dielectric layer material k value is mainly by following two：First, adopt porous material system
Standby dielectric layer, using porous material and increase its porosity and can effectively reduce its dielectric constant, and in mechanical properties
There is certain improvement, but have such problems as that chemically mechanical polishing damages, etching is lost and Vapor adsorption in this way；
2nd, air-gap (Air gap) is used to replace porous material filling around metal connecting line, in the prior art, to dielectric layer
The middle method introducing air-gap is after metal deposit and planarization, the ground floor dielectric layer between etching metal interconnecting wires, shape
Become groove, deposit second layer dielectric layer afterwards, in deposition process, dielectric layer material is on the groove top etching formation in advance
End gradually pinch off, thus cavity is retained in ground floor dielectric layer, but this method is difficult between metal interconnecting wires
Low K dielectrics layer material all etches totally, and the empty size in the ground floor dielectric layer obtaining in this way
Can not controlling, when etching of second layer metal throuth hole it may appear that cutting through the phenomenon in the cavity in ground floor dielectric layer, causing tight
The integrity problem of weight.
Therefore, how to provide a kind of preparation method of low-k dielectrics layer, thus improving the reliability of interconnection, it has also become
The problem that those skilled in the art need to solve.
Content of the invention
It is an object of the invention to, a kind of preparation method of the interconnection structure containing air-gap (Air gap) is provided, is used for
Reduce the dielectric constant of dielectric layer, reduce RC retardation ratio, solve the problems, such as interlinking reliability.
For solving above-mentioned technical problem, the present invention provides a kind of preparation method of the interconnection structure containing air-gap, including：
Deposit dielectrics layer on substrate, the material of described dielectric layer is carbonaceous material；
Dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, and removes and is located at
Carbon in the dielectric layer of described groove pattern sidewall areas, to form loose on the side wall of described groove pattern
One interlayer；
Form filling dielectric in described groove pattern；
Form some interconnecting channels on the substrate, described some interconnecting channels are located at described dielectric layer and described fill out
In at least one of charged media, described interconnecting channel is staggered with described first interlayer；
Conductive material is filled in described interconnecting channel；And
Remove described first interlayer, form air-gap with the side-walls in described groove pattern.
Further, using dielectric layer described in dry etch process selective etch, the quarter of described dry etch process
Erosion gas comprises one of fluorine base gas and epoxide gas or combination.
Further, form the step of some groove patterns in described dielectric layer and formed in described groove pattern
Between the step of filling dielectric, also include burin-in process step, continue to remove the electricity being located at described groove pattern sidewall areas
Carbon in dielectric layer, to adjust the thickness of described first interlayer.
Further, the reacting gas of described burin-in process step comprises epoxide gas.
Further, after removing the step of described first interlayer, described interconnecting channel has described sky each other
Air gap.
Further, after removing the step of described first interlayer, described adjacent interconnecting channel institute each other
The quantity stating air-gap is more than or equal to 1.
Further, this preparation method also includes：
While forming some interconnecting channels on the substrate, remove the electrolyte of the sidewall areas of described interconnecting channel
Carbon in layer or filled media, to form the second loose interlayer on the side wall of described interconnecting channel；
Conductive material is filled in described interconnecting channel；And
While removing described first interlayer, remove described second interlayer, formed with the side-walls in described interconnecting channel
Interconnecting channel air-gap.
Further, also include before deposit dielectrics layer step on substrate：Deposition-etch stops on the substrate
Layer.
Further, the step of deposit dielectrics layer and form some groove patterns in described dielectric layer on substrate
Step between, also include：It is sequentially depositing protective oxide film and hard mask layer on said dielectric layer.
Further, the material of described dielectric layer is the lower dielectric material of carbon containing.
Further, the material of described filling dielectric is identical with the material of described dielectric layer.
Further, described interconnecting channel is one of raceway groove and through hole or combination.
Further, the described step that described interconnecting channel filled by conductive material includes：
Metal barrier and the Seed Layer of described conductive material is prepared in described interconnecting channel；
Deposit described conductive material to fill described interconnecting channel；And
Planarize described conductive material to expose described dielectric layer.
Further, described first interlayer is removed using wet-etching technology.
Further, the etch liquids of described wet-etching technology are the Fluohydric acid. of dilution.
Compared with prior art, the present invention provide the interconnection structure containing air-gap preparation method have following excellent
Point：
1st, the preparation method of the interconnection structure containing air-gap that the present invention provides, is first shape before forming interconnecting channel
Become the first interlayer, then after described interconnecting channel filled by conductive material, remove described first interlayer to form air-gap, institute
State the dielectric constant that air-gap reduces dielectric layer, reduce RC retardation ratio.
2nd, the preparation method of the interconnection structure containing air-gap that the present invention provides, is first shape before forming interconnecting channel
Become the first interlayer, then after described interconnecting channel filled by conductive material, remove described first interlayer to form air-gap, institute
Impact will not be produced to interconnecting channel with the process forming air-gap, it is to avoid air-gap and the conducting of interconnecting channel, improve mutually
Even reliability of structure is high.
3rd, the preparation method of the interconnection structure containing air-gap that the present invention provides, is first shape before forming interconnecting channel
Become the first interlayer, the thickness of the first interlayer is nanoscale, so the thickness of the air-gap removing described first interlayer afterwards and being formed
Degree size is little, and the thickness of air-gap, length dimension, quantity, arrangement mode and the equal scalable of shape, so adopt should
The mechanicalness of the interconnection structure that method obtains can control.
Brief description
Fig. 1 is the flow chart of the preparation method of the interconnection structure containing air-gap in one embodiment of the invention；
Fig. 2 a- Fig. 2 f is the schematic diagram of the preparation method of the interconnection structure containing air-gap in one embodiment of the invention；
Fig. 3 a- Fig. 3 c is the interconnection structure being obtained using the preparation method containing the interconnection structure of air-gap for the present invention
Schematic diagram.
Specific embodiment
Below in conjunction with schematic diagram, the preparation method containing the interconnection structure of air-gap for the present invention is carried out in more detail
Description, which show the preferred embodiments of the present invention it should be appreciated that those skilled in the art can change described here
Invention, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that for those skilled in the art's
Widely known, and it is not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
It is necessary to make a large amount of implementation details to realize the specific objective of developer in sending out, such as according to relevant system or relevant business
Limit, another embodiment is changed into by an embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Seek book, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all in the form of very simplification and all using non-
Accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
The core concept of the present invention is, provides a kind of preparation method of the interconnection structure containing air-gap, on substrate
Deposit dielectrics layer, the material of described dielectric layer is carbonaceous material, dielectric layer described in selective etch, to be situated between in described electricity
Form some groove patterns in matter layer, remove the carbon being located in the dielectric layer of described groove pattern sidewall areas, with
Form the first loose interlayer on the side wall of described groove pattern, form filling dielectric in described groove pattern, described fill out
Charged media is separated by described first interlayer with the side wall of described groove pattern, after conductive interconnection passage is formed, removes institute
State the first interlayer, form air-gap with the side-walls in described groove pattern, described air-gap reduces the dielectric of dielectric layer
Constant, and the thickness of air-gap, length dimension, quantity, arrangement mode and the equal scalable of shape, so this interconnection structure
Mechanicalness can control.
Refer to Fig. 1, Fig. 1 is the flow process of the preparation method of the interconnection structure containing air-gap in one embodiment of the invention
Figure, in conjunction with the core concept of Fig. 1 and the present invention, the present invention provides a kind of preparation method of the interconnection structure containing air-gap, bag
Include following steps：
Step S01, deposit dielectrics layer on substrate, the material of described dielectric layer is carbonaceous material；
Step S02, dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, and
Remove the carbon being located in the dielectric layer of described groove pattern sidewall areas, to be formed on the side wall of described groove pattern
The first loose interlayer；
Step S03, forms filling dielectric in described groove pattern；
Step S04, forms some interconnecting channels on the substrate, and described some interconnecting channels are located at described dielectric layer
Or in described filling dielectric, or be located at respectively in described dielectric layer and described filling dielectric, described interconnecting channel with
Described first interlayer is staggered；
Step S05, fills conductive material in described interconnecting channel；
Step S06, removes described first interlayer, forms air-gap with the side-walls in described groove pattern.
Hereinafter refer to the preparation side that Fig. 1 and Fig. 2 a- Fig. 2 f describes the interconnection structure containing air-gap of the present invention in detail
The detailed process of method, wherein, Fig. 2 a- Fig. 2 f is the preparation method of the interconnection structure containing air-gap in one embodiment of the invention
Schematic diagram.
Carry out step S01 first, on the substrate 101 deposit dielectrics layer 102, wherein substrate 101 comprises necessary device
And interconnection, described substrate 101 can be the Semiconductor substrate with source area, drain region and isolation structure, can also be bag
Include the structure of the multilayer interconnection layer in above-mentioned Semiconductor substrate and Semiconductor substrate.Due in the present embodiment, step S01 it
Before, the step that is additionally included in Deposited Etch Stop 201 on substrate 101, so first sunk on the substrate 101 using conventional method
Long-pending etching stop layer 201, described etching stop layer 201 can play quarter during subsequent etching forms groove pattern 103
Erosion fails.Then using conventional method deposit dielectrics layer 102 on etching stop layer 201, see Fig. 2 a.Dielectric layer
102 material is carbonaceous material, to ensure to readily obtain the first interlayer 104 in subsequent step, preferably selects to contain
The lower dielectric material of carbon, such as one kind of silicon nitride of silicon dioxide, the fluorine silica glass of carbon dope and carbon dope of carbon dope and combinations thereof,
But other carbonaceous materials can also be as the material of dielectric layer 102 also within the thought range of the present invention.
Then carry out step S02, form some groove patterns 103 in described dielectric layer 102, and remove positioned at groove
Carbon in the dielectric layer 102 in figure 103 side wall 104 region, to have first on the side wall 131 of groove pattern 103
Interlayer 104, is shown in Fig. 2 b.Using conventional dry etch process selective etch dielectric layer 102, with dielectric layer 102
Form groove pattern 103, while etching dielectric layer 102, the plasma in dry etch process is known from experience to groove pattern
103 side wall 131 is bombarded, so in the gas of dry etch process and the electrolyte in groove pattern 103 side wall 131 region
Carbon reaction in layer 102, makes the material on the side wall 131 of groove pattern 103 become ratio more loose, forms the first interlayer
104.Preferably, adding fluorine base gas or epoxide gas in dry etch process, or it is simultaneously introduced fluorine base gas and epoxide
Gas because fluorine base gas and epoxide gas can with carbon react, and retain the electricity in groove pattern 103 side wall 131 region
Non-carbon element in dielectric layer 102, so it is more loose to make the material on the side wall 131 of groove pattern 103 become ratio, forms first
Interlayer 104.Can be by adjusting the technological parameter of dry etch process, such as gas flow, pressure, voltage, power etc. controls and goes
Except the amount of carbon, the thickness of the first interlayer 104 can be controlled simultaneously.The depth of groove pattern 103 can be controlled
System, can be equal to or less than the height of dielectric layer 102, thus penetrated or partially pass through the first of dielectric layer 102 every
Layer 104.
In preferred embodiment, between step S02 and step S03, also include burin-in process step, burin-in process walks
Carbon in the dielectric layer in rapid groove pattern 103 side wall 131 region of removal further, to control the thickness of the first interlayer 104
Degree.Burin-in process step preferably using plasma dry etch process, wherein preferably reacting gas is using containing epoxide
Gas so that in burin-in process step, plasma continuation can be bombarded to the side wall 131 of groove pattern 103, wait from
Epoxide gas in daughter continues to react with the carbon in the dielectric layer in side wall 131 region of groove pattern 103, carbonoxide
Element, makes the loose part of the side wall 131 of groove pattern 103 increase, obtains the thickness of the first interlayer 104 of needs.Can lead to
Overregulate the technological parameter of plasma dry etch process, such as gas flow, pressure, voltage, power etc. control removal carbon unit
The amount of element, is controlled to the thickness of the first interlayer 104.
Then carry out step S03, groove pattern 103 forms filling dielectric 105, filling dielectric 105 and groove
The side wall 131 of figure 104 is separated by the first interlayer 104, sees Fig. 2 c.Deposited in groove pattern 103 using conventional method
Filling dielectric 105, being then passed through planarization makes filling dielectric 105 equal with dielectric layer 102, in the structure obtaining, fills out
Charged media 105 is separated by the first interlayer 104 with dielectric layer 102.The material of filling dielectric 105 preferably selects and electricity
Dielectric layer 102 identical material, but the material differing, as long as the material of filling dielectric 105 is dielectric substance, all at this
Within the thought range of invention.
Subsequently carry out step S04, form some interconnecting channels 106, some interconnecting channels 106 be located at dielectric layer 102 or
In filling dielectric 105, or some of which is located at other in dielectric layer 102 and is located in filling dielectric 105,
Interconnecting channel 106 is staggered with the first interlayer 104.Preferably, interconnecting channel 106 has the first interlayer 104 each other, intercommunicated
The quantity of road 106 the first interlayer 104 each other is more than or equal to 1.Interconnecting channel 106 is one of raceway groove and through hole or group
Close, for the interconnection connection of metal.In the present embodiment, etched in filling dielectric 105 using conventional lithographic method
Form interconnecting channel 106, interconnecting channel 106 both sides has the first interlayer 104, sees Fig. 2 d.Due to also setting up in the present embodiment
Etching stop layer 201, so interconnecting channel 106 passes through etching stop layer 201, is connected with the interconnection ensureing conductive material 107.
Then carry out step S05, fill interconnecting channel 106 with conductive material 107, this step includes：In interconnecting channel 106
Inside prepare metal barrier and the Seed Layer of conductive material 107, to improve the filling quality of conductive material 107；Deposition conduction material
Material 107 is to fill interconnecting channel 106；And planarization conductive material 107 is to expose dielectric layer 102.
Finally carry out step S06, remove the first interlayer 104, to form air-gap at the side wall 131 of groove pattern 103
108.First interlayer 104 is removed using conventional wet-etching technology, is formed between sky at the side wall 131 of groove pattern 103
Gap, thus form air-gap 108.Preferably, wet-etching technology is using the Fluohydric acid. of dilution, (percentage ratio of dilution 100: 1～
1000: 1) other structures are not caused to remove the first interlayer 104 to damage.By controlling the depth of groove pattern 103, thus
Penetrated or partially passed through the first interlayer 104 of dielectric layer 102, the depth of air-gap 108, air can be controlled further
Gap 108 can penetrate or partially pass through dielectric layer 102.Air-gap 108 position in an interconnection structure and quantity can be according to
Need to arrange, the thickness due to air-gap 108 can accomplish nanoscale, so the machinery of the interconnection structure being obtained using the method
Property is good, due to the thickness of air-gap 108, length dimension, quantity scalable, so the interconnection structure being obtained using the method
Dielectric constant can be adjusted as required.
The present invention is not limited to above-described embodiment, can increase some steps as between step S01 and step S02, go back
Protective oxide film and hard mask layer, protective oxide film and hard mask layer can be sequentially depositing on dielectric layer 102
For improving the precision of etching and reducing the damage to dielectric layer 102 for the etching process, to improve the quality of etching, and can
To remove in the planarization process in step S03；Can also in carrying out step S04, some interconnecting channels 106 of formation
Position, and the quantity of interconnecting channel 106 the first interlayer 104 each other can be differently configured from above-described embodiment, such as intercommunicated
Road 106 is located in dielectric layer 102, or some of which is located at other in dielectric layer 102 and is situated between positioned at filling electricity
In matter 105, the quantity more than one of interconnecting channel 106 the first interlayer 104 each other, see Fig. 3 a, Fig. 3 b；In addition, this preparation
The side wall being additionally may included in interconnecting channel 106 in the step of method forms air-gap 108, in the side wall shape of interconnecting channel 106
The step becoming interconnecting channel air-gap 118 includes：While carrying out step S04, remove the sidewall region of described interconnecting channel 106
Carbon in the dielectric layer in domain or filled media, so that the second loose interlayer to be formed on the side wall of interconnecting channel 106, so
After carry out step S05, finally carry out S06, remove described first interlayer while, remove described second interlayer, with interconnection
The side-walls of passage 106 form interconnecting channel air-gap 118, see Fig. 3 c, can be by dry etch process in regulating step S04
Technological parameter, such as gas flow, pressure, voltage, power etc. controls the amount removing carbon, simultaneously can be to the second interlayer
Thickness is controlled, this side simultaneously forming air-gap 108 in the side wall of groove pattern 103 and the side wall of interconnecting channel 106
Method, in the case of not increasing processing step, can further increase the quantity of air-gap, reduce Jie between interconnection structure
Electric constant, improves the reliability of interconnection.
In sum, the present invention provides a kind of preparation method of the interconnection structure containing air-gap, deposits electricity on substrate
Dielectric layer, the material of described dielectric layer is carbonaceous material, and dielectric layer described in selective etch, with described dielectric layer
Form some groove patterns, remove the carbon being located in the dielectric layer of described groove pattern sidewall areas, with described recessed
Form the first loose interlayer on the side wall of groove figure, described groove pattern forms filling dielectric, described filling electricity is situated between
Matter is separated by described first interlayer with the side wall of described groove pattern, after conductive interconnection passage is formed, removes described first
Interlayer, forms air-gap with the side-walls in described groove pattern, described air-gap reduces the dielectric constant of dielectric layer, and
And the thickness of air-gap, length dimension, quantity, arrangement mode and the equal scalable of shape, so the machinery of this interconnection structure
Property can control.Compared with prior art, the present invention provide the interconnection structure containing air-gap preparation method have following
Advantage：
1st, the preparation method of the interconnection structure containing air-gap that the present invention provides, is first shape before forming interconnecting channel
Become the first interlayer, then after described interconnecting channel filled by conductive material, remove described first interlayer to form air-gap, institute
State the dielectric constant that air-gap reduces dielectric layer, reduce RC retardation ratio.
2nd, the preparation method of the interconnection structure containing air-gap that the present invention provides, is first shape before forming interconnecting channel
Become the first interlayer, then after described interconnecting channel filled by conductive material, remove described first interlayer to form air-gap, institute
Impact will not be produced to interconnecting channel with the process forming air-gap, it is to avoid air-gap and the conducting of interconnecting channel, improve mutually
Even reliability of structure is high.
3rd, the preparation method of the interconnection structure containing air-gap that the present invention provides, is first shape before forming interconnecting channel
Become the first interlayer, the thickness of the first interlayer is nanoscale, so the thickness of the air-gap removing described first interlayer afterwards and being formed
Degree size is little, and the thickness of air-gap, length dimension, quantity, arrangement mode and the equal scalable of shape, so adopt should
The mechanicalness of the interconnection structure that method obtains can control.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (14)
1. a kind of preparation method of the interconnection structure containing air-gap, including：
Deposit dielectrics layer on substrate, the material of described dielectric layer is carbonaceous material；
Dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, and removes positioned at described
Carbon in the dielectric layer of groove pattern sidewall areas, with formed on the side wall of described groove pattern loose first every
Layer；
Form filling dielectric in described groove pattern；
Form some interconnecting channels on the substrate, described some interconnecting channels are located at described dielectric layer and described filling electricity
In at least one of medium, described interconnecting channel is staggered with described first interlayer；
Conductive material is filled in described interconnecting channel；And
Remove described first interlayer, form air-gap with the side-walls in described groove pattern；
Wherein, this preparation method also includes：While forming some interconnecting channels on the substrate, remove described interconnecting channel
The dielectric layer of sidewall areas or filled media in carbon, so that loose to be formed on the side wall of described interconnecting channel
Two interlayers；And while removing described first interlayer, remove described second interlayer, with the side-walls shape in described interconnecting channel
Become interconnecting channel air-gap.
2. the preparation method of the interconnection structure containing air-gap as claimed in claim 1 is it is characterised in that adopt dry etching
Process selectivity etches described dielectric layer, and the etching gas of described dry etch process comprise in fluorine base gas and epoxide gas
One kind or combination.
3. the preparation method of the interconnection structure containing air-gap as claimed in claim 1 is it is characterised in that in described electrolyte
Formed in layer between the step of some groove patterns and the step forming filling dielectric in described groove pattern, also include old
Change process step, continue to remove the carbon being located in the dielectric layer of described groove pattern sidewall areas, to adjust described the
The thickness of one interlayer.
4. the preparation method of the interconnection structure containing air-gap as claimed in claim 3 is it is characterised in that described burin-in process
The reacting gas of step comprises epoxide gas.
5. the preparation method of the interconnection structure containing air-gap as claimed in claim 1 is it is characterised in that removing described the
After the step of one interlayer, described interconnecting channel has described air-gap each other.
6. the preparation method of the interconnection structure containing air-gap as claimed in claim 5 is it is characterised in that removing described the
After the step of one interlayer, the quantity of described adjacent interconnecting channel described air-gap each other is more than or equal to 1.
7. the interconnection structure containing air-gap as described in any one in claim 1-6 preparation method it is characterised in that
Substrate also includes before deposit dielectrics layer step：Deposited Etch Stop on the substrate.
8. the interconnection structure containing air-gap as described in any one in claim 1-6 preparation method it is characterised in that
On substrate between the step of deposit dielectrics layer and the step forming some groove patterns in described dielectric layer, also wrap
Include：It is sequentially depositing protective oxide film and hard mask layer on said dielectric layer.
9. the interconnection structure containing air-gap as described in any one in claim 1-6 preparation method it is characterised in that
The material of described dielectric layer is the lower dielectric material of carbon containing.
10. the preparation method of the interconnection structure containing air-gap as described in any one in claim 1-6, its feature exists
In the material of described filling dielectric is identical with the material of described dielectric layer.
The preparation method of 11. interconnection structures containing air-gap as described in any one in claim 1-6, its feature exists
In described interconnecting channel is one of raceway groove and through hole or combination.
The preparation method of 12. interconnection structures containing air-gap as described in any one in claim 1-6, its feature exists
In the described step that described interconnecting channel filled by conductive material includes：
Metal barrier and the Seed Layer of described conductive material is prepared in described interconnecting channel；
Deposit described conductive material to fill described interconnecting channel；And
Planarize described conductive material to expose described dielectric layer.
The preparation method of 13. interconnection structures containing air-gap as described in any one in claim 1-6, its feature exists
In using wet-etching technology described first interlayer of removal.
The preparation method of 14. interconnection structures containing air-gap as claimed in claim 13 is it is characterised in that described wet method is carved
The etch liquids of etching technique comprise Fluohydric acid..
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| CN105826279B (en) * | 2015-01-06 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| KR102473660B1 (en) | 2016-02-22 | 2022-12-02 | 삼성전자주식회사 | Memory device and method of manufacturing the same |
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| CN101231969A (en) * | 2007-01-26 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Forming method of IC structure |
| CN101589459A (en) * | 2007-01-26 | 2009-11-25 | 应用材料股份有限公司 | Uv curing of pecvd-deposited sacrificial polymer films for air-gap ild |
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| TWI227043B (en) * | 2000-09-01 | 2005-01-21 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device |
| US6924222B2 (en) * | 2002-11-21 | 2005-08-02 | Intel Corporation | Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide |
| JP4864307B2 (en) * | 2003-09-30 | 2012-02-01 | アイメック | Method for selectively forming an air gap and apparatus obtained by the method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101231969A (en) * | 2007-01-26 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Forming method of IC structure |
| CN101589459A (en) * | 2007-01-26 | 2009-11-25 | 应用材料股份有限公司 | Uv curing of pecvd-deposited sacrificial polymer films for air-gap ild |
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