CN110265352A - The forming method of fleet plough groove isolation structure and the forming method of memory device - Google Patents
The forming method of fleet plough groove isolation structure and the forming method of memory device Download PDFInfo
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- CN110265352A CN110265352A CN201910550301.4A CN201910550301A CN110265352A CN 110265352 A CN110265352 A CN 110265352A CN 201910550301 A CN201910550301 A CN 201910550301A CN 110265352 A CN110265352 A CN 110265352A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The present invention provides a kind of forming method of fleet plough groove isolation structure and the forming method of memory device, substrate is provided and covers the mask layer of substrate, then the substrate of etch mask layer and segment thickness, to form at least one isolated groove；Filling isolated groove is formed using high-aspect-ratio technique and extends over the dielectric layer of mask layer, wherein, the dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, the top surface of the first medium layer is higher than the substrate and is lower than the top surface of the mask layer, the flow of silicon-containing gas is less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer in high-aspect-ratio technique due to forming the second dielectric layer, so when near the notch for filling isolated groove, since the flow of silicon-containing gas in high-aspect-ratio technique is smaller, filling capacity is preferable, the notch that can be avoided isolated groove nearby generates hole, and then improve the performance of semiconductor storage unit.
Description
Technical field
The present invention relates to the forming method of technical field of semiconductor preparation more particularly to a kind of fleet plough groove isolation structure and deposit
The forming method of memory device.
Background technique
In semiconductor processing, the quality of fleet plough groove isolation structure (Shallow trench isolation, STI) determines
The basic electric property of semiconductor devices.With the rapid development of semiconductor preparing process, the feature of semiconductor storage unit
Size is substantially reduced, and in order to realize higher current densities, not only the characteristic size of semiconductor devices is reduced, semiconductor devices
In the size of fleet plough groove isolation structure corresponding can also reduce.The manufacturing process of fleet plough groove isolation structure is proposed as a result,
Requirements at the higher level, for nonvolatile flash memory (Nor Flash), technology node has evolved to 55nm hereinafter, shallow trench
Isolation structure peak width becomes smaller, and depth-to-width ratio (Aspect Ratio, AR) becomes larger, so that the filling of isolated groove becomes more next
It is more difficult, become an important processing step for influencing memory device performance.
Industry generallys use high-aspect-ratio technique (High Aspect Ratio Process, HARP) as isolation at present
The filling of groove, filling capacity is extremely strong, can preferably fill depth-to-width ratio be greater than or equal to 3 isolated groove, but with
Storage unit characteristic size is smaller and smaller, and depth-to-width ratio increases, can be in isolated groove when using HARP process filling isolated groove
(filling closing at) forms hole at notch, and hole can develop as hole in the subsequent process, leads to semiconductor storage unit
Performance decline.
Summary of the invention
The purpose of the present invention is to provide a kind of forming method of fleet plough groove isolation structure and the forming method of memory device,
Hole can be formed when solving the problem of existing HARP process filling isolated groove in isolated groove, and guarantees HARP
The dielectric layer density and hardness with higher filled at the notch of isolated groove, avoids producing dielectric layer in the subsequent process
Raw hole defect.
In order to achieve the above object, the present invention provides a kind of forming methods of fleet plough groove isolation structure, comprising:
One substrate is provided, a mask layer is formed on the substrate；
The substrate of the mask layer and segment thickness is etched, to be formed at least in the substrate and the mask layer
One isolated groove；
Dielectric layer is formed using high-aspect-ratio technique, the dielectric layer fills the isolated groove and extends over described cover
Mold layer, wherein the dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, and described first is situated between
The top surface of matter layer is higher than the substrate and is lower than the top surface of the mask layer, and forms the high-aspect-ratio work of the second dielectric layer
The flow of silicon-containing gas is less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer in skill.
Optionally, the material of the dielectric layer is silica, and the silicon-containing gas is ethyl orthosilicate.
Optionally, formed the flow of silicon-containing gas in the high-aspect-ratio technique of the first medium layer between 1mg/s~
Between 1.5mg/s.
Optionally, formed the flow of silicon-containing gas in the high-aspect-ratio technique of the second dielectric layer between 0.6mg/s~
Between 0.8mg/s.
Optionally, the top surface of the first medium layer be located at the mask layer in the vertical direction height 3/10~2/5
Place.
Optionally, the top surface of the top surface of the second dielectric layer is higher than between the top surface of the mask layer in vertical direction
On distance between the top surface 3/10~2/5 of the height in the vertical direction of the mask layer.
Optionally, it is formed after the dielectric layer, the forming method of the fleet plough groove isolation structure further include:
The dielectric layer is planarized to the mask layer top surface, so that remaining in the isolated groove and the isolated groove
The dielectric layer constitute fleet plough groove isolation structure.
The present invention also provides a kind of forming methods of memory device, comprising:
One substrate is provided, a mask layer is formed on the substrate；
The substrate of the mask layer and segment thickness is etched, to be formed at least in the substrate and the mask layer
One isolated groove；
Dielectric layer is formed using high-aspect-ratio technique, the dielectric layer fills the isolated groove and extends over described cover
Mold layer, wherein the dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, and described first is situated between
The top surface of matter layer is higher than the substrate and is lower than the top surface of the mask layer, and forms the high-aspect-ratio work of the second dielectric layer
The flow of silicon-containing gas is less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer in skill.
Optionally, it is formed after the dielectric layer, the forming method of the memory device further include:
The dielectric layer is planarized to the mask layer top surface, so that remaining in the isolated groove and the isolated groove
The dielectric layer constitute fleet plough groove isolation structure.
Optionally, it is formed after the fleet plough groove isolation structure, the forming method of the memory device further include:
The mask layer is removed to form several openings；
Floating gate material layer is formed over the substrate, and the floating gate material layer filling is described to be open and extend over described shallow
Groove isolation construction；
The part that floating gate material layer is higher than the fleet plough groove isolation structure is removed, the floating gate material layer in the opening is retained
To constitute floating gate layer.
Inventors have found that high-aspect-ratio technique can be reacted shape in HARP board using silicon-containing gas and ozone
At dielectric layer to fill isolated groove, also, when the flow of increase silicon-containing gas, the speed of the dielectric layer of formation increases, advanced
Width is more worse than the filling capacity of technique, and the quality of dielectric layer can be deteriorated；Conversely, when reducing the flow of silicon-containing gas, Jie of formation
The speed of matter layer reduces, and the filling capacity of high-aspect-ratio technique is stronger, and the quality of dielectric layer can improve.Further, inventor goes back
It it was found that hole is usually found near the notch of isolated groove when high-aspect-ratio process filling isolated groove, and is in vertical
Threadiness distribution.
Based on this, in the forming method of fleet plough groove isolation structure provided by the invention and the forming method of memory device,
It include: the mask layer that substrate is provided and covers substrate, the then substrate of etch mask layer and segment thickness, to form at least one
Isolated groove；Filling isolated groove is formed using high-aspect-ratio technique and extends over the dielectric layer of mask layer, wherein is given an account of
Matter layer includes the second dielectric layer of first medium layer and the covering first medium layer, and the top surface of the first medium layer is higher than institute
It states substrate and is lower than the top surface of the mask layer, silicon-containing gas in the high-aspect-ratio technique due to forming the second dielectric layer
Flow is less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer, so in filling isolated groove
When near notch, since the flow of silicon-containing gas in high-aspect-ratio technique is smaller, filling capacity is preferable, can be avoided isolated groove
Notch nearby generate hole, and then improve the performance of semiconductor storage unit, and due to being only in filling isolated groove
Notch near when reduce the flow of silicon-containing gas in high-aspect-ratio technique, the influence to yield is also smaller.
Detailed description of the invention
Fig. 1-Fig. 7 is the diagrammatic cross-section of the semiconductor structure formed using a kind of forming method of memory device；
Fig. 8 is the flow chart of the forming method of fleet plough groove isolation structure provided in an embodiment of the present invention；
Fig. 9-Figure 14 is half that the forming method provided in an embodiment of the present invention using the fleet plough groove isolation structure is formed
The diagrammatic cross-section of conductor structure；
Figure 15-Figure 17 be memory device provided in an embodiment of the present invention forming method formed fleet plough groove isolation structure it
The diagrammatic cross-section of the semiconductor structure formed afterwards；
Wherein, appended drawing reference are as follows:
101- substrate；102- pad oxide；103- mask layer；104- isolated groove；105- dielectric layer；106- hole；
106 '-holes；107- fleet plough groove isolation structure；108- opening；109- floating gate material layer；110- floating gate layer；
201- substrate；202- pad oxide；203- mask layer；204- isolated groove；205- dielectric layer；2051- first is situated between
Matter layer；2052- second dielectric layer；2053- third dielectric layer；207- fleet plough groove isolation structure；208- opening；209- floating gate material
Layer；210- floating gate layer；
The height of H1- mask layer in the vertical direction；
The height of H2- mask layer in the vertical direction；
H3- first medium layer exceeds the height of substrate in the vertical direction；
H4- second dielectric layer exceeds the height of mask layer in the vertical direction.
Specific embodiment
The diagrammatic cross-section of the semiconductor structure formed using a kind of forming method of memory device is as shown in Fig. 1-Fig. 7.
The memory device is, for example, a nonvolatile flash memory (Nor Flash), specifically, substrate 101 is provided referring initially to Fig. 1, it is described
A pad oxide 102 and mask layer 103 are formed on substrate 101, the pad oxide 102 covers the substrate 101, described to cover
Mold layer 103 covers the pad oxide 102, and the height H1 (thickness) in the vertical direction of the mask layer 103 depends on needing
Floating gate to be formed thickness (namely the mask layer 103 according to the thickness design of floating gate in the memory device vertical
Height H1 on direction).Then, as shown in Fig. 2, etching the mask layer 103, the pad oxide 102 and segment thickness
The substrate 101 forms several isolated grooves 104, and the isolated groove 104 is located in the substrate 101, active for being isolated
Area, the device that the quantity and size of the isolated groove 104 can be formed according to actual needs are designed.Then figure is please referred to
3, dielectric layer 105 is formed in the isolated groove 104 using high-aspect-ratio technique (HARP technique), makes the dielectric layer 105
It fills the isolated groove 104 and extends over the mask layer 103.It is understood that the high-aspect-ratio technique is usual
It is in HARP board, using silicon-containing gas (e.g. ethyl orthosilicate, TEOS) and ozone (O3) reaction generation dielectric layer 105
To fill the isolated groove 104, but as it can be seen that since the operational characteristic of high-aspect-ratio technique causes in institute from Fig. 2 and Fig. 3
The notch for stating isolated groove 104 can nearby generate hole 106, and the hole 106 is in vertical linear distribution.
Further, as shown in figure 4, planarizing the dielectric layer 105 to the mask using CMP process
103 top surface of layer, make in the isolated groove 104 and the isolated groove 104 the remaining dielectric layer 105 constitute shallow trench every
From structure 107, as can be seen from Fig. 4, at this point, the hole 106 exposes and is located at the top of the fleet plough groove isolation structure 107.
Next as shown in figure 5, removing the mask layer 103 (for example, the material when the mask layer 103 is nitrogen using wet etching
When SiClx, need to remove the mask layer 103 using hot phosphoric acid), since the hole 106 is located at the fleet plough groove isolation structure
107 top, and 105 corrosion resistance of dielectric layer around the hole 106 is very poor, when causing to remove the mask layer 103, meeting
Corrode the dielectric layer 105 around the hole 106, the hole 106 is caused to be widened and/or opened up deeply to form hole
106'.The mask layer 103 forms several openings 108 after being removed.
Next, as shown in Figures 5 and 6, forming floating gate material layer 109, the floating gate material layer on the substrate 101
The 109 fillings opening 108 simultaneously extends over the fleet plough groove isolation structure 107.It is flat using chemical machinery finally refering to Fig. 7
Smooth chemical industry skill removal is higher than the floating gate material layer 109 of the fleet plough groove isolation structure 107, makes remaining floating in the opening 108
Gate material layer 109 constitutes floating gate layer 110.It is understood that the size due to described hole 106 ' is larger, formed
When the floating gate material layer 109, the material of the floating gate material layer 109 can also enter in described hole 106 ', due to described floating
The material of gate material layer 109 is usually the conductive materials such as polysilicon, even if described hole 106 ' is filled with a small amount of conductive material,
Also the isolation performance that will affect the fleet plough groove isolation structure 107 causes the performance of the semiconductor storage unit to decline.
Based on this, the present invention provides a kind of forming method of fleet plough groove isolation structure and the forming method of memory device,
Substrate is provided and covers the mask layer of substrate, then the substrate of etch mask layer and segment thickness, to form at least one isolation
Groove；Filling isolated groove is formed using high-aspect-ratio technique and extends over the dielectric layer of mask layer, wherein the dielectric layer
Second dielectric layer including first medium layer and the covering first medium layer, the top surface of the first medium layer are higher than the lining
Bottom and the top surface for being lower than the mask layer, due to the flow of silicon-containing gas in the high-aspect-ratio technique of the formation second dielectric layer
Less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer, so in the notch of filling isolated groove
When neighbouring, since the flow of silicon-containing gas in high-aspect-ratio technique is smaller, filling capacity is preferable, can be avoided the slot of isolated groove
Hole is generated near mouthful, and then improves the performance of semiconductor storage unit.
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description,
Advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate
Ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As shown in figure 8, present embodiments providing a kind of forming method of fleet plough groove isolation structure, comprising:
Step S1: a substrate is provided, is formed with a mask layer on the substrate；
Step S2: etching the substrate of the mask layer and segment thickness, in the substrate and the mask layer
Form at least one isolated groove；
Step S3: dielectric layer is formed using high-aspect-ratio technique, the dielectric layer, which is filled the isolated groove and extended, to be covered
Cover the mask layer, wherein the dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, institute
The top surface for stating first medium layer is higher than the substrate and is lower than the top surface of the mask layer, and forms the height of the second dielectric layer
The flow of silicon-containing gas is less than the stream of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer in depth-to-width ratio technique
Amount.
Specifically, please referring to Fig. 9-Figure 14, partly led for what is formed using the forming method of the fleet plough groove isolation structure
The diagrammatic cross-section of body structure, next, formation of Fig. 9-Figure 14 to fleet plough groove isolation structure provided in this embodiment will be combined
Method elaborates.
Firstly, referring to Fig. 9, execution step S1, provides a substrate 201, has defined in the substrate 201 multiple active
Area (not shown), each active area is from the top of the substrate 201 to the internal stretch of the substrate 201 to the lining
The certain depth at bottom 201 can form source region and drain region (not shown) in the active area, into one by modes such as ion implantings
Step, the doping type in the source region and drain region can be determined according to the type for being formed by semiconductor storage unit.The substrate
A pad oxide 202 and mask layer 203 are formed on 201, the pad oxide 202 covers the substrate 201, the mask layer
The 203 covering pad oxides 202.The material of the pad oxide 202 can be silica etc., to play alleviation stress, increase
The material of the effect of adhesion strength between blooming layer, the mask layer 203 can be silicon nitride etc., can be used for etch stopper
Or grinding blocking etc..The height H2 (thickness) of the mask layer 203 in the vertical direction depends on the subsequent floating gate needed to form
Thickness (namely in the semiconductor storage unit formed as needed mask layer 203 described in the thickness design of floating gate vertical
Height H2 on direction).
Next, referring to Fig. 10, execution step S2, etches the mask layer 203, pad oxide 202 and segment thickness
The substrate 201, to form at least one isolated groove 204 in the substrate 201 and the mask layer 203, that is,
It says, the isolated groove 204 runs through the mask layer 203 and extends to the inside of the substrate 201, the isolated groove 204
Quantity and the semiconductor storage unit that can be formed according to actual needs of size be designed and (only schematically shown in figure
Two isolated grooves 204).Optionally, the depth-to-width ratio of the isolated groove 204 is greater than or equal to 3.
Then, Figure 11-Figure 13 is please referred to, step S3 is executed, forms dielectric layer using high-aspect-ratio technique (HARP technique)
205, the dielectric layer 205 fills the isolated groove 204 and extends over the mask layer 203, in the present embodiment, is given an account of
The material of matter layer 205 is silica, it should be appreciated that in other embodiments, the dielectric layer 205 can also be other medium materials
Material.In the present embodiment, the high-aspect-ratio technique be in HARP board, using silicon-containing gas (e.g. ethyl orthosilicate,
) and ozone (O TEOS3) generation silica is reacted to fill the isolated groove 204.Specifically, as shown in figure 11, firstly, adopting
First medium layer 2051 is formed with high-aspect-ratio technique, the first medium layer 2051 is located in the isolated groove 204, and institute
The top surface for stating first medium layer 2051 is higher than the surface of the substrate 201 and is lower than the top surface of the mask layer 203.Further,
When forming the first medium layer 2051, in the high-aspect-ratio technique flow of silicon-containing gas can between 1mg/s~
Between 1.5mg/s, e.g. 1.1mg/s, 1.2mg/s or 1.4mg/s, under this range of flow, the first medium layer 2051
Film quality preferably and formed the first medium layer 2051 rate it is also very fast.
Then as shown in figure 12, formed after the first medium layer 2051, reduce the siliceous of the high-aspect-ratio technique
The flow of gas, for example, by the flow-reduction of the silicon-containing gas in the high-aspect-ratio technique between 0.6mg/s~0.8mg/
Between s, to form second dielectric layer 2052, the second dielectric layer 2052 is located on the first medium layer 2051, with filling
The remaining isolated groove 204 simultaneously extends over the mask layer 203.Due to reducing the siliceous of the high-aspect-ratio technique
The film quality of the flow of gas, the second dielectric layer 2052 is better than the film quality of the first medium layer 2051, can be with
Avoid occurring porosity defects in the second dielectric layer 2052, also, due to only forming the second dielectric layer 2052
When reduce the high-aspect-ratio technique silicon-containing gas flow, yield will not be influenced by excessive.
Further, it has been investigated that, when using isolated groove 204 described in high-aspect-ratio process filling, hole can be described
The notch of isolated groove 204 nearby occurs, specifically, the bottommost of hole is located approximately at the mask layer 203 in the vertical direction
Height H2 3/5 position at, the top of hole is about higher by the top surface 3/10 of the mask layer 203, in order to avoid institute as far as possible
It states first medium layer 2051 and porosity defects does not occur, and the second dielectric layer 2052 can cover the area for generating hole as far as possible
Domain, in the present embodiment, the top surface of the first medium layer 2051 can be located at the height of the mask layer 203 in the vertical direction
3/10~2/5 at (i.e. H3=(3/10~2/5) H2), the top surface of the second dielectric layer 2052 is higher than the mask layer 203
Top surface 3/10~2/5 (i.e. H4=(3/10~2/5) H2).
Optionally, as shown in figure 13, leeway, the present embodiment are processed in order to stop for subsequent CMP process
In, it is formed after the second dielectric layer 2052, the flow of the silicon-containing gas of the high-aspect-ratio technique can also be increased, such as
It is to be increased to 8mg/s~12mg/s, quickly to form third dielectric layer 2053, the first medium layer 2051, second dielectric layer
2052 and third dielectric layer 2053 constitute dielectric layer 205.The height of the third dielectric layer 2053 in the vertical direction depends on
The height of the dielectric layer 205 needed to form in the vertical direction, at this point, the flow of the silicon-containing gas of the high-aspect-ratio technique is very
Greatly, the rate for forming the third dielectric layer 2053 quickly, has saved the time of preparation.The film layer of the third dielectric layer 2053
Quality is also poor, but since the third dielectric layer 2053 can be removed in subsequent CMP process, institute
With unimportant the film quality of the third dielectric layer 2053 is poor.
Further, it is formed after the dielectric layer 205, planarizes the dielectric layer 205 to 203 top surface of mask layer,
So that the remaining dielectric layer 205 constitutes fleet plough groove isolation structure in the isolated groove 204 and the isolated groove 204
207, it is specific as shown in figure 14.It is understood that using the forming method shape of fleet plough groove isolation structure provided in this embodiment
At the fleet plough groove isolation structure 207 in do not have a porosity defects, the corrosion resistance of the fleet plough groove isolation structure 207 and
Isolating power is preferable.
Based on this, as shown in Fig. 9-Figure 17, the present embodiment additionally provides a kind of forming method of memory device, including first
Corrosion resistance is formed using the forming method of the fleet plough groove isolation structure as shown in Fig. 9-Figure 14 and isolating power is preferable
Fleet plough groove isolation structure 207.
Next, please referring to Figure 15, after forming the fleet plough groove isolation structure 207, institute is removed using wet etching
Mask layer 203 is stated to form several openings 208, since the corrosion resistance of the fleet plough groove isolation structure 207 is good, wet etching
When removing the mask layer 203, the fleet plough groove isolation structure 207 will not be impacted.Next, as shown in figure 16, described
Floating gate material layer 209 is formed on substrate 201, the floating gate material layer 209 fills the opening 208 and extends over the shallow ridges
Recess isolating structure 207.Finally, as shown in figure 17, removal floating gate material layer 209 is higher than the portion of the fleet plough groove isolation structure 207
Point, retain the floating gate material layer 209 in the opening 208 to constitute floating gate layer 210.It is understood that due to the shallow ridges
The top of recess isolating structure 207 does not have porosity defects, and when forming the floating gate material layer 209, the floating gate material layer 209 is led
Electric material will not enter the isolation performance that the fleet plough groove isolation structure 207 is influenced in the fleet plough groove isolation structure 207, thus
Improve the performance for the semiconductor storage unit to be formed.
To sum up, in the forming method of fleet plough groove isolation structure provided in an embodiment of the present invention and the forming method of memory device
In, comprising: substrate is provided and covers the mask layer of substrate, then the substrate of etch mask layer and segment thickness, to be formed at least
One isolated groove；Filling isolated groove is formed using high-aspect-ratio technique and extends over mask layer dielectric layer, wherein described
Dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, and the top surface of the first medium layer is higher than
The substrate and the top surface for being lower than the mask layer, due to silicon-containing gas in the high-aspect-ratio technique of the formation second dielectric layer
Flow be less than the flow for forming silicon-containing gas in the high-aspect-ratio technique of the second dielectric layer, so in filling isolated groove
Notch near when, since the flow of silicon-containing gas in high-aspect-ratio technique is smaller, filling capacity is preferable, can be avoided isolating trenches
The notch of slot nearby generates hole, and then improves the performance of semiconductor storage unit, and due to being only in filling isolating trenches
The flow that silicon-containing gas in high-aspect-ratio technique is reduced when near the notch of slot, the influence to yield are also smaller.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. a kind of forming method of fleet plough groove isolation structure characterized by comprising
One substrate is provided, a mask layer is formed on the substrate；
The substrate of the mask layer and segment thickness is etched, to form at least one in the substrate and the mask layer
Isolated groove；
Dielectric layer is formed using high-aspect-ratio technique, the dielectric layer fills the isolated groove and extends over the mask
Layer, wherein the dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, the first medium
The top surface of layer is higher than the substrate and is lower than the top surface of the mask layer, and forms the high-aspect-ratio technique of the second dielectric layer
The flow of middle silicon-containing gas is less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer.
2. the forming method of fleet plough groove isolation structure as described in claim 1, which is characterized in that the material of the dielectric layer is
Silica, and the silicon-containing gas is ethyl orthosilicate.
3. the forming method of fleet plough groove isolation structure as claimed in claim 1 or 2, which is characterized in that form described first and be situated between
The flow of silicon-containing gas is between 1mg/s~1.5mg/s in the high-aspect-ratio technique of matter layer.
4. the forming method of fleet plough groove isolation structure as claimed in claim 3, which is characterized in that form the second dielectric layer
High-aspect-ratio technique in silicon-containing gas flow between 0.6mg/s~0.8mg/s.
5. the forming method of fleet plough groove isolation structure as claimed in claim 1 or 2, which is characterized in that the first medium layer
Top surface be located at the mask layer in the vertical direction height 3/10~2/5 at.
6. the forming method of fleet plough groove isolation structure as claimed in claim 1 or 2, which is characterized in that the second dielectric layer
Top surface between the top surface of the mask layer in the vertical direction at a distance between the mask layer in the vertical direction
Between the 3/10~2/5 of height.
7. the forming method of fleet plough groove isolation structure as described in claim 1, which is characterized in that formed the dielectric layer it
Afterwards, the forming method of the fleet plough groove isolation structure further include:
The dielectric layer is planarized to the mask layer top surface, so that remaining institute in the isolated groove and the isolated groove
It states dielectric layer and constitutes fleet plough groove isolation structure.
8. a kind of forming method of memory device characterized by comprising
One substrate is provided, a mask layer is formed on the substrate；
The substrate of the mask layer and segment thickness is etched, to form at least one in the substrate and the mask layer
Isolated groove；
Dielectric layer is formed using high-aspect-ratio technique, the dielectric layer fills the isolated groove and extends over the mask
Layer, wherein the dielectric layer includes the second dielectric layer of first medium layer and the covering first medium layer, the first medium
The top surface of layer is higher than the substrate and is lower than the top surface of the mask layer, and forms the high-aspect-ratio technique of the second dielectric layer
The flow of middle silicon-containing gas is less than the flow of silicon-containing gas in the high-aspect-ratio technique for forming the second dielectric layer.
9. the forming method of memory device as claimed in claim 8, which is characterized in that it is formed after the dielectric layer, it is described
The forming method of memory device further include:
The dielectric layer is planarized to the mask layer top surface, so that remaining institute in the isolated groove and the isolated groove
It states dielectric layer and constitutes fleet plough groove isolation structure.
10. the forming method of memory device as claimed in claim 9, which is characterized in that form the fleet plough groove isolation structure
Later, the forming method of the memory device further include:
The mask layer is removed to form several openings；
Floating gate material layer is formed over the substrate, and the floating gate material layer filling is described to be open and extend over the shallow trench
Isolation structure；
The part that floating gate material layer is higher than the fleet plough groove isolation structure is removed, retains the floating gate material layer in the opening with structure
At floating gate layer.
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| CN101231967A (en) * | 2007-01-26 | 2008-07-30 | 联华电子股份有限公司 | Shallow groove isolation layer of semiconductor element and manufacturing method thereof |
| US20160247921A1 (en) * | 2015-02-19 | 2016-08-25 | International Business Machines Corporation | Field-effect transistor with aggressively strained fins |
| CN105931982A (en) * | 2015-02-26 | 2016-09-07 | 台湾积体电路制造股份有限公司 | Method For Fabricating Shallow Trench Isolation And Semiconductor Structure Using The Same |
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| CN101231967A (en) * | 2007-01-26 | 2008-07-30 | 联华电子股份有限公司 | Shallow groove isolation layer of semiconductor element and manufacturing method thereof |
| US20160247921A1 (en) * | 2015-02-19 | 2016-08-25 | International Business Machines Corporation | Field-effect transistor with aggressively strained fins |
| CN105931982A (en) * | 2015-02-26 | 2016-09-07 | 台湾积体电路制造股份有限公司 | Method For Fabricating Shallow Trench Isolation And Semiconductor Structure Using The Same |
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| CN110739314A (en) * | 2019-10-23 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | Polysilicon resistance structure and manufacturing method thereof |
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