CN103530670A - Amplitude limiting circuit of antenna in electronic tag - Google Patents
Amplitude limiting circuit of antenna in electronic tag Download PDFInfo
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- CN103530670A CN103530670A CN201210225642.2A CN201210225642A CN103530670A CN 103530670 A CN103530670 A CN 103530670A CN 201210225642 A CN201210225642 A CN 201210225642A CN 103530670 A CN103530670 A CN 103530670A
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Abstract
The invention discloses an amplitude limiting circuit of an antenna in an electronic tag. The amplitude limiting circuit comprises a first N-channel enhanced field effect transistor, a second N-channel enhanced field effect transistor, a third N-channel enhanced field effect transistor, a fourth N-channel enhanced field effect transistor, a third resistor, a fourth resistor, a first capacitor and a second capacitor. The two ends of the second resistor are respectively connected in series with the third resistor and the fourth resistor and then are connected in parallel with the first capacitor so as to form a series-parallel circuit. One terminal, provided with the third resistor, of the series-parallel circuit is connected with a circuit between a drain electrode of the third N-channel enhanced field effect transistor and a drain electrode of the fourth N-channel enhanced field effect transistor; and the other terminal of the series-parallel circuit is grounded. Grid electrodes of the first N-channel enhanced field effect transistor and the second N-channel enhanced field effect transistor are connected with a circuit between the second capacitor and the fourth resistor. According to the scheme, the provided amplitude limiting circuit with the simple structure can be realized conveniently. Moreover, when the voltage amplitude limiting of the antenna is realized, the power is not influenced.
Description
Technical field
The present invention relates to radio-frequency technique field, specifically the amplitude limiter circuit of antenna in electronic tag.
Background technology
Radio-frequency (RF) identification is current application one of the most contactless Target Recognition, and it has the advantages such as noncontact, read-write is flexible, speed is fast, security is high, is therefore widely used in every field.Radio-frequency recognition system mainly comprises reader and electronic tag, the energy that electronic tag receives reader can be affected by the angle between operating distance and reader antenna, the voltage that electronic tag senses may be larger, so must there be independent modular circuit to realize amplitude limit, by limiting voltage within limits, breakdown to prevent receiving metal-oxide-semiconductor grid.The simplest directly measure of amplitude limit is to reduce coupling coefficient, people usually reduce coupling coefficient by the operating distance of adjustment reader and electronic tag or the input capacitance of adjustment electronic tag now, wherein, adopting the operating distance of adjustment reader and electronic tag is to be difficult to hold for operating personnel, and the method does not gear to actual circumstances; Change the input capacitance of electronic tag, be to change resonance frequency, reduce coupling coefficient, the power transmitting in electronic tag also can reduce, in large scale integrated circuit design, the realization of electric capacity can take larger chip area, and the parameter of electric capacity is floated relatively large.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of convenient operation to control, simple in structure, and when carrying out voltage amplitude limit, can not affect the amplitude limiter circuit of antenna in the electronic tag of delivering power.
Object of the present invention is achieved through the following technical solutions: the amplitude limiter circuit of antenna in electronic tag, comprise a N channel enhancement field effect transistor, the 2nd N channel enhancement field effect transistor, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor, the 3rd resistance, the 4th resistance, the first electric capacity and the second electric capacity, the 3rd N channel enhancement field effect transistor is with the 4th N channel enhancement field effect transistor the metal-oxide-semiconductor that diode is connected, the drain electrode of described the 3rd N channel enhancement field effect transistor is connected with a N channel enhancement field effect transistor drain electrode with the 4th N channel enhancement field effect transistor drain electrode respectively with source electrode, the drain electrode of the 2nd N channel enhancement field effect transistor is connected with the 4th N channel enhancement field effect transistor source electrode, the one N channel enhancement field effect transistor source electrode and the 2nd N channel enhancement field effect transistor source grounding, connect respectively and form connection in series-parallel circuit with the first Capacitance parallel connection after the 3rd resistance and the 4th resistance in described the second electric capacity two ends, this connection in series-parallel circuit is provided with one end of the 3rd resistance and the connection between the drain electrode of the 3rd N channel enhancement field effect transistor and the 4th N channel enhancement field effect transistor utmost point, its other end ground connection, the connection of the grid of a described N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor all and between the second electric capacity and the 4th resistance, on circuit between a described N channel enhancement field effect transistor drain electrode and the 3rd N channel enhancement field effect transistor source electrode, be connected with the first antenna signal input part, on the circuit between the 2nd N channel enhancement field effect transistor drain electrode and the drain electrode of the 4th N channel enhancement field effect transistor, be connected with the second antenna signal input part.Wherein, the present invention is when application, and the first antenna signal input part and the second antenna signal input part are for external antenna.The metal-oxide-semiconductor that in the present invention, diode connects is that the grid of metal-oxide-semiconductor and source electrode are linked together, because metal-oxide-semiconductor exists leakage current under certain voltage, so the metal-oxide-semiconductor that in the present invention, diode connects is used for simulating the resistance that resistance is very large, and can realize the control to resistance by adjusting the parameter of metal-oxide-semiconductor.
On circuit between a described N channel enhancement field effect transistor drain electrode and the 3rd N channel enhancement field effect transistor source electrode, be connected with the first resistance; On circuit between described the 2nd N channel enhancement field effect transistor drain electrode and the 4th N channel enhancement field effect transistor source electrode, be connected with the second resistance.
Described the first antenna signal input part is connected on the circuit between the first resistance and N channel enhancement field effect transistor drain electrode; Described the second antenna signal input part is connected on the circuit between the second resistance and the drain electrode of the 2nd N channel enhancement field effect transistor.
The present invention is when application, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor and the first electric capacity are used for the radiofrequency signal of sampling, the one N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor are leak-off pipe, and a N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor are connected in parallel on antenna ends and carry out amplitude limit shunting.When the signal of sampling is during higher than datum, the electric current of the 4th resistance of flowing through increases, therefore the current potential of controlling a N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor grid improves, increase the ducting capacity of a N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor, the electric current of the N channel enhancement field effect transistor of flowing through and the 2nd N channel enhancement field effect transistor increases, reduce the service load of label antenna, thus the voltage amplitude of restriction aerial signal.The connection in series-parallel circuit that in the present invention, the 3rd resistance, the 4th resistance, the first electric capacity and the second electric capacity form is filter circuit, the conducting degree of this filter circuit feedback adjusting the one N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor, thus while guaranteeing that the present invention applies, voltage is stable.
Compared with prior art, the present invention has following beneficial effect: the present invention includes a N channel enhancement field effect transistor, the 2nd N channel enhancement field effect transistor, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor, the 3rd resistance, the 4th resistance, the first electric capacity and the second electric capacity, the present invention uses the quantity of electronic component few, one-piece construction is simple, while being integrated in module, volume is little, be convenient to realize, cost is low, and the present invention passes through to improve the grid voltage of a N channel enhancement field effect transistor and the second enhancement mode field effect transistor when application, can not exert an influence to power, at input voltage, make divided circuit conducting in parallel during higher than certain voltage value, make the electric current of circuit become large, thereby make voltage voltage stabilizing in certain scope.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of the present invention.
In accompanying drawing, the corresponding name of Reference numeral is called: N1-one N channel enhancement field effect transistor, N2-two N channel enhancement field effect transistor, N3-three N channel enhancement field effect transistor, N4-four N channel enhancement field effect transistor, C1-the first electric capacity, C2-the second electric capacity, R1-the first resistance, R2-the second resistance, R3-three resistance, R4-four resistance, Ant1-the first antenna signal input part, Ant2-the second antenna signal input part.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment:
As shown in Figure 1, the amplitude limiter circuit of antenna in electronic tag, comprise a N channel enhancement field effect transistor N1, the 2nd N channel enhancement field effect transistor N2, the 3rd N channel enhancement field effect transistor N3, the 4th N channel enhancement field effect transistor N4, the 3rd resistance R 3, the 4th resistance R 4, the first capacitor C 1 and the second capacitor C 2, wherein, the 3rd N channel enhancement field effect transistor N3 and the 4th N channel enhancement field effect transistor N4, the metal-oxide-semiconductor connecting at this diode is that the grid in metal-oxide-semiconductor is connected with source electrode.The drain electrode of the 3rd N channel enhancement field effect transistor N3 is connected with a N channel enhancement field effect transistor N1 drain electrode with the 4th N channel enhancement field effect transistor N4 drain electrode respectively with source electrode, the drain electrode of the 2nd N channel enhancement field effect transistor N2 is connected with the 4th N channel enhancement field effect transistor N4 source electrode, a N channel enhancement field effect transistor N1 source electrode and the 2nd N channel enhancement field effect transistor N2 source grounding.Connect respectively after the 3rd resistance R 3 and the 4th resistance R 4 and the first capacitor C 1 formation in parallel connection in series-parallel circuit in the second capacitor C 2 two ends, this connection in series-parallel circuit is provided with one end of the 3rd resistance R 3 and the connection between the 3rd N channel enhancement field effect transistor N3 drain electrode and the 4th N channel enhancement field effect transistor N4 drain electrode, its other end ground connection.The connection of the grid of the one N channel enhancement field effect transistor N1 and the 2nd N channel enhancement field effect transistor N2 all and between the second capacitor C 2 and the 4th resistance R 4.
On circuit between the one N channel enhancement field effect transistor N1 drain electrode and the 3rd N channel enhancement field effect transistor N3 source electrode, be connected with on the circuit between the first resistance R 1, the first resistance R 1 and N channel enhancement field effect transistor N1 drain electrode and be connected with the first antenna signal input part Ant1.On circuit between the 2nd N channel enhancement field effect transistor N2 drain electrode and the 4th N channel enhancement field effect transistor N4 source electrode, be connected with on the circuit between the second resistance R 2, the second resistance R 2 and the 2nd N channel enhancement field effect transistor N2 drain electrode and be connected with the second antenna signal input part Ant2.
As mentioned above, can well realize the present invention.
Claims (3)
1. the amplitude limiter circuit of antenna in electronic tag, it is characterized in that: comprise a N channel enhancement field effect transistor (N1), the 2nd N channel enhancement field effect transistor (N2), the 3rd N channel enhancement field effect transistor (N3), the 4th N channel enhancement field effect transistor (N4), the 3rd resistance (R3), the 4th resistance (R4), the first electric capacity (C1) and the second electric capacity (C2), the 3rd N channel enhancement field effect transistor (N3) is with the 4th N channel enhancement field effect transistor (N4) metal-oxide-semiconductor that diode is connected, the drain electrode of described the 3rd N channel enhancement field effect transistor (N3) is connected with N channel enhancement field effect transistor (N1) drain electrode with the 4th N channel enhancement field effect transistor (N4) drain electrode respectively with source electrode, the drain electrode of the 2nd N channel enhancement field effect transistor (N2) is connected with the 4th N channel enhancement field effect transistor (N4) source electrode, the one N channel enhancement field effect transistor (N1) source electrode and the 2nd N channel enhancement field effect transistor (N2) source grounding, connect respectively after the 3rd resistance (R3) and the 4th resistance (R4) and the first electric capacity (C1) formation in parallel connection in series-parallel circuit in described the second electric capacity (C2) two ends, this connection in series-parallel circuit is provided with one end of the 3rd resistance (R3) and the connection between the drain electrode of the 3rd N channel enhancement field effect transistor (N3) and the drain electrode of the 4th N channel enhancement field effect transistor (N4), its other end ground connection, a described N channel enhancement field effect transistor (N1) and the connection of the 2nd both grids of N channel enhancement field effect transistor (N2) all and between the second electric capacity (C2) and the 4th resistance (R4), on circuit between described N channel enhancement field effect transistor (N1) drain electrode and the 3rd N channel enhancement field effect transistor (N3) source electrode, be connected with the first antenna signal input part (Ant1), on the circuit between the 2nd N channel enhancement field effect transistor (N2) drain electrode and the drain electrode of the 4th N channel enhancement field effect transistor (N4), be connected with the second antenna signal input part (Ant2).
2. the amplitude limiter circuit of antenna in electronic tag according to claim 1, is characterized in that: on the circuit between described N channel enhancement field effect transistor (N1) drain electrode and the 3rd N channel enhancement field effect transistor (N3) source electrode, be connected with the first resistance (R1); On circuit between described the 2nd N channel enhancement field effect transistor (N2) drain electrode and the 4th N channel enhancement field effect transistor (N4) source electrode, be connected with the second resistance (R2).
3. the amplitude limiter circuit of antenna in electronic tag according to claim 2, is characterized in that: described the first antenna signal input part (Ant1) is connected on the circuit between the first resistance (R1) and a N channel enhancement field effect transistor (N1) drain electrode; Described the second antenna signal input part (Ant2) is connected on the circuit between the second resistance (R2) and the drain electrode of the 2nd N channel enhancement field effect transistor (N2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210225642.2A CN103530670A (en) | 2012-07-03 | 2012-07-03 | Amplitude limiting circuit of antenna in electronic tag |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210225642.2A CN103530670A (en) | 2012-07-03 | 2012-07-03 | Amplitude limiting circuit of antenna in electronic tag |
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| Publication Number | Publication Date |
|---|---|
| CN103530670A true CN103530670A (en) | 2014-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210225642.2A Pending CN103530670A (en) | 2012-07-03 | 2012-07-03 | Amplitude limiting circuit of antenna in electronic tag |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040036576A1 (en) * | 1998-09-17 | 2004-02-26 | Intermec Ip Corp | Reference circuit enhancement for passive RFID tags |
| CN102244502A (en) * | 2011-04-25 | 2011-11-16 | 胡建国 | Automatic Q value adjustment amplitude limiting circuit |
| CN202677431U (en) * | 2012-07-03 | 2013-01-16 | 成都市宏山科技有限公司 | Amplitude limit circuit of antenna in electronic tag |
-
2012
- 2012-07-03 CN CN201210225642.2A patent/CN103530670A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040036576A1 (en) * | 1998-09-17 | 2004-02-26 | Intermec Ip Corp | Reference circuit enhancement for passive RFID tags |
| CN102244502A (en) * | 2011-04-25 | 2011-11-16 | 胡建国 | Automatic Q value adjustment amplitude limiting circuit |
| CN202677431U (en) * | 2012-07-03 | 2013-01-16 | 成都市宏山科技有限公司 | Amplitude limit circuit of antenna in electronic tag |
Non-Patent Citations (1)
| Title |
|---|
| 位召勤: "《电子标签芯片射频接口电路研究与设计》", 《中国优秀硕士学位论文全文数据库》, no. 6, 31 December 2007 (2007-12-31) * |
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Application publication date: 20140122 |