CN202632345U - Antenna amplitude-limit circuit for electronic tags in radio frequency system - Google Patents
Antenna amplitude-limit circuit for electronic tags in radio frequency system Download PDFInfo
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- CN202632345U CN202632345U CN 201220316348 CN201220316348U CN202632345U CN 202632345 U CN202632345 U CN 202632345U CN 201220316348 CN201220316348 CN 201220316348 CN 201220316348 U CN201220316348 U CN 201220316348U CN 202632345 U CN202632345 U CN 202632345U
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Abstract
The utility model discloses an antenna amplitude-limit circuit for electronic tags in a radio frequency system. The antenna amplitude-limit circuit comprises a first N-channel field effect reinforcing tube, a second N-channel field effect reinforcing tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor and a second capacitor, wherein both ends of the first resistor are respectively connected with the drain electrode of the first N-channel field effect reinforcing tube and the second resistor; the second resistor is connected with the drain electrode of the second N-channel field effect reinforcing tube; the second capacitor is connected with the third resistor and the fourth resistor and then connected with the first capacitor in parallel to form a circuit in a serial and parallel connection; the end of the circuit in a serial and parallel connection is provided with a circuit connection between one end of the third resistor, the first resistor and the second resistor; and grid electrodes of the first N-channel field effect reinforcing tube and the second N-channel field effect reinforcing tube are connected with the circuit between the second capacitor and the fourth resistor. By adopting the structure provided by the utility model, the antenna amplitude-limit circuit for electronic tags in a radio frequency system has the advantages that the whole structure is simple and is easy to realize, and the power cannot be influenced when limiting the voltage amplitude of the antenna.
Description
Technical field
The utility model relates to the radio-frequency technique field, specifically is the antenna amplitude limiter circuit of electronic tag in the radio system.
Background technology
RF identification is current application one of the most non-contact automatic target identification technology, and therefore advantages such as it has noncontact, read-write is flexible, speed is fast, security height are widely used in every field.Radio-frequency recognition system mainly comprises reader and electronic tag; The energy that electronic tag receives reader can receive the angle between operating distance and the reader antenna; The voltage that electronic tag is sensed may be bigger; So must there be independent modular circuit to realize amplitude limit, with voltage limit within limits, breakdown to prevent the receiving metal-oxide-semiconductor grid.The simplest directly measure of amplitude limit is to reduce coupling coefficient; People usually reduce coupling coefficient through the operating distance of adjusting reader and electronic tag or the input capacitance of adjusting electronic tag now; Wherein, Adopting the operating distance of adjustment reader and electronic tag is to be difficult to hold for operating personnel, and this method does not gear to actual circumstances; Change the input capacitance of electronic tag; Promptly be to change resonance frequency, reduce coupling coefficient, the power that transmits in the electronic tag also can reduce; The realization of electric capacity can take bigger chip area in VLSI Design, and the parameter of electric capacity is floated relatively large.
The utility model content
The purpose of the utility model is to overcome the deficiency of prior art, provides a kind of being convenient to control, and is simple in structure, and when carrying out the voltage amplitude limit, can not influence the antenna amplitude limiter circuit of electronic tag in the radio system of delivering power.
The purpose of the utility model mainly realizes through following technical scheme: the antenna amplitude limiter circuit of electronic tag in the radio system; Comprise a N channel enhancement FET, the 2nd N channel enhancement FET, first resistance, second resistance, the 3rd resistance, the 4th resistance, first electric capacity and second electric capacity; The two ends of said first resistance are connected with second resistance with the drain electrode of a N channel enhancement FET respectively; The other end that second resistance connects first resistance terminal relatively is connected with the drain electrode of the 2nd N channel enhancement FET; The one N channel enhancement FET source electrode and the 2nd N channel enhancement FET source grounding; Connect respectively behind the 3rd resistance and the 4th resistance and the parallelly connected formation of first electric capacity SP circuit in the said second electric capacity two ends; This SP circuit is provided with an end of the 3rd resistance and is connected with circuit between first resistance and second resistance; Its other end ground connection, the grid of a said N channel enhancement FET and the 2nd N channel enhancement FET all with second electric capacity and the 4th resistance between circuit be connected.
Be connected with the first aerial signal input end on the circuit between said first resistance and the N channel enhancement FET drain electrode, be connected with the second aerial signal input end on the circuit between second resistance and the drain electrode of the 2nd N channel enhancement FET.The utility model is convenient to and external antenna through the first aerial signal input end and the second aerial signal input end are set.
Said first resistance and second resistance are adjustable resistance.The utility model can be through regulating and control to change the limiting voltage of the utility model to the resistance of first resistance and second resistance, thereby easy to operate when making the utility model change limiting voltage.
The utility model is when using; First resistance, second resistance and first electric capacity are used to the radiofrequency signal of sampling; The one N channel enhancement FET and the 2nd N channel enhancement FET are leak-off pipe, and a N channel enhancement FET and the 2nd N channel enhancement FET are connected in parallel on antenna ends and carry out the amplitude limit shunting.When the signal of sampling is higher than datum; The electric current of the 4th resistance of flowing through increases; Therefore the current potential of controlling a N channel enhancement FET and the 2nd N channel enhancement FET grid improves; Increase the ducting capacity of a N channel enhancement FET and the 2nd N channel enhancement FET; The electric current of a N channel enhancement FET and the 2nd N channel enhancement FET of flowing through increases, and reduces the service load of label antenna, thus the voltage amplitude of restriction aerial signal.The SP circuit that the 3rd resistance, the 4th resistance, first electric capacity and second electric capacity constitute in the utility model is a filter circuit; The conducting degree of this filter circuit feedback adjustment the one N channel enhancement FET and the 2nd N channel enhancement FET, thus voltage is stable when guaranteeing that the utility model is used.
Compared with prior art; The utlity model has following beneficial effect: the utility model comprises a N channel enhancement FET, the 2nd N channel enhancement FET, first resistance, second resistance, the 3rd resistance, the 4th resistance, first electric capacity and second electric capacity; The utility model uses the quantity of electronic component few, and one-piece construction is simple, and volume is little when being integrated on the module; Be convenient to realize, cost is low; And the utility model through improving the grid voltage of a N channel enhancement FET and the second enhancement mode FET, can not exert an influence to power when using, and when input voltage is higher than certain voltage value, makes parallelly connected divided circuit conducting; Make the electrorheological of circuit big, thereby make the voltage voltage stabilizing in certain scope.
Description of drawings
Fig. 1 is the structural representation of the utility model embodiment.
The pairing name of Reference numeral is called in the accompanying drawing: N1-the one N channel enhancement FET, N2-the 2nd N channel enhancement FET, C1-first electric capacity; C2-second electric capacity, R1-first resistance, R2-second resistance; R3-the 3rd resistance; R4-the 4th resistance, Ant1-first aerial signal input end, Ant2-second aerial signal input end.
Embodiment
Below in conjunction with embodiment and accompanying drawing the utility model is done further to specify, but the embodiment of the utility model is not limited thereto.
Embodiment:
As shown in Figure 1; The antenna amplitude limiter circuit of electronic tag in the radio system; Comprise a N channel enhancement FET N1, the 2nd N channel enhancement FET N2, first resistance R 1, the second resistance N2, the 3rd resistance R 3, the 4th resistance R 4, first capacitor C 1 and second capacitor C 2; Wherein, first resistance R 1, second resistance R 2 and the 3rd resistance R 3 are adjustable resistance.The two ends of first resistance R 1 are connected with second resistance R 2 with the drain electrode of a N channel enhancement FET N1 respectively; The other end that second resistance R 2 connects first resistance R, 1 end relatively is connected a N channel enhancement FET N1 source electrode and the 2nd N channel enhancement FET N2 source grounding with the drain electrode of the 2nd N channel enhancement FET N2.Second capacitor C, 2 two ends connect respectively the 3rd resistance R 3 and the 4th resistance R 4 back and first capacitor C, 1 parallelly connected formation SP circuits; This SP circuit is provided with an end of the 3rd resistance R 3 and is connected its other end ground connection with circuit between first resistance R 1 and second resistance R 2.The grid of the one N channel enhancement FET N1 and the 2nd N channel enhancement FET N2 all with second capacitor C 2 and the 4th resistance R 4 between circuit be connected.
For the ease of external antenna; Be connected with the first aerial signal input end Ant1 on the circuit between first resistance R 1 and the N channel enhancement FET N1 drain electrode, be connected with the second aerial signal input end Ant2 on the circuit between second resistance R 2 and the 2nd N channel enhancement FET N2 drain electrode.
As stated, then can well realize the utility model.
Claims (3)
1. the antenna amplitude limiter circuit of electronic tag in the radio system; It is characterized in that: comprise a N channel enhancement FET (N1), the 2nd N channel enhancement FET (N2), first resistance (R1), second resistance (N2), the 3rd resistance (R3), the 4th resistance (R4), first electric capacity (C1) and second electric capacity (C2); The two ends of said first resistance (R1) are connected with second resistance (R2) with the drain electrode of a N channel enhancement FET (N1) respectively; The other end that second resistance (R2) connects first resistance (R1) end relatively is connected with the drain electrode of the 2nd N channel enhancement FET (N2); The one N channel enhancement FET (N1) source electrode and the 2nd N channel enhancement FET (N2) source grounding; Said second electric capacity (C2) two ends connect respectively the 3rd resistance (R3) and the 4th resistance (R4) back and the parallelly connected formation of first electric capacity (C1) SP circuit; This SP circuit is provided with an end of the 3rd resistance (R3) and is connected with circuit between first resistance (R1) and second resistance (R2); Its other end ground connection, a said N channel enhancement FET (N1) and the 2nd both grids of N channel enhancement FET (N2) all with second electric capacity (C2) and the 4th resistance (R4) between circuit be connected.
2. the voltage amplitude limit module of antenna in the radio-frequency recognition system according to claim 1; It is characterized in that: be connected with the first aerial signal input end (Ant1) on the circuit between said first resistance (R1) and a N channel enhancement FET (N1) drain electrode, be connected with the second aerial signal input end (Ant2) on the circuit between second resistance (R2) and the drain electrode of the 2nd N channel enhancement FET (N2).
3. the voltage amplitude limit module of antenna in the radio-frequency recognition system according to claim 1 and 2 is characterized in that: said first resistance (R1) and second resistance (R2) are adjustable resistance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN 201220316348 CN202632345U (en) | 2012-07-03 | 2012-07-03 | Antenna amplitude-limit circuit for electronic tags in radio frequency system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 201220316348 CN202632345U (en) | 2012-07-03 | 2012-07-03 | Antenna amplitude-limit circuit for electronic tags in radio frequency system |
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CN202632345U true CN202632345U (en) | 2012-12-26 |
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CN 201220316348 Expired - Fee Related CN202632345U (en) | 2012-07-03 | 2012-07-03 | Antenna amplitude-limit circuit for electronic tags in radio frequency system |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103530677A (en) * | 2012-07-03 | 2014-01-22 | 成都市宏山科技有限公司 | Antenna amplitude limiting circuit of electronic tag in radio frequency system |
-
2012
- 2012-07-03 CN CN 201220316348 patent/CN202632345U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103530677A (en) * | 2012-07-03 | 2014-01-22 | 成都市宏山科技有限公司 | Antenna amplitude limiting circuit of electronic tag in radio frequency system |
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Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121226 Termination date: 20130703 |